CN112701156A - Back gate transistor and preparation method thereof - Google Patents
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- CN112701156A CN112701156A CN202011606191.8A CN202011606191A CN112701156A CN 112701156 A CN112701156 A CN 112701156A CN 202011606191 A CN202011606191 A CN 202011606191A CN 112701156 A CN112701156 A CN 112701156A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
Abstract
The present invention provides a back gate transistor, comprising: the periodic hole substrate consists of a silicon substrate and a dielectric layer on the surface of the silicon substrate, and the surface of the dielectric layer is provided with a periodic hole array; the source electrode is positioned on the periodic hole substrate; the drain electrode is positioned on the periodic hole substrate and is separated from the source electrode on two sides of a hole; a gate electrode which is suspended beta-Ga2O3And the nano belt is connected with the source electrode and the drain electrode. The invention solves the problem of beta-Ga2O3Difficult to be applied to the channel material and provides a back gate transistor with high performance.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a back gate transistor and a preparation method thereof.
Background
In recent years, wide bandgap semiconductor beta-Ga2O3The material has high critical breakdown field strength, ultra-large forbidden band width, good thermal stability and chemical inertness, and thus has received extensive attention from researchers. High quality of beta-Ga2O3The substrate can be applied to high-temperature, high-voltage and high-power electronic equipmentAnd (4) preparing. Combined about 300cm2V-1s-1Carrier mobility of beta-Ga2O3Exhibits a large Baliga figure of merit (BFOM, about 3444), much higher than the same type of materials SiC and GaN. This results in beta-Ga2O3Becoming an ideal choice for the next generation of power electronic devices. At present, researchers have reported a variety of simple and low-cost beta-Ga2O3The single crystal growth method includes, for example, the mode-guiding method, the floating region method, and the Bridgman method. beta-Ga2O3The effective electron concentration of the single crystal material can be 1016-1019cm-3Effective modulation is achieved in this wide interval. Furthermore, beta-Ga is compared to other wide band gap materials2O3Another unique property of (a) is that quasi-two-dimensional β -Ga can be obtained by common tape stripping techniques2O3Nanosheets. All this leads to beta-Ga2O3Has wide feasibility in future application. However, since beta-Ga2O3The development of channel devices is still in the early stage of development and faces numerous technical difficulties. For example beta-Ga2O3The thermal conductivity of the material is obviously lower, and the flat SiO is generally used in the industry2/p++Si as substrate for two-dimensional (2D) and quasi 2D back gate transistors, and SiO2The thickness of the gate dielectric layer is 285-300nm, which will aggravate beta-Ga2O3The heat dissipation problem of the device influences the high-temperature working state of the device. In addition, gate dielectrics/beta-Ga are also present2O3The interface trap density between channels. Gate dielectric and beta-Ga2O3The interfacial characteristics between channel layers may significantly affect Ga2O3Channel transport, field effect mobility, threshold voltage stability of the base device, and reliability of the transistor.
In recent years, in order to research the physical properties of channel materials and avoid the influence of the defects on the channel by the surface of the substrate, researchers have proposed the concept of a suspended device in the field of 2D material devices, that is, the channel material of a transistor is suspended and prevented from being in complete contact with a dielectric layer at the bottom. Chen and Lodha et al developed partially suspended Mo using the same device process, respectivelyS2And ReS2Back gate Field Effect Transistors (FETs). They had previously been made of smooth SiO2(300-nm)/p++Preparing source and drain electrodes on a Si substrate, and then directly transferring a channel material onto the two electrodes in a dry method. The prepared suspended FET has good ohmic contact and shows better electrical and photoelectric properties.
However, since beta-Ga2O3Having an ultra-wide bandgap, requiring subsequent annealing to form ohmic contacts, the device process described above tends to result in β -Ga2O3Large contact resistance, which affects the transistor performance, is not suitable for beta-Ga applications2O3Over the channel material.
Disclosure of Invention
The technical problem to be solved by the invention is that beta-Ga2O3The problem that the transistor is difficult to be applied to channel materials and prepare a high-efficiency transistor is solved, and the back gate transistor and the preparation method thereof are provided.
In order to solve the above problem, the present invention provides a back gate transistor comprising: the periodic hole substrate consists of a silicon substrate and a dielectric layer on the surface of the silicon substrate, and the surface of the dielectric layer is provided with a periodic hole array; the source electrode is positioned on the periodic hole substrate; the drain electrode is positioned on the periodic hole substrate and is separated from the source electrode on two sides of a hole; a gate electrode which is suspended beta-Ga2O3And the nano belt is connected with the source electrode and the drain electrode.
In order to solve the above problems, the present invention also provides a method for preparing a back gate transistor, comprising the following steps: providing a substrate, wherein the substrate consists of a silicon substrate and a dielectric layer on the surface of the silicon substrate; etching the substrate to form a periodic hole substrate with a periodic hole array; reacting beta-Ga2O3Transferring the nanobelt to one hole of the periodic hole substrate; etching the periodic hole substrate to form a hole in the beta-Ga2O3Photoetching patterns of source and drain electrodes on two sides of the nanobelt; depositing on the lithographic patternA metal stack to form a source and a drain of the transistor; annealing in N2 atmosphere.
The invention solves the problem of beta-Ga2O3Difficult to be applied to the channel material and provides a back gate transistor with high performance.
Drawings
FIG. 1 is a schematic diagram illustrating the steps of one embodiment of the present invention.
FIGS. 2A-2E are schematic views of the process of steps S10-S14 shown in FIG. 1.
FIG. 3 is an optical microscope image of a periodic hole substrate according to one embodiment of the present invention.
FIG. 4 shows beta-Ga transferred to a periodic pore substrate according to one embodiment of the present invention2O3Optical microscopy images of nanoribbons.
Fig. 5 is an optical microscope image of a back gate transistor according to an embodiment of the present invention.
Fig. 6 is a current-voltage electrical measurement image of a back gate transistor according to an embodiment of the present invention.
Fig. 7A-7F are schematic views of a periodic hole substrate process according to an embodiment of the invention.
Detailed Description
The following describes in detail a back-gate transistor and a method for manufacturing the back-gate transistor according to embodiments of the present invention with reference to the drawings.
FIG. 1 is a schematic diagram illustrating the steps of an embodiment of the present invention, including: step S10, providing a base, wherein the base is composed of a silicon substrate and a dielectric layer on the surface of the silicon substrate; step S11, etching the substrate to form a periodic hole substrate with a periodic hole array; step S12, adding beta-Ga2O3Transferring the nanobelt to one hole of the periodic hole substrate; step S13, etching the periodic hole substrate to form a hole in the beta-Ga2O3Photoetching patterns of source and drain electrodes on two sides of the nanobelt; step S14, depositing a metal stack on the photoetching pattern to formA source and a drain of the transistor; step S15, at N2And annealing in the atmosphere.
Referring to step S10, as shown in fig. 2A, a base 21 is provided, where the base 21 is composed of a silicon substrate 201 and a dielectric layer 202 on a surface of the silicon substrate 201. In one embodiment of the present invention, the silicon substrate 201 is a heavily doped P-type silicon substrate, and the dielectric layer 202 is SiO with a thickness of 110nm2A layer of material.
Referring to step S11, as shown in fig. 2B, the substrate 21 is etched to form a periodic hole substrate 22 with a periodic hole array. In one embodiment of the present invention, the holes of the periodic array of holes have a diameter of 5 μm and a depth that can be modulated by varying the reactive ion etching time; the distance between adjacent 5 x 5 circular arrays was 100 μm, and the pitch of adjacent circles in each array was 10 μm.
To more clearly show the structure of the periodic hole substrate 22, image scanning was performed using a scanning electron microscope. FIG. 3 is an optical microscope image of a periodic hole substrate according to an embodiment of the present invention.
Referring to step S12, shown in FIG. 2C, the beta-Ga is mixed2O3The nanoribbon 203 is transferred to one of the holes of the periodic hole substrate 22. In one embodiment of the present invention, the above transfer step is accomplished using a two-dimensional material transfer platform, the beta-Ga2O3Nanobelt 203 from beta-Ga using 3M adhesive tape2O3Mechanically peeling the monocrystalline block; the beta-Ga2O3The effective carrier concentration of the single crystal bulk is 1017-1019cm-3。
To more clearly express beta-Ga2O3The transfer position of the nanobelt 203 was image-scanned using a scanning electron microscope. FIG. 4 shows beta-Ga transferred to a periodic hole substrate according to one embodiment of the present invention2O3Optical microscope image of nanoribbon 203.
Referring to step S13, as shown in FIG. 2D, the periodic hole substrate 22 is etched to form a hole pattern in the beta-Ga2O3The source and drain electrode photo- etching patterns 204, 205 on both sides of the nanoribbon 203, in a specific embodiment of the present invention, the boxes marked by the dotted lines are the photo- etching patterns 204, 205.
Referring to step S14, shown in fig. 2E, a metal stack is deposited on the lithographic patterns 204, 205 to form the source 206 and drain 207 of the transistor. In one embodiment of the present invention, the source electrode 206 and the drain electrode 207 are formed by depositing a metal stack by electron beam evaporation, wherein the metal stack comprises a metal Ti layer, a metal Al layer, a metal Ni layer, and a metal Au layer, and the thicknesses of the metal stack are 20nm, 100nm, 40nm, and 80nm, respectively, and the forming temperature is 50 ℃.
Step S15, at N2And annealing in the atmosphere. In one embodiment of the invention, the annealing process uses a rapid thermal annealing apparatus at N2Annealing in the atmosphere to realize good ohmic contact of the transistor, wherein the annealing temperature is 470 ℃ and the annealing time is 70 s.
After the above steps are completed, a back gate transistor according to an embodiment of the present invention is obtained, where a structure of the back gate transistor is shown in fig. 2E, and includes: a periodic hole base 22, wherein the periodic hole base 22 is composed of a silicon substrate 201 and a dielectric layer 202 on the surface of the silicon substrate 201, and the surface of the dielectric layer 202 is provided with a periodic hole array; a source 206, the source 206 being located on the periodic hole substrate 22; a drain electrode 207, wherein the drain electrode 207 is located on the periodic hole substrate 22 and separated from the source electrode 206 at two sides of a hole; a gate 203, the gate 203 being a floating beta-Ga2O3And a nanoribbon connecting the source 206 and the drain 207. In one embodiment of the present invention, the silicon substrate 201 is a heavily doped P-type silicon substrate, and the dielectric layer 202 is SiO with a thickness of 110nm2A layer of material. The periodic holes on the substrate 22 are arranged in a 5 × 5 hole array, the distance between adjacent arrays is 100 μm, and the distance between adjacent holes in the arrays is 10 μm; the holes are circular holes with the diameter of 5 mu m.
Fig. 5 is an optical microscope image of a back gate transistor according to an embodiment of the present invention.
The electrical characteristics of the above samples were measured using a semiconductor device analyzer, as shown in FIG. 6, and the graph a on the left side shows the drain current-source drain voltage (I) of the transistord-Vd) Ohmic characteristic detection curve, and the right graph b shows the drain current-gate voltage (I) of the transistord-Vbg) The transfer characteristic curve, with a switching current ratio higher than 104, shows that the sample has good device characteristics.
The technical proposal solves the problem of beta-Ga2O3Difficult to be applied to the channel material and provides a back gate transistor with high performance.
An example of the above technical solution is given below with reference to a specific process scenario.
Based on SiO2(110-nm)/p++beta-Ga of-Si periodic pore substrate2O3And (4) preparing a nanoribbon suspended back gate transistor, wherein the hole depth is 55 nm.
The first step, substrate cleaning: with a flat growth of 110nm SiO2Heavily doped P-type Si (100) of the layer is taken as a substrate, ultrasonic cleaning is sequentially carried out for 15min by acetone, ethanol and deionized water, organic matters on the surface of the Si are removed, and finally, nitrogen is used for blow-drying.
Second step, SiO2(110-nm)/p++A method for preparing a Si periodic pore substrate, referring to the schematic process diagram of the periodic pore substrate in an embodiment of the present invention shown in fig. 7A to 7F, the method comprises the following steps:
(1) FIG. 7A shows the cleaned flat substrate SiO2(110-nm)/p++Si is fixed on a spin coater tray and a positive photoresist is spin coated. The rotating speed of the spin coater is as follows: forwarding for 500rad/min and 5 s; then, the rotor rotates at 3000rad/min for 60 s;
(2) placing the sample in the step (1) on a glue drying table for soft drying, wherein the heating temperature of the glue drying table is 100 ℃, and the glue drying time is 90 s;
(3) carrying out ultraviolet exposure on a sample by using a photoetching machine, transferring the periodic circular array micro-pattern on the mask plate onto the sample photoresist, wherein the exposure time is 18s, the circular diameter of the periodic circular array micro-pattern on the mask plate is 5 mu m, the distance between adjacent 5 multiplied by 5 circular arrays is 100 mu m, and the distance between adjacent circles in each array is 10 mu m;
(4) soaking the sample in a developing solution for developing for 45s, then immediately taking out the sample, washing the sample with deionized water, and using N2Drying; the structure shown in fig. 7B is obtained.
(5) FIG. 7C shows that metal nickel with a thickness of about 60nm is deposited on the surface of the sample with the photoetching pattern by a magnetron sputtering method, the metal nickel is used for etching a mask, the power is 75W, and the working pressure is 0.35Pa in the Ar atmosphere;
(6) FIG. 7D shows that the sample is immersed in an acetone solution, and the remaining photoresist is removed by ultrasonic cleaning using an ultrasonic cell until the pattern on the surface of the sample is completely developed;
(7) FIG. 7E shows that the sample in step (6) is subjected to Reactive Ion Etching (RIE) with etching gas SF6/O2The flow rate is 20 sccm and 30sccm respectively, the etching power is 150W, the working pressure is 3Pa, and the etching time is 60 s;
(8) FIG. 7F shows the sample immersed in the mixed solution (volume ratio HNO)3:HCl:H2O1: 1:3), ultrasonic cleaning for 15min to remove residual mask metal nickel, and obtaining the SiO2(110-nm)/p++-Si periodic pore substrate.
A third step, based on SiO2(110-nm)/p++beta-Ga of-Si periodic pore substrate2O3A preparation method of a nanoribbon suspended back gate transistor comprises the following steps:
(1) from beta-Ga using 3M tape2O3Mechanically stripping beta-Ga from single crystal block2O3The thickness of the nanobelt is 200 nm;
(2) utilizing a two-dimensional material transfer platform to transfer the beta-Ga obtained in the step (1)2O3Nanobelt transfer to SiO2(110-nm)/p++-a certain hole of the Si periodic hole substrate;
(3) and (3) fixing the sample in the step (2) on a spin coater tray, and spin-coating electron beam photoresist. The rotating speed of the spin coater is as follows: forwarding for 500rad/min and 5 s; then, the back rotation is carried out for 4000rad/min and the back rotation time is 60 s;
(4) placing the sample in the step (3) on a glue drying table for soft drying, wherein the heating temperature of the glue drying table is 170 ℃, and the glue drying time is 3min and 30 s;
(5) performing electron beam Exposure (EBL) on the sample in the step (4) to manufacture a source and drain electrode pattern;
(6) soaking the exposed sample in a developing solution for developing for 60s, and immediately taking out the sample to use N2Blow-drying, soaking the sample in isopropanol for fixing for 60s, immediately taking out the sample, and applying N2Drying;
(7) depositing Ti/Al/Ni/Au laminated metal on one surface of the sample with the photoetching pattern by using an Electron Beam Evaporation (EBE) method, wherein the laminated metal is used as an electrode of a transistor, the thickness of the laminated metal electrode is 20/100/40/80nm, and the growth temperature is 50 ℃;
(8) soaking the sample in the step (7) in an acetone solution, carrying out ultrasonic cleaning by using an ultrasonic pool to strip the residual photoresist until the surface pattern of the sample is completely appeared, then taking out the sample, washing the sample with deionized water, and using N to wash the sample2Blow-drying to obtain the SiO-based material2(110-nm)/p++beta-Ga of-Si periodic pore substrate2O3The nanoribbon suspended back gate transistor.
(9) N-performing on the sample in the step g by using a rapid thermal annealing (RTP) device2And annealing the atmosphere to realize good ohmic contact of the transistor, wherein the annealing temperature is 470 ℃ and the annealing time is 70 s.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. A back gate transistor, comprising:
the periodic hole substrate consists of a silicon substrate and a dielectric layer on the surface of the silicon substrate, and the surface of the dielectric layer is provided with a periodic hole array;
the source electrode is positioned on the periodic hole substrate;
the drain electrode is positioned on the periodic hole substrate and is separated from the source electrode on two sides of a hole;
a gate electrode which is suspended beta-Ga2O3And the nano belt is connected with the source electrode and the drain electrode.
2. The back gate transistor according to claim 1, wherein the silicon substrate is a heavily doped P-type silicon substrate, and the dielectric layer is SiO with a thickness of 110nm2A layer of material.
3. A back gate transistor according to claim 1, wherein the periodic holes in the substrate are arranged in a 5 x 5 array of holes, with a distance of 100 μm between adjacent arrays and a distance of 10 μm between adjacent holes in an array.
4. The back gate transistor according to claim 3, wherein the hole is a circular hole having a diameter of 5 μm.
5. A preparation method of a back gate transistor is characterized by comprising the following steps:
providing a substrate, wherein the substrate consists of a silicon substrate and a dielectric layer on the surface of the silicon substrate;
etching the substrate to form a periodic hole substrate with a periodic hole array;
reacting beta-Ga2O3Transferring the nanobelt to one hole of the periodic hole substrate;
etching the periodic hole substrate to form a hole in the beta-Ga2O3Photoetching patterns of source and drain electrodes on two sides of the nanobelt;
depositing a metal stack on the photolithographic pattern to form a source and a drain of a transistor;
in N2And annealing in the atmosphere.
6. The method of claim 5, wherein the periodic array of holes has a hole diameter of 5 μm and a depth that can be modulated by varying the reactive ion etching time; the distance between adjacent 5 x 5 circular arrays was 100 μm, and the pitch of adjacent circles in each array was 10 μm.
7. The method of claim 5, wherein the β -Ga is2O3Nanobelt from beta-Ga using 3M adhesive tape2O3Mechanically peeling the monocrystalline block; the beta-Ga2O3The effective carrier concentration of the single crystal bulk is 1017-1019cm-3。
8. The method of claim 6, wherein the source and drain electrodes are formed by depositing a metal stack by electron beam evaporation, the metal stack comprising a metal Ti layer, a metal Al layer, a metal Ni layer, and a metal Au layer in that order, and having a thickness of 20nm, 100nm, 40nm, and 80nm in that order, and a forming temperature of 50 ℃.
9. The method of claim 5, wherein the annealing process uses a rapid thermal annealing apparatus at N2Annealing in the atmosphere to realize good ohmic contact of the transistor, wherein the annealing temperature is 470 ℃ and the annealing time is 70 s.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011606191.8A CN112701156A (en) | 2020-12-28 | 2020-12-28 | Back gate transistor and preparation method thereof |
| PCT/CN2020/141975 WO2022141353A1 (en) | 2020-12-28 | 2020-12-31 | Back-gate transistor and preparation method therefor |
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| CN202011606191.8A CN112701156A (en) | 2020-12-28 | 2020-12-28 | Back gate transistor and preparation method thereof |
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Citations (5)
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| CN103943511A (en) * | 2014-04-18 | 2014-07-23 | 江苏大学 | Low-power-consumption thin back gate graphene field effect transistor manufacturing method |
| US20160056304A1 (en) * | 2013-04-12 | 2016-02-25 | The Regents Of The University Of California | Nanowire nanoelectromechanical field-effect transistors |
| CN110663117A (en) * | 2017-05-25 | 2020-01-07 | 华为技术有限公司 | Graphene field effect transistor and preparation method thereof |
| CN111524998A (en) * | 2020-05-07 | 2020-08-11 | 西安电子科技大学 | Solar light blind area Schottky back grid metal oxide semiconductor field effect photoelectric transistor |
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| CN106898644B (en) * | 2017-01-23 | 2019-07-30 | 西安电子科技大学 | High-breakdown-voltage field effect transistor and preparation method thereof |
| TWI712171B (en) * | 2017-06-07 | 2020-12-01 | 聯華電子股份有限公司 | Semiconductor device |
| CN108470675B (en) * | 2018-02-28 | 2021-09-28 | 唐为华 | Si-based gallium oxide thin film back grid solar blind ultraviolet transistor and preparation method thereof |
| CN111435682A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Multi-channel gate-all-around transistor |
| CN112133755A (en) * | 2020-10-07 | 2020-12-25 | 西安电子科技大学 | Preparation method of high-performance gallium oxide field effect transistor of insulating substrate |
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| KR20130078310A (en) * | 2011-12-30 | 2013-07-10 | 그래핀스퀘어 주식회사 | Radio frequancy device using suspended graphene |
| US20160056304A1 (en) * | 2013-04-12 | 2016-02-25 | The Regents Of The University Of California | Nanowire nanoelectromechanical field-effect transistors |
| CN103943511A (en) * | 2014-04-18 | 2014-07-23 | 江苏大学 | Low-power-consumption thin back gate graphene field effect transistor manufacturing method |
| CN110663117A (en) * | 2017-05-25 | 2020-01-07 | 华为技术有限公司 | Graphene field effect transistor and preparation method thereof |
| CN111524998A (en) * | 2020-05-07 | 2020-08-11 | 西安电子科技大学 | Solar light blind area Schottky back grid metal oxide semiconductor field effect photoelectric transistor |
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