CN116344617A - Gallium oxide laminated full-surrounding grid field effect transistor and preparation method thereof - Google Patents
Gallium oxide laminated full-surrounding grid field effect transistor and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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Abstract
The invention discloses a gallium oxide laminated full-surrounding gate field effect transistor and a preparation method thereof, belonging to the field of semiconductor devices; the transistor mainly solves the problems of weak gate control capability, low switch conduction ratio and large threshold swing existing in the conventional gallium oxide MOS device. The gallium oxide semiconductor comprises an insulating substrate, a gallium oxide channel layer, a two-dimensional material dielectric layer surrounding the gallium oxide channel, a grid, an insulating layer and a stacked structure repeated above. The grid electrode surrounding the surrounding channel is realized in a mode of stripping a film, so that the problem of difficult realization of the GAA structure process is solved; the four-sided contact of the gate gives the device good channel control capability. The invention improves the on-off ratio of the device and can be used for manufacturing gallium oxide MOSFET devices with high on-off characteristics.
Description
Technical Field
The invention belongs to the field of semiconductor devices, and particularly relates to a gallium oxide laminated full-surrounding gate field effect transistor and a preparation method thereof.
Background
Gallium oxide is an emerging semiconductor material with an ultra wide band gap of 4.5eV-4.9eV and thus achieves a high critical breakdown field strength of about 8 MV/cm. At the same time, the gallium oxide crystal has five crystal forms of alpha, beta, gamma, delta and epsilon, wherein beta-phase Ga 2 O 3 Is widely studied and applied due to its chemical stability and direct band gap characteristics. Gallium oxide devices are considered to be a material with great development prospect in terms of power devices in consideration of the ultra-wide forbidden bandwidth, the critical breakdown field strength of 8MV/cm and the Barbary gamma figure of merit which is more than twenty times that of the traditional silicon materials.
Although gallium oxide materials have very high theoretical material properties and relatively low manufacturing costs, they are not currently in widespread use in practical applications. Worldwide, factors that hinder the large-scale use of gallium oxide include p-typeDoping is difficult to achieve, and the self-heating effect and heat dissipation of the device with low thermal conductivity of the gallium oxide material are problems; in addition, in the device implementation in engineering, the fabrication of the enhanced device faces great difficulties. Depletion of gallium oxide channels is practically difficult to achieve, and most of the existing enhancement modes rely on etched recessed gates to fabricate devices. However, such implementation methods often have problems that the manufacturing process is very complex and difficult, and even after the completion, damage to the device is obvious, such as unclear boundary, increased defect density, uncontrollable leakage channel and the like; at the same time, the grid electrode is sinking to a certain extent to improve the grid electrode to Ga 2 O 3 Channel control capability; the weak gate control capability also causes corresponding problems of reduced frequency response, high subthreshold swing and the like of the switch.
In such a background, a Gate-all-around (GAA) device is a new structural device that extends the existing semiconductor technology route, and the whole channel outline of GAA is completely wrapped by the Gate, and compared with the conventional three-terminal-surrounding channel, the four-side control of the fully-surrounding structure means better Gate control capability. GAA devices have many advantages, and the superior performance in electrostatic performance is called "final device", but there are difficulties in that the process is difficult to implement, the manufacturing process is complicated, and the like.
Disclosure of Invention
Aiming at the problems of weak grid control capability, difficult realization of enhancement type devices and difficult realization of device technology of gallium oxide devices, the invention provides a gallium oxide laminated full-surrounding grid field effect tube which is built by stripping two-dimensional materials and stripping gallium oxide nano film stacks so as to reduce device damage and improve device performance.
In order to achieve the aim, the gallium oxide laminated full-surrounding gate field effect transistor comprises an insulating substrate (1), a source electrode (9) and a drain electrode (10) which are arranged on the insulating substrate (1), and a laminated full-surrounding gate structure which is arranged between the source electrode (9) and the drain electrode (10);
the laminated full-surrounding grid structure comprisesBack gate (2), first beta-Ga 2 O 3 A channel layer (4) surrounding the first beta-Ga 2 O 3 A first dielectric layer (3), a first top gate (5), a second beta-Ga of the channel layer (4) 2 O 3 A channel layer (7) surrounding the second beta-Ga 2 O 3 A second dielectric layer (6) of the channel layer (7), a second top gate (8); the back grid (2) is arranged at the bottom of the laminated full-surrounding grid structure and connected with the edge of the first top grid (5) to surround the first dielectric layer (3); the second top grid (8) is arranged at the top of the laminated full-surrounding grid structure, and is connected with the edge of the first top grid (5) to surround the second dielectric layer (6);
the back grid (2), the first top grid (5) and the second top grid (8) are made of two-dimensional materials; the channel material is Ga 2 O 3 Nanoplatelets or nanowires.
Further, the first beta-Ga 2 O 3 Channel layer (4) and said second beta-Ga 2 O 3 beta-Ga of channel layer (7) 2 O 3 Crystalline material having a doping concentration of 1X 10 16 ～2×10 18 cm -3 The thickness is 100 nm-200 nm.
Furthermore, the back grid (2), the first top grid (5) and the second top grid (8) are all made of peeled graphene, and the thickness is 5-20nm.
Further, the insulating substrate (1) is diamond, siO 2 /p + Si, sapphire or Fe doped Ga 2 O 3 One of an insulating or semi-insulating substrate.
In order to achieve the above object, the present invention further provides a method for preparing a gallium oxide full-surrounding gate stack field effect transistor, which specifically includes the following steps:
step s1: beta-Ga 2 O 3 And (3) preparing a film. For a doping concentration of 1X 10 16 ～2×10 18 cm -3 The crystal orientation is
beta-Ga of (C) 2 O 3 A substrate material, the crystal orientation of which is found (100), is arranged on a Nittro blue adhesive tapeRepeatedly tearing to obtain beta-Ga 2 O 3 Film, transfer Ga on blue tape through PDMS glue 2 O 3 Selecting a film material with proper thickness under an optical microscope during transferring;
step s2: and (5) pretreatment of the substrate material. Selecting a target substrate, treating the surface of the target substrate for 15min, 15min and 5min respectively by using acetone, isopropanol and deionized water, and drying by using nitrogen to obtain a substrate material with a clean surface;
step s3: preparing the h-BN two-dimensional material. The h-BN crystal is selected and placed on a blue adhesive tape, the crystal material is repeatedly torn to obtain the h-BN two-dimensional material, the h-BN two-dimensional material is transferred to PDMS adhesive, and the h-BN two-dimensional material with the thickness of 15-60nm is selected and marked by utilizing an optical microscope and an atomic force microscope;
step s4: and preparing a transfer die for transferring the graphene. Using a mechanical solid transparent peel with a thickness of about 2 μm, the adhesive side by the Pritt tape was applied towards the glass plate; spin-coating a 1 μm methacrylate copolymer dissolved in a methyl isobutyl ketone solution (MIBK solvent), and then baking the transfer film at 120 ℃ for 10min to remove the MIBK solvent from the copolymer;
step s5: and preparing and transferring the graphene nano film to a transfer mold. Stripping a certain number of graphene nano films from the highly-oriented pyrolytic graphite crystal by using a mechanical stripping method, and then depositing the graphene nano films on the methacrylate copolymer layer prepared in the previous step;
step s6: and transferring the graphene to a target substrate by using the methacrylate copolymer transfer film. Placing a substrate sample on a support, setting the ambient temperature to 75-100 ℃, then aligning the copolymer with the graphene nanofilm to the substrate surface, lowering a mask on the polymer side onto a heated substrate, contacting the polymer with the substrate surface and melting and adhering to the substrate.
Step s7: the copolymer adhering to the substrate is removed. After the transfer step is completed, using an acetone solution to soak for 30min to remove the methacrylate polymer, and then using isopropanol to wash to obtain a large-area transferred graphene nano film serving as a bottom gate of the GAA device;
step s8: transferring the h-BN two-dimensional material. The prepared h-BN two-dimensional material is transferred to a substrate sheet with a graphene nano film by a dry method by using a transfer platform;
step s9: and manufacturing a gallium oxide channel layer. beta-Ga to be prepared by using transfer platform 2 O 3 Selecting proper size under an optical microscope by using PDMS glue, transferring to a substrate and stacking the substrate above the h-BN two-dimensional material;
step s10: and transferring the gate dielectric and the graphene gate to the upper part of the channel layer. Confirming an h-BN two-dimensional material with the thickness of 20nm, enabling the h-BN to be in contact with a target substrate after aligning the position of the mark, standing for 5min, and depositing an h-BN gate medium above the channel layer; then, adhering the transfer film to the substrate close to the sample under the condition that the set temperature is set at 80 ℃ by using a methacrylate polymer transfer die with a graphene nano film with the thickness of 20nm mechanically stripped; after cooling, respectively soaking and flushing the mixture by using acetone and isopropanol to remove the methacrylate polymer, thus completing the manufacture of a layer of full-surrounding gate structure;
step s11: transferring the h-BN two-dimensional material onto the top gate. Selecting a 50nm h-BN two-dimensional material, and transferring the h-BN two-dimensional material to the position above a full-surrounding structure of a bottom gate-gate medium-channel-medium-top gate first layer of the device by using a transfer platform;
step s12: and manufacturing a second laminated full-surrounding grid. Repeating the steps (9) - (10), and building a layer of the same repeated stacking structure on the basis of the full-surrounding gate device of the single-layer gallium oxide channel;
step s13: the metal electrode is transferred and annealed to form an ohmic contact. Transfer evaporated Au/Ti 20:80nm metal electrode, then 480 ℃ for 60min, N 2 And (5) performing atmosphere annealing to form good ohmic contact and finish device manufacturing.
Further, the step s1: beta-Ga 2 O 3 In the preparation of the film, beta-Ga 2 O 3 The crystal has n-type doping concentration of 1×10 16 ～2×10 18 cm -3 The thickness is 100 nm-200 nm.
Further, the step s13: in the process of transferring source and drain metal electrodes and annealing to form ohmic contact, the metal electrode manufacturing method adopts a method of transferring by using a transfer tape after vapor plating, or a laminated device is built after electrodes are manufactured on a substrate material in a photoetching mode.
Further, the step s6: the graphene nano film is transferred into a target substrate, the transfer mode is realized by a transfer mode formed by a methacrylate copolymer, an adhesive tape and mechanically transparent glass, and the graphene nano film and the transfer mode are attached to the target substrate together and then dissolved to wash out the copolymer to obtain the graphene nano film with high integrity.
The invention has the following beneficial effects:
1. the gallium oxide laminated full-surrounding grid field effect transistor combines two-dimensional material nano layers on the basis of the existing back grid field effect transistor to form a nano laminated full-surrounding grid device in a stacking way, so that the control capability of a grid electrode on a channel is effectively enhanced, the current conduction ratio of the device is increased, and the electrostatic characteristic of the device is optimized; the control of the four-sided channel optimizes the switching characteristics of the device and reduces the subthreshold swing.
2. According to the preparation method of the gallium oxide full-surrounding gate field effect transistor, a mechanical stripping method is used for preparing the gallium oxide channel layer and the two-dimensional material nano layer, and compared with the conventional technical scheme of multiple selective etching and epitaxial growth, the preparation method is simple and convenient to operate, low in cost, high in crystal lattice integrity of the wafer surface and high in film quality; the prepared film can be used for selecting film materials with proper thickness from prepared samples to manufacture devices, and meanwhile, the operation of transferring the film materials onto a substrate is simple and easy to realize.
3. Compared with the traditional metal gate electrode, the graphene electrode adopted by the preparation method of the gallium oxide full-surrounding gate field effect transistor has the advantages that the graphene electrode can be combined with other two-dimensional materials serving as gate dielectrics and nano gallium oxide channels to form and wrap the channels; meanwhile, graphene has the unique advantages of excellent conductivity and adjustable energy band, and forms a potential barrier with a contact material to control channel carriers.
4. The preparation method adopted by the invention can finish the process on any substrate, and can finish the device preparation on the diamond substrate aiming at the problems of low gallium oxide heat conductivity, difficult heat dissipation and the like.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a gallium oxide stack fully-surrounding gate field effect transistor structure;
FIG. 2 is a cross-sectional view of a gallium oxide stack fully surrounding a channel of a gate field effect transistor;
wherein 1, an insulating substrate, 2, a back gate, 3, a first dielectric layer, 4, a first beta-Ga 2 O 3 Channel layer 5, first top gate 6, second dielectric layer 7, second beta-Ga 2 O 3 Channel layer 8, second top gate 9, source electrode 10, drain electrode.
Detailed Description
The technical solutions of the present invention will be clearly and completely described in connection with the embodiments, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.
The experimental methods described in the following examples are all conventional methods unless otherwise specified; the reagents and materials, unless otherwise specified, are commercially available.
The full surrounding gate gallium oxide stack field effect transistor and the manufacturing process of the invention are described in further detail below with reference to the accompanying drawings.
Referring to fig. 1 and 2, the structure of the gallium oxide laminated full-surrounding gate field effect transistor of the present inventionThe full-surrounding gate structure comprises an insulating substrate, a source electrode, a drain electrode, a source electrode 9 and a drain electrode 10 which are arranged on the insulating substrate 1, and a laminated full-surrounding gate structure which is arranged between the source electrode 9 and the drain electrode 10; the laminated full-surrounding gate structure comprises a back gate 2, a first beta-Ga 2 O 3 A channel layer 4 surrounding the first beta-Ga 2 O 3 First dielectric layer 3, first top gate 5, second beta-Ga of channel layer 4 2 O 3 A channel layer 7 surrounding the second beta-Ga 2 O 3 A second dielectric layer 6, a second top gate 8 of the channel layer 7; the back gate 2 is arranged at the bottom of the laminated full-surrounding gate structure, and is connected with the edge of the first top gate 5 to surround the first dielectric layer 3; the second top gate 8 is arranged on the top of the laminated full-surrounding gate structure and connected with the edge of the first top gate 5 to surround the second dielectric layer 6; beta-Ga used 2 O 3 Crystalline material having a doping concentration of 1X 10 16 ～2×10 18 cm -3 The thickness is 100 nm-200 nm; the insulating substrate 1 is diamond or SiO 2 /p + Si, sapphire or Fe doped Ga 2 O 3 One of the following; the gate dielectric is positioned between the gallium oxide channel and the gate, and in order to realize high dielectric property and meet the conditions that the device process can be realized, a stripped hexagonal boron nitride material is adopted; the grids in the full-surrounding structure are made of graphene materials, are manufactured by a stripping method, have the thickness of 5-20nm, and are completely wrapped around two layers of channel layers, so that the grid voltage is sensitive to the switching regulation and control of the channels, and has good electrostatic characteristics and lower subthreshold swing in a subthreshold region when the grid is turned off, and the switching on ratio of the device is improved.
Example 1
The preparation method of the gallium oxide laminated full-surrounding gate field effect transistor adopting the transfer metal electrode comprises the following steps:
step 1: beta-Ga 2 O 3 Preparation of films
The doping concentration is selected to be 1.8X10 17 cm -3 A kind of electronic device
Crystal orientation n-type beta-Ga 2 O 3 Single crystal substrate, then sequentially in acetone solution, anhydrousUltrasonic cleaning is carried out on ethanol and deionized water for 5min, and then nitrogen is used for blow-drying. Finding out (100) crystal orientation with weaker gallium oxide single crystal bonding, and cleaving the cleaned beta-Ga along the (100) direction by using tweezers or a blade 2 O 3 Single crystal, obtaining micron-sized beta-Ga 2 O 3 A film. Micron-sized beta-Ga to be prepared 2 O 3 The film is adhered on the adhesive tape and contains micron-sized beta-Ga 2 O 3 The adhesive tape of the film is folded and adhered for many times, after two layers of adhesive tapes are attached, a single-sided extrusion material can remove bubbles, and the beta-Ga 2O3 film with the thickness of nano scale is obtained through many times of mechanical stripping and is adhered on the transfer adhesive tape for standby.
Step 2: cleaning SiO 2 /p + Si insulating substrate sheet
Selecting SiO 2 /p + Si insulating substrate sheet, wherein SiO 2 The thickness of the layer is 270nm, the layer is soaked in acetone solution for 8 hours, and then is respectively washed for 5 minutes by using the isopropyl alcohol and the deionized water in sequence to remove organic pollutants, and then is dried by using nitrogen to obtain the target substrate with good interface.
Step 3: stripping the dielectric layer of the h-BN two-dimensional material
And (3) repeatedly tearing the crystal material by selecting the h-BN crystal on the blue adhesive tape to obtain the h-BN nano-scale film, then cutting out small transparent PDMS (polydimethylsiloxane) adhesive, adhering the h-BN two-dimensional material from the blue adhesive tape, placing the h-BN two-dimensional material under an electron microscope to find out the nano-scale film, determining the position of the rear mark, and selecting the film with the thickness of 20nm by using an atomic force microscope AFM.
Step 4: preparation graphene transfer mould
Using a mechanical solid transparent glass with a thickness of 2 μm, the adhesive side of the Pritt tape was laminated towards the glass plate; then, a 1 μm methacrylate copolymer dissolved in a methyl isobutyl ketone solution (MIBK solvent) was spin-coated, and then the transfer film was baked at 120℃for 10 minutes to remove the MIBK solvent from the copolymer. A glass-methacrylate copolymer transfer mold was obtained.
Step 5: stripping and transferring graphene nanomembranes to a transfer die
And repeatedly tearing the highly oriented pyrolytic graphene by using a blue tape by using a mechanical stripping method to obtain the nanoscale graphene film layer. And after transferring to PDMS glue, selecting a graphene layer with the thickness of about 5nm by using an optical microscope and an atomic force microscope, and depositing the peeled graphene film on a methacrylate copolymer transfer die so as to facilitate subsequent transfer.
Step 6: transferring graphene films to target substrates using methacrylate copolymers
The substrate sample containing h-BN was placed on a stand, the ambient temperature was set at 75-100 ℃, then the copolymer with graphene flakes was aligned to the substrate surface, the mask on the polymer side was lowered onto the heated substrate, and the polymer was brought into contact with the substrate surface and melt adhered to the substrate. And obtaining the substrate-bottom gate-copolymer structure with the graphene bottom gate.
Step 7: removal of methacrylate attached to a substrate
And soaking the substrate-bottom gate-copolymer structure in an acetone solution for 30min, removing the methacrylate polymer, and then flushing with isopropanol to obtain a large-area transferred graphene nano sheet serving as a bottom gate of the GAA device.
Step 8: transferring h-BN dielectric layer
And (3) confirming that the thickness of the layer of the h-BN two-dimensional material stripped in the step (5) is 20nm by an atomic force microscope before transferring by using a transfer adhesive tape, opening an air pump, adsorbing a slide glass and a clean glass sheet, putting the material into a transfer platform downwards, enabling the h-BN to be in contact with a target substrate by slowly adjusting a knob after the target substrate is aligned to the position of a mark, waiting for 5min, separating the slide glass from the target substrate by slowly adjusting the knob, and ensuring good adhesion between the h-BN and a graphene grid under the full action of Van der Waals force, thus obtaining the bottom grid structure of the transistor.
Step 9: transfer beta-Ga 2O3 film
Transferring beta-Ga 2O3 film on blue adhesive tape with PDMS adhesive, adhering the material with thickness of 100nm and thickness uniformity to the area of deposited back grid and grid medium over insulating substrate with cantilever Liang Huanman, applying 1200g/cm2 pressure to the adhesive tape, holding for 40s, and stripping off the adhesive tape to obtain nanometer filmβ-Ga 2 O 3 And transferring the film to the substrate and the h-BN medium to obtain a layer of full-surrounding gate channel.
Step 10: transferring gate dielectric and graphene gate over channel layer
Through the same technological method in the step 8, confirming that the thickness of the h-BN nano layer is 20nm through an atomic force microscope, slowly adjusting a knob after aligning the position of the mark to enable the h-BN to be in contact with a target substrate, waiting for 5min, slowly adjusting the knob to separate a slide glass from the target substrate, and depositing an h-BN grid medium above a channel layer; then covering the gallium oxide channel and the upper part of the gate dielectric by using a methacrylate polymer with a graphene material with a thickness of 20nm by mechanical stripping, keeping the graphene on the polymer to cover part of the gate dielectric and to be in contact with the bottom gate in a certain area, and then approaching the transfer film to the sample under the condition that the temperature of the substrate is set at 80 ℃ so that the copolymer is adhered to the substrate; and (3) cooling, and respectively soaking and washing with acetone and isopropanol to remove the methacrylate polymer, thereby completing the manufacture of a layer of full-surrounding gate structure.
Step 11: transferring the h-BN gate dielectric onto the top gate
Firstly, an atomic force microscope is used for observing h-BN film materials on a transfer adhesive to find h-BN two-dimensional materials which are enough to cover a graphene grid and have the thickness of about 50nm, then a transfer platform is used for aligning a device manufacturing area, a mechanical cantilever is slowly lowered to be attached to the surface, pressure is applied to transfer h-BN to the upper part of a first layer full-surrounding structure of a bottom grid-grid medium-channel-medium-top grid of the device, and a medium layer for isolating an upper layer channel and a lower layer channel is obtained.
Step 12: manufacturing a second laminated full-surrounding grid
Repeating the steps 9-10, and building a layer of the same repeated stacking structure on the basis of the GAA device with the single-layer gallium oxide channel. With beta-Ga by means of a transfer platform 2 O 3 The PDMS of the film layer is slowly attached to the area where the back gate and the gate dielectric are deposited above the insulating substrate, pressure is applied to the adhesive tape part, and the adhesive tape is peeled off after the adhesive tape stays for 40 seconds; then the h-BN which is determined to be 20nm thick by an atomic force microscope is aligned and then passes through a transfer platform to be connected with a gallium oxide channelThe layers 2 are contacted, and after waiting for 5min, the slide glass and the adhesive tape are slowly separated to obtain a gate medium covered on the channel; covering a methacrylate polymer with a mechanical stripping graphene material above the gallium oxide channel and the gate dielectric, and setting the substrate temperature to 80 ℃ to enable the transfer film to be close to the sample so that the copolymer is adhered to the substrate; and cooling, and respectively soaking and washing with acetone and isopropanol to remove the methacrylate polymer, so as to obtain a second-layer gallium oxide full-surrounding structure.
Step 13: transferring metal electrodes and forming ohmic contacts
The Ti/Au metal electrode which is transferred and evaporated through the transfer platform is respectively transferred to the substrate material, the gallium oxide channel, and the top gate and the back gate are contacted by the interconnected graphene material. Placing the device with electrode manufacture into an annealing instrument, setting annealing temperature to 480 ℃ and adding N 2 And annealing for 60min in the atmosphere to enable the metal electrode and the material to form good ohmic contact, so that the device manufacturing is completed.
Example two
The preparation method of the gallium oxide laminated full-surrounding gate field effect transistor adopting the photoetching technology to manufacture the metal electrode comprises the following steps:
step 1: beta-Ga 2 O 3 Preparation of films
The doping concentration is selected to be 1.8X10 17 cm -3 
Crystal orientation n-type beta-Ga 2 O 3 And (3) ultrasonically cleaning the monocrystalline substrate in acetone solution, absolute ethyl alcohol and deionized water for 5min, and drying by nitrogen. Finding out (100) crystal orientation with weaker beta-Ga 2O3 monocrystal bonding, and cleaving cleaned beta-Ga along (100) direction by using tweezers or blades 2 O 3 Single crystal, obtaining micron-sized beta-Ga 2 O 3 A film. Micron-sized beta-Ga to be prepared 2 O 3 The film is adhered on the adhesive tape and contains micron-sized beta-Ga 2 O 3 The adhesive tape of the film is folded and adhered for a plurality of times, and after the two layers of adhesive tapes are attached, the material can be extruded unilaterally to remove bubbles and pass through a plurality of layers of adhesive tapesAnd (5) secondary mechanical stripping to obtain the beta-Ga 2O3 film with the thickness of nano scale, and adhering the film onto a transfer adhesive tape for standby.
Step 2: cleaning SiO 2 /p + Si insulating substrate sheet
Selecting SiO 2 /p + The thickness of the SiO2 layer is 270nm, the Si insulating substrate slice is soaked in acetone solution for 8 hours, and then is respectively washed for 5 minutes by using the isopropyl alcohol and the deionized water in sequence to remove organic pollutants, and then is dried by using nitrogen to obtain the target substrate with good interface.
Step 3: manufacturing substrate cross mark array by photoetching technology
Uniformly coating photoresist on the cleaned substrate by using a photoresist homogenizer, and then placing the substrate on a heating table to perform pre-baking at 100 ℃ for 90 seconds; and (5) putting the substrate with the bubbles eliminated after the pre-baking into a photoetching machine for exposure, and adjusting the photoetching machine to be in a Hard contact mode for exposure for 1.2s. The substrate was then developed with a developer for 40 seconds. The use of NMD-3 developer requires attention that the device is not capable of emitting yellow light.
Step 4: metal electrode vapor deposition
Placing the developed substrate into an e-beam for evaporation, wherein a Ti/Au electrode with the evaporation metal of 10/80nm is used as a source electrode and a drain electrode of the device; and then the device is put into acetone solution for metal stripping, and ultrasound is carried out in an ultrasonic machine in the stripping process to rapidly finish the stripping. Multiple source-drain metal electrode sets with different pitches, including 20 μm, 30 μm, 40 μm and 50 μm, are manufactured on the same piece of substrate material at one time so as to conveniently select proper pitches according to the size of the stripping material.
Step 5: stripping the dielectric layer of the h-BN two-dimensional material
And (3) repeatedly tearing the crystal material by selecting an h-BN crystal on a blue adhesive tape to obtain an h-BN two-dimensional material, then cutting out small transparent PDMS (polydimethylsiloxane) adhesive, adhering an h-BN film from the blue adhesive tape, placing the h-BN film under an electron microscope to find out a nano-scale film, determining the position of the h-BN after marking, and selecting the film with the thickness of 20nm by using an atomic force microscope AFM.
Step 6: preparation graphene transfer mould
Using a mechanical solid transparent glass with a thickness of 2 μm, the adhesive side of the Pritt tape was laminated towards the glass plate; the methacrylate copolymer was then spin-coated 1 μm in a methyl isobutyl ketone solution (MIBK solvent), and the transfer film was then baked at 120℃for 10min to remove the MIBK solvent from the copolymer. A glass-methacrylate copolymer transfer mold was obtained.
Step 7: stripping and transferring graphene film to transfer mold
And repeatedly tearing the highly oriented pyrolytic graphene by using a blue tape by using a mechanical stripping method to obtain the nanoscale graphene film layer. And transferring to PDMS glue, selecting a graphene layer with the thickness of about 5nm by using an optical microscope and an atomic force microscope, and depositing the peeled graphene film on a methacrylate copolymer transfer mold.
Step 8: transferring graphene films to target substrates using methacrylate copolymers
Placing a substrate sample containing boron nitride on a bracket, setting the ambient temperature to 75-100 ℃, and selecting the step 4: the metal electrode evaporation is carried out to manufacture a source-drain metal electrode group with the interval of 40 mu m, then a copolymer with graphene sheets is aligned to the selected metal electrode group, and a mask on the polymer side is lowered onto a heating substrate, so that the polymer contacts the surface of the substrate to contact and melt and adhere to the substrate. And obtaining the substrate-bottom gate-copolymer structure with the graphene bottom gate.
Step 9: removal of methacrylate attached to a substrate
And soaking the substrate-bottom gate-copolymer structure in an acetone solution for 30min, removing the methacrylate polymer, and then flushing with isopropanol to obtain a large-area transferred graphene sheet serving as a bottom gate of the GAA device.
Step 10: transferring h-BN dielectric layer
And (3) confirming that the thickness of the layer of the h-BN two-dimensional material stripped in the step (5) is 20nm by an atomic force microscope before transferring by using a transfer adhesive tape, opening an air pump, adsorbing a slide glass and a clean glass sheet, putting the material into a transfer platform downwards, enabling the h-BN to be in contact with a target substrate by slowly adjusting a knob after the target substrate is aligned to the position of a mark, waiting for 5min, separating the slide glass from the target substrate by slowly adjusting the knob, and ensuring good adhesion between the h-BN and a graphene grid under the full action of Van der Waals force, thus obtaining the bottom grid structure of the transistor.
Step 11: transfer beta-Ga 2O3 film
Transferring beta-Ga 2O3 film on blue adhesive tape with PDMS adhesive, adhering the film to the back grid and grid medium deposited area over the insulating substrate with cantilever Liang Huanman, applying 1200g/cm2 pressure to the adhesive tape, holding for 40s, stripping the adhesive tape to obtain nanometer beta-Ga film 2 O 3 The film is transferred to the substrate and the boron nitride medium.
Step 12: transferring gate dielectric and graphene gate over channel layer
Through the same technological method in the step 8, confirming that the thickness of the h-BN two-dimensional material is 20nm through an atomic force microscope, slowly adjusting a knob after aligning the position of the mark to enable the h-BN to be in contact with a target substrate, waiting for 5min, slowly adjusting the knob to separate a slide glass from the target substrate, and depositing a hexagonal boron nitride grid medium above a channel layer; then covering the gallium oxide channel and the upper part of the gate dielectric by using a methacrylate polymer with a graphene material with a thickness of 20nm by mechanical stripping, keeping the graphene on the polymer to cover part of the gate dielectric and to be in contact with the bottom gate in a certain area, and then approaching the transfer film to the sample under the condition that the temperature of the substrate is set at 80 ℃ so that the copolymer is adhered to the substrate; and cooling, and respectively soaking and washing with acetone and isopropanol to remove the methacrylate polymer, thereby completing the preparation of a layer of GAA structure.
Step 13: transferring the h-BN gate dielectric onto the top gate
Firstly, an atomic force microscope is used for observing h-BN film materials on a transfer adhesive, h-BN two-dimensional materials which are enough to cover a graphene grid and have the thickness of about 50nm are found, then a transfer platform is used for aligning with a device manufacturing area, a mechanical cantilever is slowly lowered to be attached to the surface, and pressure is applied to transfer boron nitride to the upper part of a first layer full-surrounding structure of a bottom grid-grid medium-channel-medium-top grid of the device.
Step 14: manufacturing a second laminated full-surrounding grid
Repeating the steps 9-10, and building a layer of the same repeated stacking structure on the basis of the GAA device with the single-layer gallium oxide channel. With beta-Ga by means of a transfer platform 2 O 3 The PDMS of the film layer is slowly attached to the area where the back gate and the gate dielectric are deposited above the insulating substrate, pressure is applied to the adhesive tape part, and the adhesive tape is peeled off after the adhesive tape stays for 40 seconds; then h-BN which is determined to be 20nm thick by an atomic force microscope is aligned and then is contacted with the gallium oxide channel layer 2 through a transfer platform, and after waiting for 5min, a slide glass and an adhesive tape are slowly separated, so that a gate medium covered on a channel is obtained; covering a methacrylate polymer with a mechanical stripping graphene material above the gallium oxide channel and the gate dielectric, and setting the substrate temperature to 80 ℃ to enable the transfer film to be close to the sample so that the copolymer is adhered to the substrate; and cooling, and respectively soaking and washing with acetone and isopropanol to remove the methacrylate polymer, so as to obtain a second-layer gallium oxide full-surrounding structure.
Step 15: annealing to form ohmic contacts
The manufactured gallium oxide laminated layer fully surrounding grid field effect tube is put into an annealing instrument, the annealing temperature is set at 480 ℃, and the annealing temperature is set at N 2 And annealing for 60min in the atmosphere to enable the metal electrode and the material to form good ohmic contact, so that the device manufacturing is completed.
The foregoing is merely illustrative and explanatory of the invention, as it is well within the scope of the invention as claimed, as it relates to various modifications, additions and substitutions for those skilled in the art, without departing from the inventive concept and without departing from the scope of the invention as defined in the accompanying claims.
Claims (8)
1. A gallium oxide stack fully-surrounding gate field effect transistor, characterized by: the structure comprises an insulating substrate (1), a source electrode (9) and a drain electrode (10) which are arranged on the insulating substrate (1), and a laminated full-surrounding gate structure which is arranged between the source electrode (9) and the drain electrode (10);
the laminated full-surrounding gate structure comprises a back gate (2), a first beta-Ga 2 O 3 A channel layer (4) surrounding the first beta-Ga 2 O 3 A first dielectric layer (3), a first top gate (5), a second beta-Ga of the channel layer (4) 2 O 3 A channel layer (7) surrounding the second beta-Ga 2 O 3 A second dielectric layer (6) of the channel layer (7), a second top gate (8); the back grid (2) is arranged at the bottom of the laminated full-surrounding grid structure and connected with the edge of the first top grid (5) to surround the first dielectric layer (3); the second top grid (8) is arranged at the top of the laminated full-surrounding grid structure, and is connected with the edge of the first top grid (5) to surround the second dielectric layer (6);
the back grid (2), the first top grid (5) and the second top grid (8) are made of two-dimensional materials; the first beta-Ga 2 O 3 Channel layer (4) and second beta-Ga 2 O 3 The material of the channel layer (7) is Ga 2 O 3 Nanoplatelets or nanowires.
2. A transistor according to claim 1, characterized in that: the first beta-Ga 2 O 3 Channel layer (4) and said second beta-Ga 2 O 3 The channel layer (7) is beta-Ga 2 O 3 Crystalline material having a doping concentration of 1X 10 16 ～2×10 18 cm -3 The thickness is 100 nm-200 nm.
3. A transistor according to claim 1, characterized in that: the back grid (2), the first top grid (5) and the second top grid (8) are all made of peeled graphene, and the thickness of the peeled graphene is 5-20nm.
4. A transistor according to claim 1, characterized in that: the insulating substrate (1) is diamond or SiO 2 /p + Si, sapphire or Fe doped Ga 2 O 3 One of an insulating or semi-insulating substrate.
5. A preparation method of a gallium oxide laminated full-surrounding gate field effect transistor is characterized by comprising the following steps: the method specifically comprises the following steps:
step s1: beta-Ga 2 O 3 Preparing a film; beta-Ga 2 O 3 The substrate material is repeatedly torn to obtain beta-Ga 2 O 3 Transferring beta-Ga through PDMS glue 2 O 3 A film;
step s2: pretreating a substrate material; processing the surface of the target substrate to obtain a substrate material with clean surface;
step s3: preparing an h-BN two-dimensional material; selecting an h-BN crystal, repeatedly tearing the h-BN crystal, transferring the obtained nanoscale h-BN two-dimensional material to PDMS adhesive, and selecting and marking the h-BN two-dimensional material with the thickness of 15-60 nm;
step s4: preparing a transfer die for transferring graphene; using mechanically solid transparent glass, bonding with the adhesive side of the Pritt tape toward the glass; spin-coating a methacrylate copolymer dissolved in a methyl isobutyl ketone solution, wherein the solvent of the methyl isobutyl ketone solution is MIBK solvent; baking the transfer film to remove MIBK solvent from the copolymer;
step s5: preparing and transferring the graphene nano film to a transfer mold; stripping a certain number of graphene thin layers by using a mechanical stripping method, and depositing the graphene thin layers on the methacrylate copolymer layer;
step s6: transferring the graphene nano film to a target substrate; placing a substrate sample on a support, aligning a copolymer with graphene to the surface of the substrate, and lowering a mask on the polymer side onto a heated substrate, so that the polymer contacts the surface of the substrate to contact and melt and adhere to the substrate;
step s7: removing the copolymer attached to the substrate; removing the methacrylate polymer, and then flushing by using isopropanol to obtain a large-area transferred graphene nano film as a bottom gate;
step s8: transferring the h-BN two-dimensional material; transferring the prepared h-BN two-dimensional material to a substrate sheet with a graphene nano film by using a transfer platform;
step s9: preparation of Ga 2 O 3 A channel layer; in a transfer platform, selecting beta-Ga with proper size 2 O 3 A thin film transferred and stacked onto the h-BN two-dimensional material;
step s10: transferring the gate dielectric and the graphene gate to the upper part of the channel layer; the h-BN two-dimensional material is contacted with a target substrate and kept stand, and h-BN gate dielectric is deposited above the channel layer; then adhering the transfer film on the substrate close to the sample, cooling, soaking and flushing to remove the methacrylate polymer, and completing the manufacture of a layer of full-surrounding gate structure;
step s11: transferring the h-BN two-dimensional material onto the top gate; selecting an h-BN two-dimensional material, and transferring the h-BN two-dimensional material to the position above a full-surrounding structure of a first layer of a bottom gate-gate medium-channel-medium-top gate of the device by using a transfer platform;
step s12: manufacturing a second laminated full-surrounding grid; repeating the steps s9 and s10, and forming a single layer of Ga 2 O 3 Building a layer of same repeated stacking structure on the basis of the full-surrounding gate device of the channel;
step s13: transferring source and drain metal electrodes and annealing to form ohmic contact; the evaporated Au/Ti metal electrode is transferred and then annealed to form a good ohmic contact.
6. The method according to claim 5, wherein: in the step s1, the beta-Ga 2 O 3 The doping type of the crystal is n type, and the doping concentration is 1 multiplied by 10 16 ～2×10 18 cm -3 The thickness is 100 nm-200 nm.
7. The method according to claim 5, wherein: in step s13, the method for manufacturing the metal electrode adopts a method of transferring by using a transfer tape after vapor deposition, or builds a laminated device after manufacturing the electrode on the substrate material by using a photoetching mode.
8. The method according to claim 5, wherein: in the step s6, the transfer mode is realized by a transfer mode formed by the methacrylate copolymer, the adhesive tape and the mechanical transparent glass, and the graphene film and the transfer mode are attached to the target substrate together and then dissolved to wash out the copolymer to obtain the graphene nano film with high integrity.
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