CN210325807U - Gallium oxide-based field effect transistor - Google Patents
Gallium oxide-based field effect transistor Download PDFInfo
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- CN210325807U CN210325807U CN201921416886.2U CN201921416886U CN210325807U CN 210325807 U CN210325807 U CN 210325807U CN 201921416886 U CN201921416886 U CN 201921416886U CN 210325807 U CN210325807 U CN 210325807U
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Abstract
The utility model discloses a gallium oxide base field effect transistor belongs to the technical field of semiconductor electron, including the substrate, substrate upper portion is equipped with the insulating layer, insulating layer upper portion is equipped with the gallium oxide channel layer, two-dimentional laminar material interface modification layer is equipped with respectively at gallium oxide channel layer upper portion both ends, both ends two-dimentional laminar material interface modification layer upper portion is equipped with source leakage district electrode respectively, gallium oxide channel layer upper portion is two be equipped with the dielectric layer between the source leakage district electrode, dielectric layer upper portion is equipped with the gate electrode; the utility model discloses be equipped with two-dimentional laminar material interface modification layer, overcome prior art's metal and directly make contact characteristic receive surface oxygen to hang the key influence and contact the great problem of resistance with gallium oxide channel layer contact for gallium oxide base field effect transistor has lower electrode contact resistance, higher carrier injection efficiency.
Description
Technical Field
The utility model belongs to the technical field of semiconductor electron, concretely relates to gallium oxide base field effect transistor.
Background
Gallium oxide is a novel wide bandgap semiconductor material, has a plurality of excellent physical properties (such as large forbidden band width of-4.9 eV, large breakdown electric field intensity of-8 MV/cm and the like), and shows great application prospects in devices such as field effect transistors, solar blind photodetectors, transparent conductive electrodes, information memories, LED substrates and the like. In the current semiconductor development process, contact is a critical step, which affects the performance and power consumption of the whole device. Obtaining good ohmic contact is a prerequisite for the development and application of gallium oxide based devices.
The patent document "a method for enhancing ohmic contact of gallium oxide semiconductor device" (application No. 201711303287.5 application publication No. CN 107993934A) applied by the institute of microelectronics of Chinese academy of sciences is disclosed as a method for enhancing ohmic contact of gallium oxide semiconductor device. The method carries out plasma etching surface treatment on the gallium oxide semiconductor, and regulates and controls the roughness, oxygen vacancy and oxygen dangling bond of the surface of the gallium oxide semiconductor by controlling the etching process, so that the surface roughness is reduced and the oxygen vacancy is increased; and growing a metal layer with a corresponding work function on the gallium oxide semiconductor subjected to the plasma etching surface treatment to form the ohmic contact semiconductor device. However, the method still has the defects that the etching process damages the gallium oxide interface, the number of oxygen dangling bonds cannot be well regulated, the stability of ohmic contact characteristics is poor due to unstable oxygen vacancy defects of the channel layer, and in addition, the oxygen dangling bonds react with the metal electrode to form oxides, so that the interface contact resistance is difficult to accurately regulate and control.
The paper "Oxidized Metal Schottky Contacts on (010) β -Ga" published by Caixia Hou et al authors2O3”(IEEE Electron Device Letters, vol.40, No.2,2019) investigated the barrier height when forming a heterojunction interface with metals Ir, Pd, Pt, Ag, Au and their oxides and gallium oxide. In the preparation process of the heterojunction, a layer of metal oxide is formed on the surface of gallium oxide under the oxidation condition, so that the heterojunction interface has good thermal stability. However, the preparation method of the heterojunction interface still has the defects that the formed metal oxide can improve the Schottky barrier of the interface, and the Fermi level pinning effect is serious.
SUMMERY OF THE UTILITY MODEL
The utility model provides a gallium oxide base field effect transistor to two-dimentional stratified material decorates gallium oxide channel layer surface as metal-gallium oxide interface modification layer, has overcome prior art's metal and has directly hung the key influence and contact the great problem of resistance by surface oxygen with gallium oxide channel layer contact messenger contact characteristic.
The utility model provides a gallium oxide base field effect transistor, which comprises a substrate, substrate upper portion is equipped with the insulating layer, insulating layer upper portion is equipped with the gallium oxide channel layer, gallium oxide channel layer upper portion both ends are equipped with two-dimentional laminar material interface modification layer respectively, both ends two-dimentional laminar material interface modification layer upper portion is equipped with source leakage district electrode respectively, gallium oxide channel layer upper portion is two be equipped with the dielectric layer between the source leakage district electrode, dielectric layer upper portion is equipped with the gate electrode.
Preferably, the two-dimensional layered material in the two-dimensional layered material interface modification layer is any one of hexagonal boron nitride, graphene, black phosphorus and a transition metal chalcogenide.
Preferably, the thickness of the two-dimensional layered material interface modification layer is 1-5 nm.
Preferably, the substrate is a silicon substrate.
Preferably, the insulating layer is SiO grown on the surface of the substrate2A film.
Preferably, the source drain region electrode and the gate electrode are made of metal conductive materials respectively.
Preferably, the dielectric layer is Al2O3。
The utility model provides the mechanism of high gallium oxide base device contact characteristic:
because two-dimentional lamellar material has high carrier mobility, excellent optics and electrical property, and two-dimentional lamellar material comprises one or several atomic layer, they do not like those typical nanostructure to be puzzled by dangling bond and surface defect state, and its surface is saturated chemical bond, is connected by van der waals' force usually between the adjacent layer, therefore, the utility model discloses utilize two-dimentional lamellar material as interface modification layer, after establishing the two-dimentional lamellar material of one or several atomic layer thickness on gallium oxide channel layer surface, establish the metal level again, thereby make the utility model discloses a gallium oxide based field effect transistor has lower electrode contact resistance, higher carrier injection efficiency.
Compared with the prior art, the utility model following beneficial effect has:
because the utility model discloses the interface modification layer of selecting is typical two-dimentional laminar material, has overcome prior art's metal and has directly made contact characteristic hang the key influence and contact the great problem of resistance by surface oxygen with gallium oxide channel layer contact, makes the utility model discloses a gallium oxide base field effect transistor has lower electrode contact resistance, helps improving carrier injection efficiency.
Drawings
Fig. 1 is a schematic structural diagram of a gallium oxide-based field effect transistor provided by the present invention;
fig. 2 is a graph of the contact resistance of the gallium oxide-based field effect transistor without a modification layer calculated by using a linear transfer model in example 1;
FIG. 3 is a MoS with a single layer calculated using a linear transfer model in example 12A contact resistance curve graph of the gallium oxide-based field effect transistor of the modification layer;
FIG. 4 is a graph of the contact resistance of the gallium oxide based FET with a single layer of black phosphorus calculated using a linear transfer model in example 2;
fig. 5 is a graph of the contact resistance of the gallium oxide-based field effect transistor containing single-layer graphene calculated by the linear transfer model in example 3.
Description of reference numerals:
1. the structure comprises a substrate, 2, an insulating layer, 3, a gallium oxide channel layer, 4, a two-dimensional layered material interface modification layer, 5, a source and drain region electrode, 6, a dielectric layer, 7 and a gate electrode.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, the present invention will be further described with reference to the following specific embodiments and accompanying drawings, but the embodiments are not limited to the present invention.
The gallium oxide-based field effect transistor of the present invention using two-dimensional layered material as the metal-gallium oxide interface modification layer is further described with reference to fig. 1.
The utility model provides a pair of gallium oxide base field effect transistor, including substrate 1, 1 upper portion of substrate is equipped with insulating layer 2,2 upper portions of insulating layer are equipped with gallium oxide channel layer 3, 3 upper portion both ends of gallium oxide channel layer are equipped with two-dimentional laminar material interface modification layer 4 respectively, both ends 4 upper portions of two-dimentional laminar material interface modification layer are equipped with source leakage district electrode 5 respectively, 3 upper portions of gallium oxide channel layer are two be equipped with dielectric layer 6 between source leakage district electrode 5, 6 upper portions of dielectric layer are equipped with gate electrode 7.
The utility model discloses a two-dimentional laminar material interface modification layer 4 adopts chemical vapor deposition technique, supersound liquid phase among the prior art to peel off the technique in the following embodiment, and gallium oxide channel layer 3 adopts molecular beam epitaxy technique, chemical vapor deposition technique, and source leakage electrode 5 and gate electrode 7 electrode adopt the thermal evaporation method of prior art, obtain respectively the utility model discloses a gallium oxide base field effect transistor.
Example 1
A gallium oxide based field effect transistor comprises a silicon substrate 1, wherein an insulating layer 2 is arranged on the upper part of the silicon substrate 1, and SiO2A gallium oxide channel layer 3 is arranged on the upper part of the insulating layer 2, Ag source drain region electrodes 5 are respectively arranged at two ends of the upper part of the gallium oxide channel layer 3, and the gallium oxide channel layer3 Al is arranged between the two Ag source drain region electrodes 5 on the upper part2O3A dielectric layer 6, an Ag gate electrode 7 arranged on the upper part of the dielectric layer 6, and a single-layer MoS2An interface modification layer 4, and the single-layer MoS2The interface modification layer 4 is respectively positioned between the two Ag source drain region electrodes 5 and the gallium oxide channel layer 3.
The gallium oxide-based field effect transistor is prepared by the following steps:
cutting a circular silicon wafer with the diameter of 10cm into rectangular small pieces of 2.5cm multiplied by 1.5cm by taking an n-type silicon wafer with the crystal orientation of (100) as a substrate, wherein the thickness of the silicon substrate 1 is 200 mu m;
immersing a silicon wafer into a small beaker filled with acetone, sealing the opening of the beaker, putting the beaker into an ultrasonic oscillator for cleaning for 20min, then putting the small beaker filled with absolute ethyl alcohol into the silicon wafer cleaned with acetone, oscillating and cleaning for 10min, replacing clean absolute ethyl alcohol again, oscillating and cleaning for 10min, and drying the cleaned silicon wafer with dry hot air after ensuring that surface oil stains and dust are removed;
flatly spreading the dried silicon wafer in the middle of a quartz tube, sending into a high-temperature horizontal tube type resistance furnace for thermal oxidation treatment, setting the temperature at 950 ℃, timing for 1h after the set temperature is reached, and keeping Si and O at high temperature2Reaction is carried out to form a layer of compact SiO on the surface of the Si sheet2Film, SiO2The thickness of the insulating layer 2 is about 200 nm;
will be covered with SiO2Naturally cooling the Si sheet of the film, and taking out for later use;
adopting laser molecular beam epitaxial growth technology, covering with SiO in step 12As a substrate, a thin Si wafer was used, and Ga having a purity of 99.99% was used2O3And Al2O3Ceramic target by alternatively growing Ga2O3And Al2O3Ultra-thin film, adjusting Ga2O3/Al2O3Laser pulse number ratio controlComposition for forming a thin film with a vacuum degree of 10-6Pa, substrate temperature 850 deg.C, oxygen pressure 3X 10-1Pa, laser energy and frequency of 400mJ and 1Hz, target spacing of 4cm, Ga2O3And Al2O3Selecting the laser pulse frequency ratio: 200/20, 200/40, 200/80, 200/100, 200/120, 200/140, 200/160, 200/180;
annealing the film in situ for 30 min;
carrying out post annealing on the film, and annealing for 10 hours at 1000 ℃ in an air atmosphere to obtain a gallium oxide channel layer 3 with the thickness of about 200 nm;
by CVD method using tube furnace on SiO2Growth of single-layer MoS on Si substrate2(ii) a Firstly, SiO is added2The Si substrate is sequentially ultrasonically cleaned by acetone, ethanol and deionized water, and then is dried by nitrogen;
SiO of the substrate2Placed face down in a container containing 3mg of 99.95% pure MoO3Al of (2)2O3On the crucible, the crucible was then placed in a quartz tube of a three-zone CVD furnace, and another crucible containing 500mg of 99.99% S purity was placed upstream of the quartz tube;
vacuumizing the quartz tube, flushing the quartz tube with Ar for 10 to 15min, and removing oxygen in the tube;
setting a furnace to start heating at a speed of 20 ℃/min, keeping constant for 10min after heating to 300 ℃, then heating to 720 ℃ at a speed of 50 ℃/min, keeping constant for 10min at 720 ℃, then starting cooling, and opening a furnace cover when the furnace temperature is reduced to 700 ℃, so that the quartz tube is rapidly cooled;
in the furnace temperature of 720-700 ℃, the flow rate of Ar is controlled to be 50sccm, and the flow rate of Ar in other time is controlled to be 200sccm, so as to obtain single-layer MoS2The thickness of the interface modification layer 4 is about 1 nm;
in SiO2Growth of single-layer MoS on Si substrate2Then, firstly on its surfaceSpin coating a layer of polystyrene, heating and curing on a hot table, immersing the cured polystyrene in 40% HF solution for 5-10 seconds, taking out, and vertically and slowly immersing the sample in deionized water with the surface tension of water causing MoS to adhere2The polystyrene film is completely separated from the substrate, so that the polystyrene film floats on the surface of the deionized water;
the polystyrene film is fished up in deionized water by the film prepared in the step 2, so that the single-layer MoS is formed2Transferring gallium oxide channel layer, and dissolving single layer MoS with acetone2The above polystyrene;
only a single-layer MoS is left above a source drain region by using an ion etching method2；
adopting a plasma ALD method, and masking the MoS layer without being coated with a monolayer2Covered Ga2O3Growing Al on the channel layer2O3Insulating layer 6, Al2O3The thickness of the insulating layer 6 is 15nm, the growth temperature is 180 ℃, and the insulating layer is not doped to form an insulating gate dielectric layer of the device.
putting the prepared part into a vacuum chamber, and obtaining an Ag source drain electrode 5 and an Ag gate electrode 7 with the thickness of 300nm by a thermal evaporation method through a mask;
FIG. 2 is a graph of contact resistance of a gallium oxide-based field effect transistor without a modification layer calculated by using a linear transmission model in the prior art; FIG. 3 shows that the present invention utilizes linear transmission model to calculate the obtained MoS containing single layer2A contact resistance curve graph of the gallium oxide-based field effect transistor of the modification layer; as can be seen by comparing FIGS. 2 and 3, the introduction of a single layer of MoS2After the modification layer, the contact resistance of sample reduces to 0.16 omega mum from 1.18 omega mum, explains from this the utility model overcomes the direct contact of metal and gallium oxide channel layer of prior art makes the contact characteristic hang the key influence and contact the great problem of resistance by surface oxygen, makes the utility model discloses a gallium oxide base field effect transistor has lowerElectrode contact resistance.
Example 2
A gallium oxide-based field effect transistor has the same structure as that of embodiment 1, except that a two-dimensional layered material interface modification layer 4 adopts black phosphorus, and a metal electrode adopts an Au electrode;
the gallium oxide-based field effect transistor is prepared by the following steps:
respectively putting the silicon substrate 1 into a detergent, deionized water, acetone and an alcohol solution, and respectively carrying out ultrasonic cleaning for 20min to obtain a cleaned field effect transistor substrate 1, wherein the thickness of the silicon substrate 1 is 200 mu m;
the cleaned silicon wafer is flatly laid in the middle of a quartz tube in order, and sent into a high-temperature horizontal tube type resistance furnace for thermal oxidation treatment, the temperature is set to 900 ℃, the constant temperature is kept for 1h when the temperature reaches 900 ℃, and the Si wafer and O wafer are kept at high temperature2Reaction is carried out to form a layer of compact SiO on the surface of the Si sheet2Film, SiO2The thickness of the insulating layer 2 is about 200 nm;
will be covered with SiO2Naturally cooling the Si sheet of the film, and taking out for later use;
adopting laser molecular beam epitaxial growth technology, covering with SiO in step 12As a substrate, a thin Si wafer was used, and Ga having a purity of 99.99% was used2O3And Al2O3Ceramic target by alternatively growing Ga2O3And Al2O3Ultra-thin film, adjusting Ga2O3/Al2O3The ratio of the laser pulse times controls the components of the film, the background vacuum degree is set to 10-6Pa, substrate temperature 850 deg.C, oxygen pressure 3X 10-1Pa, laser energy and frequency of 400mJ and 1Hz, target spacing of 4cm, Ga2O3And Al2O3Selecting the laser pulse frequency ratio: 200/20, 200/40, 200/80, 200/100, 200/120, 200/140, 200/160, 200/180;
annealing the film in situ for 30 min;
carrying out post annealing on the film, and annealing for 10 hours at 1000 ℃ in an air atmosphere to obtain a gallium oxide channel layer 3 with the thickness of about 200 nm;
firstly, preparing a black phosphorus nanosheet by adopting an ultrasonic liquid phase stripping method: grinding 100mg of black phosphorus by using a balance, placing 100ml of deionized water in a conical flask by using a measuring cylinder, adding the ground black phosphorus into the conical flask filled with the deionized water, filling argon into the conical flask, sealing the conical flask to prevent oxidation, then placing the conical flask into an ultrasonic cleaner for ice bath ultrasonic treatment, wherein the power is 180W, the time is 40h, then centrifugally separating the ultrasonic nano black phosphorus dispersion liquid, setting the rotating speed to 3000rpm, and collecting the supernatant to obtain the black phosphorus nanosheet dispersion liquid;
dripping the obtained black phosphorus nanosheet dispersion liquid on a copper foil to form a film, spin-coating polymethyl methacrylate (PMMA) on the surface of black phosphorus by using a spin coater, heating for 5min to dry the PMMA, then soaking the PMMA/black phosphorus/copper foil in HCl solution for 15min, and removing the copper foil; removing the residues of hydrochloric acid and hydrogen peroxide by using deionized water, flatly putting polymethyl methacrylate PMMA/black phosphorus into acetone by using a PET sterile plastic sheet for soaking for 20 minutes, then cleaning by using deionized water, and drying by using nitrogen to obtain a black phosphorus interface modification layer 4 with the thickness of about 2 nm;
lightly placing the polymethyl methacrylate PMMA/black phosphorus obtained in the third step on the gallium oxide channel layer prepared in the second step, annealing for 15min at 100 ℃ to enable the black phosphorus to be completely combined with the gallium oxide channel layer, removing the polymethyl methacrylate PMMA by using acetone, finally cleaning by using deionized water, and drying by using nitrogen;
only leaving black phosphorus above the source drain region by using an ion etching method;
by plasma ALDMethod of masking Ga not covered by black phosphorus2O3Growing Al on the channel layer2O3Insulating layer 6, Al2O3The thickness of the insulating layer 6 is 20nm, the growth temperature is 200 ℃, and the insulating layer is not doped to form an insulating gate dielectric layer of the device;
and putting the prepared part into a vacuum chamber, and obtaining the 300nm Au source/drain electrode 5 and the Au gate electrode 7 by a thermal evaporation method through a mask.
As shown in fig. 4, the contact resistance of the sample was calculated to be reduced to 0.23 Ω μm using a linear transfer model.
Example 3
A gallium oxide-based field effect transistor has the same structure as that of embodiment 1, and is different in that a silicon substrate 1 is a heavily doped P-Si (100) single-side polished wafer, a two-dimensional layered material interface modification layer 4 adopts single-layer graphene, and a metal electrode adopts an Au electrode.
The gallium oxide-based field effect transistor is prepared by the following steps:
cleaning a heavily doped P-Si (100) single-side polished wafer with acetone, dilute hydrochloric acid, absolute ethyl alcohol and deionized water in sequence, and then treating for 20min in ultrasonic; adopting a thermal growth method, controlling the temperature at 1100 ℃, firstly introducing dry high-purity oxygen (more than or equal to 99.99 percent), then introducing dry oxygen into a water bottle with the water temperature of 95 ℃ to obtain a mixed oxygen-water vapor gas source, and then introducing the dry oxygen for 0.5h, 1h and 1h respectively to form a layer of compact SiO on the surface of the Si sheet2Film, thickness of the silicon substrate 1 obtained was about 200 μm, SiO2The thickness of the insulating layer 2 is about 200 nm;
SiO in the previous step by MOCVD2Growing gallium oxide film on the film, doping Sn element during the growth process, the doping concentration is lower than 1 × 1020cm-3To do so byForming an n-type conductive channel layer, the thickness of the obtained gallium oxide channel layer 3 being about 200 nm;
selecting a copper foil with the thickness of 25 micrometers, cleaning, putting the copper foil into a quartz tube cavity of CVD equipment, introducing hydrogen with the flow of 30sccm into the quartz tube, keeping the pressure at 80Pa, heating the quartz tube to 1000 ℃ from room temperature, annealing for 20 minutes, introducing 5sccm methane for 20 minutes, forming graphene on the surface of the copper foil, keeping the flow of the methane and the hydrogen unchanged after growth is completed, and quickly cooling. When the temperature is reduced to normal temperature, obtaining single-layer graphene positioned on the surface of the copper foil, wherein the thickness of the single-layer graphene interface modification layer 4 is about 5 nm;
spin-coating a layer of PMMA colloid on the surface of the graphene which is obtained in the last step and takes the copper foil as a substrate, and baking the graphene colloid for 10 minutes at 50 ℃ in a hot plate electric furnace to form a uniform glue film; then, graphene with copper foil as a substrate was placed in 5% of Fe (NO)3)3Corroding the copper foil in the solution for about 10 hours, then placing PMMA glue carrying graphene in deionized water for cleaning for multiple times, slightly fishing the prepared substrate by the two steps, baking the substrate on an electric furnace at 50 ℃ until the water on the surface is evaporated, and then respectively baking the substrate for 10 minutes at 80 ℃ and 120 ℃ to ensure that the graphene and the gallium oxide channel layer form close contact;
method for preparing Ga uncovered by single-layer graphene by adopting plasma ALD (atomic layer deposition), and method for preparing Ga uncovered by single-layer graphene by using mask method2O3Growing Al on the channel layer2O3Insulating layer 6, Al2O3The thickness of the insulating layer 6 is 25nm, the growth temperature is 300 ℃, and the insulating layer is not doped to form an insulating gate dielectric layer of the device;
and putting the prepared part into a vacuum chamber, and obtaining the 300nm Au source/drain electrode 5 and the Au gate electrode 7 by a thermal evaporation method through a mask.
As shown in fig. 5, the contact resistance of the sample was calculated to be reduced to 0.09 Ω μm using a linear transfer model.
According to the above-mentioned result, the utility model discloses utilize two-dimentional laminar material as the interface modification layer, after the two-dimentional laminar material of one or several atomic layer thickness is established on gallium oxide channel layer surface, the metal level of rebuilding, it makes contact characteristic receive surface oxygen to hang the key influence and contact the great problem of resistance directly to have overcome prior art's metal and have contacted with gallium oxide channel layer, makes the utility model discloses a gallium oxide based field effect transistor has lower electrode contact resistance, is favorable to improving carrier injection efficiency.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (7)
1. The utility model provides a gallium oxide base field effect transistor, includes substrate (1), substrate (1) upper portion is equipped with insulating layer (2), insulating layer (2) upper portion is equipped with gallium oxide channel layer (3), gallium oxide channel layer (3) upper portion both ends are equipped with two-dimentional laminar material interface modification layer (4) respectively, both ends two-dimentional laminar material interface modification layer (4) upper portion is equipped with source leakage district electrode (5) respectively, gallium oxide channel layer (3) upper portion is two be equipped with dielectric layer (6) between source leakage district electrode (5), dielectric layer (6) upper portion is equipped with gate electrode (7).
2. The gallium oxide-based field effect transistor according to claim 1, wherein the two-dimensional layered material in the two-dimensional layered material interface modification layer (4) is any one of hexagonal boron nitride, graphene, black phosphorus, and a transition metal chalcogenide.
3. The gallium oxide-based field effect transistor according to claim 1, wherein the thickness of the two-dimensional layered material interface modification layer (4) is 1 to 5 nm.
4. Gallium oxide-based field effect transistor according to claim 1, characterized in that the substrate (1) is a silicon substrate.
5. The gallium oxide-based field effect transistor according to claim 4, characterized in that the insulating layer (2) is SiO grown on the surface of the substrate (1)2A film.
6. The gallium oxide-based field effect transistor according to claim 1, wherein the source/drain region electrode (5) and the gate electrode (7) are each a metal conductive material.
7. The gallium oxide-based field effect transistor according to claim 1, wherein the dielectric layer (6) is Al2O3。
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114823858A (en) * | 2022-04-28 | 2022-07-29 | 电子科技大学 | Novel structure gallium oxide field effect transistor power device |
| WO2022256790A1 (en) * | 2021-06-02 | 2022-12-08 | University Of Kansas | Atomically tuned ultrathin memristors |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022256790A1 (en) * | 2021-06-02 | 2022-12-08 | University Of Kansas | Atomically tuned ultrathin memristors |
| CN114823858A (en) * | 2022-04-28 | 2022-07-29 | 电子科技大学 | Novel structure gallium oxide field effect transistor power device |
| CN114823858B (en) * | 2022-04-28 | 2024-01-26 | 电子科技大学 | Gallium oxide field effect transistor power device with novel structure |
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