CN106898644B - High-breakdown-voltage field effect transistor and preparation method thereof - Google Patents

High-breakdown-voltage field effect transistor and preparation method thereof Download PDF

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CN106898644B
CN106898644B CN201710050362.5A CN201710050362A CN106898644B CN 106898644 B CN106898644 B CN 106898644B CN 201710050362 A CN201710050362 A CN 201710050362A CN 106898644 B CN106898644 B CN 106898644B
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breakdown
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CN106898644A (en
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冯倩
方立伟
韩根全
李翔
邢翔宇
黄璐
张进成
郝跃
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Xidian University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/516Insulating materials associated therewith with at least one ferroelectric layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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Abstract

The invention discloses a kind of high-breakdown-voltage field effect transistors and preparation method thereof, from bottom to top include substrate (1), Ga2O3Epitaxial layer (2) and low-doped n-type Ga2O3Film (3), film is equipped with doped n-type Si ion implantation area (4) and insulation gate medium (7), ion implanted region is equipped with source electrode (5) and drain electrode (6), the gate medium that insulate is equipped with the organic insulation medium (8) of 300~500nm thickness, organic insulation medium is by P (VDF-TrFE), Ag nano particle adulterates P (VDF-TrFE), ZnS nano particle adulterates P (VDF-TrFE) and CCTO nano particle doping P (VDF-TrFE) is constituted, and it is equipped with the grid field plate (9) that length is 1~3 μm, gate electrode is provided on the grid field plate.Breakdown voltage of the present invention is high, is used as power device and High-tension Switch Devices.

Description

High-breakdown-voltage field effect transistor and preparation method thereof
Technical field
The invention belongs to new semiconductor materials devices, and in particular to a kind of field effect transistor is used as power device Part and High-tension Switch Devices.
Background technique
As MOSFET element size constantly reduces, traditional silicon MOS device has suffered from lot of challenges, wherein breakdown voltage It is difficult to meet the requirements growing demand, becomes one of the key factor for influencing further to promote device performance.Ga2O3With with SiC, GaN are that the third generation semiconductor material of representative compares, and have broader forbidden bandwidth, disruptive field intensity is equivalent to the 20 of Si Times or more, the 2 times or more of SiC and GaN, in theory, in the Metal-oxide-semicondutor field-effect for manufacturing identical pressure resistance When transistor MOSFET power device, the conducting resistance of device can be reduced to the 1/3, Ga of the 1/10 of SiC, GaN2O3The Bali of material The gal figure of merit is 18 times of SiC, 4 times or more of GaN material, therefore Ga2O3Be it is a kind of have excellent performance be suitable for power device and high pressure The semiconductor material with wide forbidden band of switching device preparation.
In order to improve Ga2O3The performance of metal-oxide semiconductor fieldeffect transistor MOSFET power device, it is just necessary Breakdown voltage of the raising device under spent condition, and Ga2O3Metal-oxide semiconductor fieldeffect transistor MOSFET element Breakdown occur mainly in grid by drain terminal, therefore to improve the breakdown voltage of device, it is necessary to divide the electric field in grid leak region again Cloth, especially reduction grid lean on drain terminal electric field, for this purpose, people by using be added field plate method by the breakdown voltage of device from 415V is improved to 755V, while the on-off ratio of device is still greater than 109
Existing metal-oxide semiconductor fieldeffect transistor MOSFET power device, as shown in Figure 1.
The device is to make oxide layer and metal gate on a semiconductor substrate, and inject to form channel in two sides, in source Leak two outgrowth SiO2, form metal-oxide semiconductor fieldeffect transistor MOSFET element.This metal-oxide- The deficiency of semiconductor FET device is: not high, the usually less than 200V of pressure resistance, with the raising of operating voltage, due to Drain terminal connects high potential, so generating higher electric field near drain terminal, the electronics in electric field is made constantly to be accelerated and obtain energy. Since electronics moves meeting and lattice collisions in the semiconductors, when the energy that electronics obtains is sufficiently large, lattice can be caused to damage, High current is formed, by device breakdown.
Summary of the invention
It is an object of the invention in view of the above shortcomings of the prior art, propose a kind of high-breakdown-voltage field effect transistor And preparation method thereof, to reduce the electric field of drain terminal, improve the breakdown voltage of device.
To achieve the above object, high-breakdown-voltage field effect transistor of the invention includes substrate, Ga from bottom to top2O3Outside Prolong layer and low-doped n-type Ga2O3Film, film are equipped with doped n-type Si ion implantation area and insulation gate medium, infuse in ion Enter and be respectively equipped with source electrode and drain electrode in area, it is characterised in that:
The insulation gate medium is equipped with it with a thickness of 300nm~500nm organic insulation medium, which adopts It is received with by P (VDF-TrFE), Ag nano particle doping P (VDF-TrFE), ZnS nano particle doping P (VDF-TrFE) and CCTO Rice grain adulterates the thin film dielectrics material that P (VDF-TrFE) is constituted;
It is equipped with the grid field plate that length is 1 μm~3 μm in the organic insulation medium, gate electrode is set on the grid field plate.
To achieve the above object, the method that the present invention makes high-breakdown-voltage field effect transistor, includes the following steps:
1) to being epitaxially grown on the substrate Ga2O3The sample of film carries out organic washing, clear with the deionized water of flowing After washing, it is put into HF:H2Corrode 30s~60s in the solution of O=1:1, then is cleaned with the deionized water of flowing, and use high pure nitrogen Drying;
2) sample after cleaning is put into the SiO that deposition thickness in PECVD device is 50nm~70nm2Exposure mask;
3) to completion SiO2The sample of exposure mask deposit carries out photoetching, forms ion implanted region, and carry out Si ion implanting, infuses Sample is carried out to 1000 DEG C of thermal annealing 30min after entering in nitrogen atmosphere, the silicon ion of injection is activated;
4) sample for completing Si ion implantation activation is put into plasma-reaction-chamber, being passed through flow is 200sccm's Oxygen, setting chamber pressure are 30Pa~40Pa, radio-frequency power 300W, carry out the etching of 10min, to sample to remove sample The photoresist exposure mask on product surface;
5) sample for removing surface exposure mask is put into BOE solution, corrodes 5min, removes the SiO on surface2Exposure mask;
6) photoetching is carried out to the sample after corrosion, forms source electrode and drain electrode region, places into electron beam evaporation platform Metal Ti/Au is steamed, and successively carries out metal-stripping and rapid thermal annealing, forms Ohm contact electrode;
7) to formed Ohm contact electrode sample clean, place into atomic layer deposition apparatus temperature be 300 DEG C, pressure 2000Pa, H2The flow of O and TMAl is under the process conditions of 150sccm, and deposition thickness is 5nm~20nm's Al2O3Insulate gate medium;
8) to completion Al2O3The sample of insulation gate dielectric deposition carries out photoetching, forms organic dielectric P (VDF-TrFE) Depositing region, then put it into BOE solution and corrode 10s, to remove the Al of the depositing region2O3
9) configured P (VDF-TrFE) solution is spun on sample with the revolving speed of 3000rpm, then puts it into baking oven In with 130 DEG C of temperature to sample toast 24 hours;
10) photoetching is carried out to the sample for completing the preparation of P (VDF-TrFE) ferroelectric media, forms gate electrode region and grid field plate Region, then put it into electron beam evaporation platform and evaporate Ni with a thickness of 20nm~50nm, metal Au with a thickness of 100nm~200nm, Ni/Au metal, then removed, complete the production of entire device.
The present invention has the advantage that
1. the present invention has field plate and is adjusted grid by leakage using the medium below organic ferroelectric media alternative field plate Hold electric field effect, and when grid leak is reverse-biased, gate electrode apply negatively biasing voltage be continuously increased in the case where when organic The upper surface dipole negatively charged for positive charge, lower surface is formed inside ferroelectric media, thus to the electricity in semiconductor material Son generates the effect repelled, so that grid reduce by the carrier concentration of drain terminal, electric field also reduces therewith, further improves device Breakdown voltage;
2. the present invention can be obtained organic ferroelectric media only by the mode of spin coating and baking, prepared compared with existing technology Simple process.
Detailed description of the invention
Fig. 1 is existing MOSFET element structural schematic diagram;
Fig. 2 is device top view of the invention;
Fig. 3 is the schematic diagram of the section structure of the invention;
Fig. 4 is device process flow schematic diagram of the present invention.
Specific implementation
Below in conjunction with attached drawing, the present invention will be described in detail.However, the present invention can come in many different forms in fact It applies, and should not be construed as limited to embodiment set forth herein.On the contrary, thesing embodiments are provided so that the disclosure will be thorough With it is complete, and fully convey the scope of the present invention to those skilled in the art
Referring to Fig. 2 and Fig. 3, device of the present invention includes substrate 1, Ga2O3Epitaxial layer 2, low-doped n-type Ga2O3Film 3, ion Injection region 4, source electrode 5, drain electrode 6, insulation gate medium 7, organic insulation medium 8, gate electrode and grid field plate 9;Wherein substrate 1、Ga2O3Epitaxial layer 2 and low-doped n-type Ga2O3Film 3 arranges from bottom to top, and ion implanted region 4 and insulation gate medium 7 are positioned at low Adulterate N-shaped Ga2O3On film 3, source electrode 5 and drain electrode 6 are located on ion implanted region 4, and organic insulation medium 8 is located at insulated gate On medium 7, gate electrode and grid field plate 9 are located on organic insulation medium.Wherein:
Organic insulation medium 8 adulterates P (VDF-TrFE), ZnS nano particle using by P (VDF-TrFE), Ag nano particle The thin film dielectrics material of P (VDF-TrFE) and CCTO nano particle doping P (VDF-TrFE) composition are adulterated, with a thickness of 300nm ~500nm;
The length of grid field plate 9 is 1 μm~3 μm;
Substrate 1 uses sapphire or MgO or MgAl2O4Or Ga2O3
Ga2O3The electron concentration of epitaxial layer 2 is 1014cm-3~1016cm-3, thickness is greater than 1 μm;
Low-doped n-type Ga2O3The carrier concentration of film 3 is 1017cm-3~1018cm-3, thickness is greater than 100nm;
The element of the inner injection of ion implanted region 4 is one of Si, Ge or Sn or a variety of, implantation concentration is greater than 2 × 1019cm-3
The gate medium 7 that insulate includes Si3N4、Al2O3、HfO2With one of HfSiO or a variety of, with a thickness of 20nm~ 30nm。
Referring to Fig. 4, the present invention makes high-breakdown-voltage field effect transistor method and provides following three kinds of embodiments:
Example 1, production substrate are sapphire, inject Si ion, and insulation gate medium is Si3N4High-breakdown-voltage field-effect Transistor.
Step 1: cleaning sample, as shown in Fig. 4 (a).
First to being epitaxially grown on the substrate Ga2O3Sample carry out organic washing, cleaned with the deionized water of flowing Afterwards, it is put into HF:H2Corrosion 60s is carried out in the solution of O=1:1;
It is cleaned with the deionized water of flowing, and is dried up with high pure nitrogen again.
Step 2: deposit SiO2Exposure mask, as shown in Fig. 4 (b).
Cleaned sample is put into PECVD device, setting chamber pressure be 2Pa, radio-frequency power 40W, simultaneously It is passed through the SiH that flow is 40sccm4The N for being 10sccm with flow2O, in N-shaped Ga2O3Deposition thickness is the SiO of 50nm on film2 Exposure mask.
Step 3: production ion implanted region, as shown in Fig. 4 (c).
3a) to completion SiO2The sample of exposure mask deposit carries out photoetching, forms ion implanted region;
3b) sample after photoetching is put into ion implanting reaction chamber and carries out Si ion implanting twice, injects energy for the first time Amount is 60keV, and implantation dosage is 3.2 × 1014cm-2;Second of Implantation Energy is 30keV, and implantation dosage is 9.3 × 1013cm-2
3c) sample after Si ion implanting is put into annealing furnace, 1000 DEG C of thermal annealing is carried out in nitrogen atmosphere 30min is to activate the Si ion of injection.
Step 4: removing photoresist, as shown in Fig. 4 (d).
The sample for completing the activation of Si ion implanting is put into plasma-reaction-chamber, setting chamber pressure is 40Pa, Radio-frequency power is 300W, is passed through the oxygen that flow is 200sccm, 10min is etched, to remove the photoresist of sample surfaces.
Step 5: removal SiO2Exposure mask, as shown in Fig. 4 (e).
Sample after completion to be removed to photoresist is put into BOE solution, is corroded 5min, is removed the SiO on surface2Exposure mask.
Step 6: production source and drain electricity electrode, as shown in Fig. 4 (f).
Photoetching is carried out to the sample after corrosion, forms source electrode and drain electrode region, then put it into electron beam evaporation platform Middle evaporated metal Ti/Au, and being removed, wherein metal Ti with a thickness of 50nm, metal Au with a thickness of 200nm, finally exist The 60s rapid thermal annealing that temperature is 550 DEG C is carried out in nitrogen environment, forms Ohm contact electrode.
Step 7: deposit insulation gate medium, as shown in Fig. 4 (g).
It after the sample for forming Ohm contact electrode is cleaned, is put into atomic layer deposition apparatus, is in growth temperature 300 DEG C, pressure 2000Pa, H2The flow of O and TMAl is under the process conditions of 150sccm, then deposits the Si of 20nm thickness3N4 Insulate gate medium.
Step 8: etching insulative gate medium, as shown in Fig. 4 (h).
To completion Si3N4The sample of insulation gate dielectric deposition carries out photoetching, forms organic dielectric P (VDF-TrFE) Depositing region is then placed in 10s in BOE solution, and the Si in region locating for organic insulator will be made by eroding3N4
Step 9: production organic insulator, as shown in Fig. 4 (i).
Configured ferroelectric media P (VDF-TrFE) solution is spun on sample with the revolving speed of 3000rpm, and 130 DEG C baking oven in toast 24 hours.
Step 10: production grid field plate and gate electrode, as shown in Fig. 4 (j).
Photoetching is carried out to the sample for completing the preparation of ferroelectric media P (VDF-TrFE) insulating layer, forms gate electrode region and grid Field plate region places into electron beam evaporation platform and evaporates Ni/Au, wherein W metal with a thickness of 50nm, metal Au with a thickness of Then 200nm is removed, form gate electrode and grid field plate, complete the preparation of entire device.
Example 2, production substrate are Ga2O3, Sn ion is injected, insulation gate medium is HfO2High-breakdown-voltage field-effect it is brilliant Body pipe.
Step 1: cleaning sample, as shown in Fig. 4 (a).
This step is identical as the step 1 of example 1.
Step 2: deposit SiO2Exposure mask, as shown in Fig. 4 (b).
This step is identical as the step 2 of example 1.
Step 3: production ion implanted region, as shown in Fig. 4 (c).
3.1) to completion SiO2The sample of exposure mask deposit carries out photoetching, forms ion implanted region;
3.2) sample after photoetching is put into ion implanting reaction chamber and carries out Sn ion implanting twice, inject energy for the first time Amount is 60keV, and implantation dosage is 3.2 × 1014cm-2;Second of Implantation Energy is 30keV, and implantation dosage is 9.3 × 1013cm-2
3.3) sample after Sn ion implanting is put into annealing furnace, 1000 DEG C of thermal annealing is carried out in nitrogen atmosphere 30min, to be activated to the Sn ion of injection.
Step 4: removing photoresist, as shown in Fig. 4 (d).
This step is identical as the step 4 of example 1.
Step 5: removal SiO2Exposure mask, as shown in Fig. 4 (e).
This step is identical as the step 5 of example 1.
Step 6: production source and drain electricity electrode, as shown in Fig. 4 (f).
Photoetching is carried out to the sample after corrosion, source electrode and drain electrode region is formed, is put into electron beam evaporation platform and evaporates Metal Ti/Au is simultaneously removed, wherein metal Ti with a thickness of 20nm, metal Au with a thickness of 100nm, finally in nitrogen environment The middle 60s rapid thermal annealing for carrying out temperature and being 550 DEG C, forms Ohm contact electrode.
Step 7: deposit insulation gate medium, as shown in Fig. 4 (g).
It after the sample for forming Ohm contact electrode is cleaned, is put into atomic layer deposition apparatus, is in growth temperature 300 DEG C, pressure 2000Pa, H2The flow of O and TMAl is under the process conditions of 150sccm, then deposits the HfO of 20nm thickness2Absolutely Edge gate medium.
Step 8: etching insulative gate medium, as shown in Fig. 4 (h).
To completion HfO2The sample of insulation gate dielectric deposition carries out photoetching, forms organic dielectric P (VDF-TrFE) Depositing region is then placed in 10s in BOE solution, and the HfO in region locating for organic insulator will be made by eroding2
Step 9: production organic insulator, as shown in Fig. 4 (i).
This step is identical as the step 9 of example 1.
Step 10: production grid field plate and gate electrode, as shown in Fig. 4 (j).
Photoetching is carried out to the sample for completing the preparation of ferroelectric media P (VDF-TrFE) insulating layer, forms gate electrode region and grid Field plate region places into electron beam evaporation platform and evaporates Ni/Au, wherein W metal with a thickness of 20nm, metal Au with a thickness of Then 100nm is removed, form gate electrode and grid field plate, complete the preparation of entire device.
Example 3, production substrate are MgAl2O4, Ge ion is injected, insulation gate medium is Al2O3High-breakdown-voltage field-effect Transistor.
Step A: cleaning sample, as shown in Fig. 4 (a).
This step is identical as the step 1 of example 1.
Step B: deposit SiO2Exposure mask, as shown in Fig. 4 (b).
This step is identical as the step 2 of example 1.
Step C: production ion implanted region, as shown in Fig. 4 (c).
C1) to completion SiO2The sample of exposure mask deposit carries out photoetching, forms ion implanted region;
C2) sample after photoetching is put into ion implanting reaction chamber and carries out Ge ion implanting twice, injects energy for the first time Amount is 60keV, and implantation dosage is 3.2 × 1014cm-2;Second of Implantation Energy is 30keV, and implantation dosage is 9.3 × 1013cm-2
C3) sample after Ge ion implanting is put into annealing furnace, 1000 DEG C of thermal annealing is carried out in nitrogen atmosphere 30min is to activate the Ge ion of injection.
Step D: removing photoresist, as shown in Fig. 4 (d).
This step is identical as the step 4 of example 1.
Step E: removal SiO2Exposure mask, as shown in Fig. 4 (e).
This step is identical as the step 5 of example 1.
Step F: production source and drain electricity electrode, as shown in Fig. 4 (f).
Photoetching is carried out to the sample after corrosion, forms source electrode and drain electrode region, then put it into electron beam evaporation platform Middle evaporated metal Ti/Au, and being removed, wherein metal Ti with a thickness of 40nm, metal Au with a thickness of 150nm, finally exist The 60s rapid thermal annealing that temperature is 550 DEG C is carried out in nitrogen environment, forms Ohm contact electrode.
Step G: deposit insulation gate medium, as shown in Fig. 4 (g).
It after the sample for forming Ohm contact electrode is cleaned, is put into atomic layer deposition apparatus, is in growth temperature 300 DEG C, pressure 2000Pa, H2The flow of O and TMAl is under the process conditions of 150sccm, then deposits the Al of 20nm thickness2O3 Insulate gate medium.
Step H: etching insulative gate medium, as shown in Fig. 4 (h).
To completion Al2O3The sample of insulation gate dielectric deposition carries out photoetching, forms organic dielectric P (VDF-TrFE) Depositing region is then placed in 10s in BOE solution, and the Al in region locating for organic insulator will be made by eroding2O3
Step I: production organic insulator, as shown in Fig. 4 (i).
This step is identical as the step 9 of example 1.
Step J: production grid field plate and gate electrode, as shown in Fig. 4 (j).
Photoetching is carried out to the sample for completing the preparation of ferroelectric media P (VDF-TrFE) insulating layer, forms gate electrode region and grid Field plate region places into electron beam evaporation platform and evaporates Ni/Au, wherein W metal with a thickness of 40nm, metal Au with a thickness of Then 150nm is removed, form gate electrode and grid field plate, complete the preparation of entire device.
A kind of high-breakdown-voltage field effect transistor proposed by the invention is described in detail above by preferred embodiment Preparation method, it will be understood by those of skill in the art that not departing from the present invention the foregoing is merely preferred embodiment of the invention In the range of essence, certain denaturation or modification can be made to device architecture of the invention, such as promotion, recessed can also be used in source and drain It falls into source-drain structure or other new constructions such as double grid, FinFET, Ω grid, three grid or encloses grid;Preparation method is also not necessarily limited in example Disclosure of that, all equivalent changes and modifications done according to the claims in the present invention, is all covered by the present invention.

Claims (10)

1. a kind of high-breakdown-voltage field effect transistor includes substrate (1), Ga from bottom to top2O3Epitaxial layer (2) and low-doped n-type Ga2O3Film (3), film are equipped with doped n-type ion implanted region (4) and insulation gate medium (7), divide on ion implanted region It She You source electrode (5) and drain electrode (6), it is characterised in that:
The insulation gate medium (7) is equipped with it with a thickness of 300nm~500nm organic insulation medium (8), the organic insulation medium (8) using by P (VDF-TrFE), Ag nano particle doping P (VDF-TrFE), ZnS nano particle doping P (VDF-TrFE) and CCTO nano particle adulterates the thin film dielectrics material that P (VDF-TrFE) is constituted;
It is equipped with the grid field plate (9) that length is 1 μm~3 μm in the organic insulation medium (8), gate electrode is set on the grid field plate.
2. a kind of high-breakdown-voltage field effect transistor according to claim 1, it is characterised in that: the material of substrate (1) Using sapphire or MgO or MgAl2O4Or Ga2O3
3. a kind of high-breakdown-voltage field effect transistor according to claim 1, it is characterised in that: Ga2O3Epitaxial layer (2) Electron concentration be 1014cm-3~1016cm-3, thickness is greater than 1 μm.
4. a kind of high-breakdown-voltage field effect transistor according to claim 1, it is characterised in that: low-doped n-type Ga2O3 The carrier concentration 10 of film (3)17cm-3~1018cm-3, thickness is greater than 100nm.
5. a kind of high-breakdown-voltage field effect transistor according to claim 1, it is characterised in that: ion implanted region (4) The element of injection is respectively one of Si, Ge or Sn or a variety of, and implantation concentration is greater than 2 × 1019cm-3
6. a kind of high-breakdown-voltage field effect transistor according to claim 1, it is characterised in that: insulation gate medium (7) Including Si3N4、Al2O3、HfO2With one of HfSiO or a variety of, with a thickness of 20nm~30nm.
7. a kind of production method of high-breakdown-voltage field effect transistor, which comprises the steps of:
1) to being epitaxially grown on the substrate Ga2O3Sample carry out organic washing put after being cleaned with the deionized water of flowing Enter HF:H2Corrode 30s~60s in the solution of O=1:1, then is cleaned with the deionized water of flowing and dried up with high pure nitrogen;
2) sample after cleaning is put into the SiO that deposition thickness in PECVD device is 50nm~70nm2Exposure mask;
3) to completion SiO2The sample of exposure mask deposit carries out photoetching, forms ion implanted region, and carry out Si ion implanting, injects it The thermal annealing 30min that sample is carried out to 1000 DEG C in nitrogen atmosphere afterwards, activates the silicon ion of injection;
4) sample for completing the activation of Si ion implanting is put into plasma-reaction-chamber, is passed through the oxygen that flow is 200sccm, Setting chamber pressure is 30Pa~40Pa, radio-frequency power 300W, carries out the etching of 10min, to sample to remove sample table The photoresist exposure mask in face;
5) sample for removing surface exposure mask is put into BOE solution, corrodes 5min, removes the SiO on surface2Exposure mask;
6) photoetching is carried out to the sample after corrosion, forms source electrode and drain electrode region, placed into and steam gold in electron beam evaporation platform Belong to Ti/Au, and carry out metal-stripping and rapid thermal annealing according to this, forms Ohm contact electrode;
7) sample for forming Ohm contact electrode is cleaned, places into atomic layer deposition apparatus and is 300 DEG C, presses in temperature Power is 2000Pa, H2The flow of O and TMAl is under the process conditions of 150sccm, and deposition thickness is the Al of 5nm~20nm2O3Absolutely Edge gate medium;
8) to completion Al2O3The sample of insulation gate dielectric deposition carries out photoetching, forms the shallow lake of organic dielectric P (VDF-TrFE) Product region, then put it into BOE solution and corrode 10s, to remove the Al of the depositing region2O3
9) configured P (VDF-TrFE) solution is spun on sample with the revolving speed of 3000rpm, then put it into baking oven with 130 DEG C of temperature toasts sample 24 hours;
10) photoetching is carried out to the sample for completing the preparation of P (VDF-TrFE) ferroelectric media, forms gate electrode region and grid field plate region Domain, then put it into electron beam evaporation platform and evaporate Ni with a thickness of 20nm~50nm, metal Au is with a thickness of 100nm~200nm's Ni/Au metal, is then removed, and the production of entire device is completed.
8. a kind of production method of high-breakdown-voltage field effect transistor according to claim 7 is wherein formed sediment in step 2) Product SiO2The process conditions of exposure mask: SiH4Flow be 40sccm, N2The flow of O be 10sccm, reaction room pressure for 1Pa~ 2Pa, radio-frequency power 40W.
9. the production method of a kind of high-breakdown-voltage field effect transistor according to claim 7, wherein in step 3) Si ion implanting uses to be injected twice, first time Implantation Energy and implantation dosage are as follows: 60keV, 3.2 × 1014cm-2;Second of note Enter energy and implantation dosage are as follows: 30keV, 9.3 × 1013cm-2
10. a kind of production method of high-breakdown-voltage field effect transistor according to claim 7 is wherein steamed in step 6) Metal Ti with a thickness of 20nm~50nm, metal Au with a thickness of 100nm-200nm, then to sample carry out metal-stripping, finally The rapid thermal annealing of 550 DEG C, 60s is carried out in nitrogen atmosphere environment.
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