CN112701049A - Semiconductor module and packaging method thereof - Google Patents
Semiconductor module and packaging method thereof Download PDFInfo
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- CN112701049A CN112701049A CN202011531222.8A CN202011531222A CN112701049A CN 112701049 A CN112701049 A CN 112701049A CN 202011531222 A CN202011531222 A CN 202011531222A CN 112701049 A CN112701049 A CN 112701049A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000059 patterning Methods 0.000 claims abstract description 18
- 238000003825 pressing Methods 0.000 claims abstract description 7
- 238000002360 preparation method Methods 0.000 claims abstract description 5
- 238000004080 punching Methods 0.000 claims abstract 2
- 229910000679 solder Inorganic materials 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 9
- 238000005520 cutting process Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 5
- 238000005553 drilling Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 238000003754 machining Methods 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 66
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 4
- 238000012858 packaging process Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Abstract
The invention discloses a semiconductor module packaging method and a semiconductor module, wherein the semiconductor module packaging method comprises the following steps: the method comprises the steps of preparation, first combination, pressing, second combination, punching, conduction, plate removal and patterning; the semiconductor module includes: a lead frame including a first conductive portion; a wafer bonded to the first conductive portion; a DAF layer covering the front surface of the lead frame and the wafer; a metal layer, which is bonded to the front surface of the substrate and includes a second conductive portion; the front electrode is electrically connected with the second conductive part; a conductive structure disposed within the DAF layer; one end of the conductive structure is electrically connected with the first conductive part, and the conductive structure leads the back electrode to the front surface of the semiconductor module. According to the packaging method of the semiconductor module and the semiconductor module, the wafer is embedded into the substrate, the product is thinner, the size of the product is smaller, the element density can be improved, double-sided heat dissipation can be realized, the heat dissipation effect is improved, and the electrodes can be led out from the same side.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor module and a method for packaging the same.
Background
With the rapid development of portable electronic products in recent years, various related products are gradually developed towards high density and high performance, and the trend of being light, thin and small.
To the component that both sides all were equipped with the electrode, when the encapsulation, generally weld the component on the base plate earlier, again weld a current conducting plate in the component deviates from the one side of base plate, so, whole semiconductor module packaging structure is thicker, and the size is great, is unfavorable for realizing the miniaturization of product.
Disclosure of Invention
One object of an embodiment of the present invention is to: a method for packaging a semiconductor module is provided, in which a wafer is embedded in a substrate, the packaged product is thinner and smaller in size, the integration level can be improved, and double-sided heat dissipation can be realized.
Another object of an embodiment of the present invention is to: a semiconductor module is provided, in which a chip is embedded in a substrate, the thickness of the product is reduced, the density of elements can be increased, and the heat dissipation effect is improved.
A method of packaging a semiconductor module, comprising:
the preparation method comprises the following steps: placing a lead frame on the processing carrier plate;
a first combining step: adopting a conductive bonding material to bond the back surface of the wafer with the front surface of the lead frame, so that a back electrode of the wafer is electrically connected with the lead frame to form a primary structure;
and (3) laminating: covering and pressing the DAF material on the front surface of the primary structure to form a DAF layer;
a second combining step: arranging a metal layer on the front surface of the DAF layer, and electrically connecting the metal layer with a front surface electrode of the wafer;
a perforation step: processing a via hole penetrating through the DAF layer;
conducting: arranging a conductive structure in the via hole;
removing the plate: removing the processing carrier plate;
patterning step: patterning the lead frame into a patterned conductive layer, the lead frame including a first conductive portion electrically connected to the conductive structure, at least one of the first conductive portions being electrically connected to the back electrode; and etching the metal layer into a patterned conductive layer, wherein the metal layer comprises a second conductive part, at least one second conductive part is electrically connected with the first conductive part through the conductive structure, and at least one second conductive part is electrically connected with the front electrode.
Preferably, before the second combining step, a ball planting step is further included; the ball planting step comprises: planting solder balls on the front electrode;
correspondingly, the second combining step comprises: bonding the metal layer to the solder balls, thereby electrically connecting the metal layer to the front electrode.
Preferably, before the ball mounting step, a wafer providing step is included; the wafer providing step includes: providing a wafer, wherein the wafer comprises a plurality of chips;
correspondingly, the ball planting step comprises the following steps: bonding the solder balls to front electrodes of the wafer on the wafer;
correspondingly, after the ball planting step, the method comprises a cutting step: the cutting step includes: and cutting the wafer to form a plurality of chips.
Preferably, the first bonding step further comprises:
and providing a passive element, combining the back surface of the passive element with the front surface of the lead frame by adopting a conductive combination material, and electrically connecting the electric contact of the passive element with the conductive structure through the first conductive part.
Preferably, in the perforating step: processing the via hole on the DAF layer by a laser drilling processing technology;
in the turning-on step: filling a conductive material into the through hole through a printing process or an electroplating process to form the conductive structure;
in the patterning step: etching a pattern on the lead frame through a photoetching process or an etching process to form a plurality of first conductive parts; and patterning the metal layer through a photoetching process or an etching process to form a plurality of second conductive parts.
A semiconductor module, comprising:
a lead frame which is a patterned conductive layer; the lead frame includes a first conductive portion;
a wafer, wherein a front electrode is arranged on the front surface of the wafer, and a back electrode is arranged on the back surface of the wafer; the back side of the wafer is bonded to the front side of the first conductive portion through a conductive bonding layer;
a DAF layer covering the front side of the lead frame and the die; the DAF layer is combined with the lead frame to form a substrate;
a metal layer which is a second patterned conductive layer; the metal layer is combined on the front surface of the substrate; the metal layer includes a second conductive portion; the front electrode is electrically connected with the second conductive part;
a conductive structure disposed within the DAF layer; one end of the conductive structure is electrically connected with the first conductive part, and the conductive structure is used for leading the back electrode to the front surface of the semiconductor module.
Preferably, the metal layer, the DAF layer and the lead frame are sequentially penetrated through by a through hole; the conductive structure is arranged in the through hole, and one end of the conductive structure, which is deviated from the first conductive part, is electrically connected with the second conductive part.
Preferably, the semiconductor device further includes a solder ball, and the front surface electrode is electrically connected to the second conductive portion through the solder ball.
Preferably, the electronic device further comprises a passive element, wherein the back surface of the passive element is bonded to the front surface of the first conductive part through a conductive bonding layer, and the DAF layer covers the front surface and the side surface of the passive element; the passive element is electrically connected with the conductive structure through the first conductive part.
Preferably, the wafer is an active wafer, the front electrode comprises a source electrode and a gate electrode, and the back electrode comprises a drain electrode;
the second conductive part electrically connected with the source electrode is a source electrode leading-out end, the second conductive part electrically connected with the grid electrode is a grid electrode leading-out end, and the second conductive part electrically connected with the drain electrode is a drain electrode leading-out end.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention has the beneficial effects that: according to the packaging method of the semiconductor module, the wafer is embedded into the substrate, the packaged product is thinner, the size of the product is smaller, and double-sided heat dissipation can be realized; according to the semiconductor module, the wafer is embedded into the substrate, the electrodes of the wafer can be led out from the same surface, the product is thinner, the element density can be improved, double-sided heat dissipation can be realized, and the heat dissipation effect is improved.
Drawings
The invention is explained in more detail below with reference to the figures and examples.
Fig. 1 is a schematic view illustrating a method for packaging a semiconductor module according to an embodiment of the invention;
fig. 2 is a second schematic view illustrating a packaging method of a semiconductor module according to an embodiment of the invention;
fig. 3 is a third schematic view illustrating a packaging method of a semiconductor module according to a third embodiment of the present invention;
FIG. 4 is a fourth schematic view illustrating a packaging method of a semiconductor module according to an embodiment of the present invention;
FIG. 5 is a fifth exemplary illustration of a method for packaging a semiconductor module according to an embodiment of the invention;
fig. 6 is a sixth schematic view illustrating a packaging method of a semiconductor module according to an embodiment of the invention;
fig. 7 is a seventh schematic view illustrating a packaging method of a semiconductor module according to an embodiment of the invention;
fig. 8 is an eighth schematic view illustrating a packaging method of a semiconductor module according to an embodiment of the invention;
fig. 9 is a ninth schematic view illustrating a packaging method of a semiconductor module according to an embodiment of the invention;
fig. 10 is a tenth schematic view illustrating a packaging method of a semiconductor module according to an embodiment of the present invention;
fig. 11 is an eleventh schematic view of a packaging method of the semiconductor module according to an embodiment of the invention, and one of the structural schematic views of the semiconductor module;
fig. 12 is a second schematic structural diagram of a semiconductor module according to an embodiment of the invention;
in the figure: 10. a lead frame; 11. a first conductive portion; 20. a DAF layer; 30. a metal layer; 31. a second conductive portion; 311. a source terminal; 312. a gate terminal; 313. a drain terminal; 40. a wafer; 41. a wafer; 411. a front electrode; 4111. a source electrode; 4112. a gate electrode; 412. a back electrode; 50. a passive element; 61. a conductive bonding material; 62. a conductive bonding layer; 70. a solder ball; 81. a via hole; 82. a conductive structure; 90. and processing the carrier plate.
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, unless otherwise explicitly specified or limited, the terms "connected" and "fixed" are to be understood broadly, e.g., as being fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In fig. 1 to 12, the front surface of the structure in the drawings is an upward surface, and the rear surface is a downward surface.
The invention provides a packaging method of a semiconductor module, which takes a lead frame 10 and DAF materials as a substrate in a pressing way, and a wafer 41 is embedded into the substrate, thus being beneficial to reducing the thickness of a product, further reducing the volume of the product and realizing the miniaturization of the product; moreover, the density of elements in the product can be improved; in addition, the semiconductor module can realize double-sided heat dissipation, and the thinning of the semiconductor module can also improve the heat dissipation effect, so that the heat dissipation performance is good; for a semiconductor module including an active power element, the improvement of heat dissipation performance can improve the working performance of the whole module, and the reliability is improved.
As shown in fig. 1 to 12, in an embodiment of the method for packaging a semiconductor module of the present invention, the method for packaging a semiconductor module includes:
a ball planting step: bonding the solder balls 70 to the front electrodes 411 of the die 41 on the wafer 40;
cutting: cutting the wafer 40 to form a plurality of chips 41;
the preparation method comprises the following steps: placing the lead frame 10 on the die;
a first combining step: bonding the back surface of the wafer 41 to the front surface of the lead frame 10 by using the conductive bonding material 61, so that the back surface electrode 412 of the wafer 41 is electrically connected to the lead frame 10 to form a primary structure; the back surface electrode 412 of the wafer 41 is electrically connected to the lead frame 10; wherein, one, two or more wafers 41 can be combined on the lead frame 10 according to actual requirements;
providing a passive element 50, bonding the back surface of the passive element 50 with the front surface of the lead frame 10 by using a conductive bonding material 61, wherein the electric contact of the passive element 50 is electrically connected with the conductive structure 82 through the first conductive part 11;
and (3) laminating: the front surface of the primary structure is upward, namely the surface of the primary structure provided with the wafer 41 is upward, the DAF material is covered on the front surface of the primary structure, pressure is applied to the DAF material, so that the DAF material is tightly pressed and combined with the front surface of the lead frame 10, the front surface of the wafer 41 and the side surface of the wafer 41, and the DAF layer 20 combined with the lead frame 10 and the wafer 41 is formed on the primary structure; when the DAF material is pressed, a part of the solder ball 70 is exposed from the DAF layer 20; the DAF material is Die Attach Film, which is an insulating adhesive Film;
a second combining step: arranging a metal layer 30 on the front surface of the DAF layer 20, and electrically connecting the metal layer 30 with a front surface electrode 411 of the wafer 41 to form a secondary structure;
a perforation step: processing a via hole 81 which sequentially penetrates through the metal layer 30, the DAF layer 20 and the lead frame 10 in the secondary structure by laser drilling or other drilling processes; the front surface of the lead frame 10 is exposed through the via hole 81;
conducting: filling a conductive material in the via hole 81 to form a conductive structure 82, wherein the conductive structure 82 is combined with the inner wall of the via hole 81, that is, the conductive structure 82 is combined with the metal layer 30, the DAF layer 20 and the lead frame 10;
removing the plate: removing the processing carrier plate 90, and exposing the end face of the conductive structure 82 on the back surface of the lead frame 10;
a first patterning step: patterning the lead frame 10 into a patterned conductive layer, the lead frame 10 including a first conductive portion 11 electrically connected to the conductive structure 82; at least one of the first conductive portions 11 is electrically connected to the back electrode 412 of the wafer 41; at least one first conductive part 11 is electrically connected with the electric contact of the passive component 50
A second patterning step: patterning the metal layer 30 to form a conductive layer, wherein the metal layer 30 includes a second conductive portion 31, at least one of the second conductive portions 31 is electrically connected to the back electrode 412 of the wafer 41 through the conductive structure 82 and the first conductive portion 11, and at least one of the second conductive portions 31 is electrically connected to the front electrode 411; at least one second conductive portion 31 is electrically connected to the electrical contact of the passive component 50 through the conductive structure 82 and the first conductive portion 11.
In this arrangement, both the front surface electrode 411 and the back surface electrode 412 of the substrate-embedded wafer 41 can be led out from the front surface of the semiconductor module, and the electrical contact of the passive element 50 embedded in the substrate can be led out from the front surface of the semiconductor module.
Preferably, the metal layer 30 is a copper foil layer. The copper foil has good conductivity.
The semiconductor module obtained by adopting the packaging method of the invention combines the lead frame 10 and the DAF material as a substrate for application, so that the wafer 41 is conveniently embedded into the circuit substrate, thereby replacing a common PCB (printed Circuit Board), reducing the thickness of the product and being beneficial to the miniaturization design of the product; in the second aspect, a part of the wafer 41 and other electronic components are embedded into the substrate, so that a space is reserved outside the substrate, and other electronic components can be mounted, thereby increasing the density of components in the module and improving the integration level; in the third aspect, the semiconductor module can radiate heat to the outside through the metal layer 30, and can radiate heat to the outside through the lead frame 10, so that double-sided heat radiation is realized, and the heat radiation performance can be improved.
The packaging method is simple and can improve the packaging efficiency. In addition, the electrodes of the wafer 41 in the substrate of the semiconductor module and the electrical contacts of other electronic components are led out from the front surface of the semiconductor module, so that the whole module can be easily bonded with an external device or product or an electronic circuit on a PCB circuit board again.
In this embodiment, the packaging method is implemented according to the arrangement order of the above steps, so that the packaging process is more reasonable and efficient. In other embodiments, the order of the steps may be adjusted according to actual requirements.
In the packaging method of the invention, before the pressing step, the ball is planted on the front electrode 411 of the wafer 41, in the pressing step, when the DAF material is pressed, the solder ball 70 protrudes relative to the surface of the wafer 41, so that the situation that a part of the solder ball 70 penetrates out of the DAF layer 20 and the metal layer 30 is arranged subsequently is easily realized; in the second bonding step, the structure is placed in a reflow oven only by a reflow process, so that the bonding material on the surface of the solder ball 70 is melted and bonded to the metal layer 30, and then is cured, so that the front electrode 411 of the wafer 41 can be bonded to the metal layer 30. The packaging method has the advantages of simple packaging process and higher efficiency.
Specifically, in the ball mounting step, the solder ball 70 is mounted on the front electrode 411 by a reflow process, so that the solder ball 70 is electrically connected to the front electrode 411; in this embodiment, the solder ball 70 is a solder ball, and in other embodiments, the solder ball 70 may also be of other conductive metal structures, as long as a solder bump protruding outward relative to the surface of the wafer 41 and facilitating leading out of the front electrode 411 can be combined with the front electrode 411 of the wafer 41.
In this embodiment, the processing carrier 90 used in the preparation step is a glass carrier, and the processing carrier 90 plays a role of carrying the lead frame 10 so as to facilitate other subsequent packaging processes. Specifically, during the conducting step, the conductive material is conveniently filled in the via hole 81 based on processing the carrier 90, so as to form the conductive structure 82 in the via hole 81 and combined with the wall of the via hole 81.
Specifically, the conductive bonding material 61 may be, but not limited to, a conductive paste, a solder paste, or the like.
In other embodiments, solder balls may not be implanted on the front electrode 411 of the chip 41; after the pressing step, the front electrode 411 may be exposed from the DAF layer 20 by removing the DAF material, the metal layer 30 and the DAF layer 20 are bonded by a conductive or insulating bonding material, and the metal layer 30 and the front electrode 411 are bonded by a conductive bonding material 61.
Preferably, in the conduction step, a conductive material is filled in the via hole 81 through a printing process or an electroplating process, thereby forming the conductive structure 82.
Preferably, in the conducting step, the via hole 81 is filled with a copper material, and the conductive structure 82 is a copper pillar. Copper has good conductive performance and heat dissipation performance.
In the patterning step, a pattern is patterned on the metal layer 30 or the lead frame 10 by a photolithography or etching process, so that the metal layer 30 and the lead frame 10 form a patterned conductive layer, the patterned conductive layer includes a plurality of conductive portions electrically connected to the conductive structure 82, a spacing channel is provided between adjacent conductive portions, and the adjacent conductive portions can be completely independent or electrically connected according to actual requirements. When the two conductive portions are electrically connected, the wafer 41 and the wafer 41, or the wafer 41 and the passive component 50 can be electrically connected.
The passive element 50 may be, but is not limited to, a capacitor, a resistor, an inductor. The number of passive elements 50 may be one, two or more.
The type of the semiconductor wafer 41 of the present invention may be, but is not limited to, a Si wafer 41, a SiC wafer 41, a GaN wafer 41.
In the patterning step, the adjacent conductive parts can be electrically connected and can also be completely separated by a spacing channel so as to be insulated; during scribing, the part aligned with the conductive structure 82 is avoided, thereby ensuring that the conductive part remains connected with the conductive structure 82 after patterning.
As shown in fig. 1 to 12, in an embodiment of the semiconductor module of the present invention, the semiconductor module includes:
a lead frame 10 which is a patterned conductive layer; the lead frame 10 includes a first conductive portion 11;
a wafer 41 having a front surface provided with a front electrode 411 and a back surface provided with a back electrode 412; the back side of the wafer 41 is bonded to the front side of the first conductive portion 11 by a conductive bonding layer 62;
a DAF layer 20 covering the front surface of the lead frame 10 and the wafer 41; the DAF layer 20 is combined with the lead frame 10 to form a substrate;
a metal layer 30 which is a second patterned conductive layer; the metal layer 30 is bonded to the front surface of the substrate; the metal layer 30 includes a second conductive portion 31; the front electrode 411 is electrically connected to the second conductive portion 31;
a conductive structure 82 disposed within the DAF layer 20; one end of the conductive structure 82 is electrically connected to the first conductive part 11, and the conductive structure 82 is used for leading the back electrode 412 to the front surface of the semiconductor module.
According to the semiconductor module, the wafer 41 is embedded into the substrate, the electrodes of the wafer 41 can be led out from the same surface, the thickness of the product is reduced, the density of elements can be improved, double-sided heat dissipation can be realized, and the heat dissipation effect is improved.
In this embodiment, the semiconductor module includes a via hole 81 sequentially penetrating through the metal layer 30, the DAF layer 20 and the lead frame 10, a conductive structure 82 is filled in the via hole 81, one end of the conductive structure 82 is electrically connected to the first conductive part 11, and the other end is electrically connected to the second conductive part 31, so that an electrode or an electrical contact on the back surface of the electronic component (e.g., the wafer 41 and the passive component 50) embedded in the substrate is led to the front surface of the semiconductor module through the first conductive part 11, the conductive structure 82 and the second conductive part 31.
In other embodiments, the via hole 81 of the semiconductor module may penetrate only the metal layer 30, may penetrate only the DAF layer 20 and the lead frame 10 in sequence, or may penetrate only the metal layer 30 and the DAF layer 20 in sequence; it is sufficient if both ends of the conductive structure 82 are electrically connected to the first conductive part 11 and the second conductive part 31, respectively, so that the electrode or the electrical contact on the back surface of the electronic component is led to the front surface of the semiconductor module.
In the present embodiment, the conductive structure 82 sequentially passes through the metal layer 30, the DAF layer 20 and the lead frame 10, which can be realized by a simpler packaging process, thereby improving the packaging efficiency.
Specifically, the adjacent first conductive parts 11 have a spacing channel therebetween, and the spacing channel is etched by photolithography or etching, and the front surface of the DAF layer 20 is exposed from the spacing channel; the adjacent second conductive portions 31 have a spacing channel therebetween, and the spacing channel is etched by photolithography or etching, and the back surface of the DAF layer 20 is exposed through the spacing channel.
Preferably, the metal layer 30 is a copper foil layer. It should be noted that the copper foil layer is not a limitation of the metal layer 30 of the present invention.
Preferably, the conductive structure 82 is a copper pillar with good conductivity. It should be noted that the copper pillar is not a limitation of the conductive structure 82 of the present invention.
Preferably, the device further comprises a solder ball 70, and the front electrode 411 is electrically connected to the second conductive part 31 through the solder ball 70. The solder balls 70 are used to electrically connect the front electrode 411 of the wafer 41 with the second conductive portion 31, so that the packaging efficiency is higher and the reliability is higher during packaging.
Preferably, the electronic device further comprises a passive component 50, wherein the back surface of the passive component 50 is bonded to the front surface of the first conductive part 11 through a conductive bonding layer 62, and the DAF layer 20 covers the front surface and the side surface of the passive component 50; the passive element 50 is electrically connected to the conductive structure 82 through the first conductive portion 11.
Preferably, the wafer 41 is a triode wafer 41, the front electrode 411 includes a source 4111 and a gate 4112, and the back electrode 412 includes a drain;
the second conductive portion 31 electrically connected to the source 4111 is a source terminal 311, the second conductive portion 31 electrically connected to the gate 4112 is a gate terminal 312, and the second conductive portion 31 electrically connected to the drain is a drain terminal 313.
Preferably, the conductive structure 82 is completely filled in the via hole 81, that is, the outer wall of the conductive structure 82 is combined with the inner wall of the via hole 81, so as to ensure both the reliability of the electrical connection and the sealing performance of both sides of the via hole 81, thereby protecting the chip 41 or the passive component 50 inside the board.
In the semiconductor module of the present invention, the number of the wafers 41 may be one, two or more, and the number of the passive elements 50 may be one, two or more.
In this embodiment, two wafers 41 and two passive elements 50 are included.
In the description herein, it is to be understood that the terms "upper", "lower", "left", "right", and the like are used in an orientation or positional relationship based on that shown in the drawings, and are used for convenience of description and simplicity of operation only, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.
Claims (10)
1. A method of packaging a semiconductor module, comprising:
the preparation method comprises the following steps: placing a lead frame (10) on a processing carrier plate (90);
a first combining step: bonding the back surface of the wafer (41) and the front surface of the lead frame (10) by using a conductive bonding material (61), and electrically connecting the back surface electrode (412) of the wafer (41) and the lead frame (10) to form a primary structure;
and (3) laminating: covering and pressing the DAF material on the front surface of the primary structure to form a DAF layer (20);
a second combining step: providing a metal layer (30) on the front surface of the DAF layer (20), and electrically connecting the metal layer (30) with a front surface electrode (411) of the wafer (41);
a perforation step: machining a via hole (81) penetrating through the DAF layer (20);
conducting: providing a conductive structure (82) within the via hole (81);
removing the plate: removing the processing carrier plate (90);
patterning step: patterning the lead frame (10) into a patterned conductive layer, the lead frame (10) including a first conductive portion (11) electrically connected to the conductive structure (82), at least one of the first conductive portions (11) being electrically connected to the back electrode (412); patterning the metal layer (30) into a patterned conductive layer, the metal layer (30) comprising second conductive portions (31), at least one of the second conductive portions (31) being electrically connected to the first conductive portion (11) via the conductive structure (82), and at least one of the second conductive portions (31) being electrically connected to the front electrode (411).
2. The method for packaging a semiconductor module according to claim 1, further comprising a ball-mounting step before the second bonding step; the ball planting step comprises: planting solder balls (70) on the front electrode (411);
correspondingly, the second combining step comprises: bonding the metal layer (30) with the solder ball (70), thereby electrically connecting the metal layer (30) with the front electrode (411).
3. The method for packaging a semiconductor module according to claim 2, wherein a wafer (40) providing step is included before the ball mounting step; the wafer (40) providing step includes: providing a wafer (40), wherein the wafer (40) comprises a plurality of chips (41);
correspondingly, the ball planting step comprises the following steps: bonding the solder balls (70) to front electrodes (411) of the die (41) on the wafer (40);
correspondingly, after the ball planting step, the method comprises a cutting step: the cutting step includes: and cutting the wafer (40) to form a plurality of chips (41).
4. The method for packaging a semiconductor module according to claim 1, wherein the first bonding step further comprises:
providing a passive element (50), bonding the back surface of the passive element (50) with the front surface of the lead frame (10) by adopting a conductive bonding material (61), and electrically connecting the electric contact of the passive element (50) with the conductive structure (82) through the first conductive part (11).
5. The method for packaging a semiconductor module according to claim 1, wherein in the punching step: processing the via hole (81) in the DAF layer (20) by a laser drilling processing technology;
in the turning-on step: filling a conductive material in the via hole (81) through a printing process or an electroplating process to form the conductive structure (82);
in the patterning step: patterning the lead frame (10) by a photolithography process or an etching process to form a plurality of first conductive parts (11); patterning the metal layer (30) by a photolithography process or an etching process to form a plurality of second conductive portions (31).
6. A semiconductor module, comprising:
a lead frame (10) which is a patterned conductive layer; the lead frame (10) comprises a first conductive part (11);
a wafer (41) having a front surface provided with a front surface electrode (411) and a back surface provided with a back surface electrode (412); the back side of the wafer (41) is bonded to the front side of the first conductive part (11) by a conductive bonding layer (62);
a DAF layer (20) covering the front surface of the lead frame (10) and the wafer (41); the DAF layer (20) is combined with the lead frame (10) to form a substrate;
a metal layer (30) which is a second patterned conductive layer; the metal layer (30) is bonded to the front surface of the substrate; the metal layer (30) comprises a second conductive part (31); the front electrode (411) is electrically connected to the second conductive part (31);
a conductive structure (82) provided within the DAF layer (20); one end of the conductive structure (82) is electrically connected with the first conductive part (11), and the conductive structure (82) is used for leading the back electrode (412) to the front surface of the semiconductor module.
7. The semiconductor module according to claim 6, comprising a via (81), said via (81) penetrating through said metal layer (30), said DAF layer (20) and said lead frame (10) in sequence; the conductive structure (82) is arranged in the via hole (81), and one end of the conductive structure (82) departing from the first conductive part (11) is electrically connected with the second conductive part (31).
8. The semiconductor module according to claim 6, further comprising a solder ball (70), wherein the front electrode (411) is electrically connected to the second conductive portion (31) through the solder ball (70).
9. The semiconductor module according to claim 6, further comprising a passive component (50), a back surface of the passive component (50) being bonded to a front surface of the first conductive portion (11) by a conductive bonding layer (62); the passive element (50) is electrically connected to the conductive structure (82) via the first conductive part (11).
10. A semiconductor module according to claim 7, characterized in that the wafer (41) is an active wafer, the front side electrode (411) comprises a source (4111) and a gate (4112), the back side electrode (412) comprises a drain;
the second conductive part (31) electrically connected with the source electrode (4111) is a source electrode leading-out terminal (311), the second conductive part (31) electrically connected with the grid electrode (4112) is a grid electrode leading-out terminal (312), and the second conductive part (31) electrically connected with the drain electrode is a drain electrode leading-out terminal (313).
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| CN114530427A (en) * | 2022-01-12 | 2022-05-24 | 广东致能科技有限公司 | Semiconductor packaging structure, preparation method thereof and electronic equipment |
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