Disclosure of Invention
The invention provides a passivation structure applied to a contact passivation battery and a preparation method thereof, aiming at solving the problem of high light absorptivity of the contact passivation layer in the TOPCO battery.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a passivation structure for contact passivation battery comprises an N-type substrate and a passivation layer arranged on the N-type substrateTwo positive electrodes on the front surface of the substrate and two negative electrodes on the back surface of the N-type substrate, wherein the back surface of the N-type substrate is provided with SiO 2 A layer of SiO 2 The doped polycrystalline SiO is arranged on the layer x N y A layer.
In a conventional Topcon battery, the forbidden bandwidth of the back polysilicon is 1.1-1.3 eV, the absorption of visible light is serious, and in order to improve the situation, the invention improves the forbidden bandwidth of the doped polycrystalline layer and uses polycrystalline SiO x N y The band gap of the layer is 5-9 eV. The doping condition of the polycrystalline layer is adjusted to enable the work function of the polycrystalline layer to be lower than that of the tunneling SiOx layer, and the tunneling effect of the polycrystalline layer is achieved on the basis of reducing the light absorption of the polycrystalline layer, so that the battery efficiency of the battery is improved.
Preferably, the front surface of the N-type substrate is sequentially provided with a P+ layer and AlO from inside to outside x Layer and SiN x A layer.
Preferably, the positive electrode passes sequentially through SiN x Layer, alO x And a layer in contact with the P+ layer.
Preferably, the back surface of the N-type substrate is sequentially provided with SiO from inside to outside 2 Layer, doped polycrystalline SiO x N y Layer and SiN x A layer.
At present, in the photovoltaic field, a doped polycrystalline silicon layer is adopted as a contact passivation layer of the battery, but the light absorption of the layer is serious, and parasitic current is large, so that the contact passivation layer is a great obstacle for realizing a high-efficiency battery. The doped polycrystalline layer in the invention has relatively less light absorption and small parasitic current, and is one way for realizing the high-efficiency battery.
Preferably, the negative electrode passes through the SiN sequentially x Layer and partial thickness doped polycrystalline SiO x N y Layer, and doped polycrystalline SiO x N y The layers are in contact.
The negative electrode must be in contact with polycrystalline SiO x N y A layer that collects current and cannot directly contact the silicon substrate below the layer; the electrode end is made of polycrystalline SiO x N y Coating the electrode with polycrystalline SiO x N y The contact area of the layers, the collection effect of the current is enhanced,thereby improving the light conversion efficiency.
The preparation method of the passivation structure applied to the doped contact passivation battery comprises the following preparation steps:
A. an N-type monocrystalline silicon wafer is adopted, and groove type double-sided texturing is adopted;
B. boron-expanding the front surface, and controlling the surface concentration to be 1E+19-2E+19/cm 3 ;
C. Removing the back BSG by acid and performing back etching, and then cleaning and reserving the front BSG layer, wherein the reflectivity after back etching is more than 32%;
D. adopting tubular oxidation to deposit a layer of SiO with the thickness of 1.4-1.6nm on the back surface of the silicon wafer 2 A layer, then SiO is deposited under a gas flow x N y The layers are doped in situ at the same time, and the doped rear resistance is about 20-40 omega/sq;
E. then carrying out front surface detour plating on the doped silicon wafer and annealing in the environment of 900-920 ℃;
F. depositing a thin layer of AlO on the front side of a silicon wafer x And double-sided SiN is performed x Coating a layer;
G. and (5) screen printing, then carrying out optical annealing and sintering test to finish the preparation of the battery piece.
Preferably, the weight reduction of the groove type double-sided texturing in the step A is 0.3-0.35g.
Preferably, the acid in step C is HF or HNO 3 The method comprises the steps of carrying out a first treatment on the surface of the The back etching weight reduction is 0.2-0.5g.
Preferably, the gas flow rate in the step D is NH 3 With SiH 4 Flow ratio or N of (2) 2 O and SiH 4 The flow ratio of (2) is 0.2-5.
In the case of a polycrystalline SiOxNy layer, NH 3 /SiH 4 、N 2 O/SiH 4 The flow ratio is within 0.2-5, when the ratio exceeds 5, the passivation effect of the polycrystalline SiOxNy layer is poor, the required annealing temperature is relatively high, if NH3, N 2 The O flow is too large, the layer is difficult to form a polycrystal form, and the contact passivation effect is poor; the NH3 and N2O flow rates are too small, namely become zero, which is equivalent to a polysilicon layer, and the light absorption is relatively serious.
Preferably, siO in step D x N y The thickness of the layer is 120-140nm.
SiO x N y The thickness of the layer is too small, the electrode is easy to burn through the layer in the silk screen section; siO (SiO) x N y The thickness of the layer is too thick, light absorption is enhanced, and parasitic current increases.
Therefore, the invention has the following beneficial effects:
(1) The polysilicon layer in the conventional Topcon battery and POLO battery has a certain amount of light absorption, which affects the further improvement of the battery efficiency, and the polysilicon layer and the metal electrode are ensured to have lower contact resistance by properly doping and annealing at proper temperature by using a wide-bandgap passivation layer, namely a silicon oxynitride layer, so that the light absorption of the passivation layer is reduced, and the aim of synergy is fulfilled;
(2) In the process of preparing the passivation structure, the usage amount of silane is reduced, the deposition quality of the polycrystalline SiOxNy layer is improved, the cost is saved, the potential safety hazard is reduced, and the preparation efficiency is improved.
Detailed Description
The invention is further described below in connection with the following detailed description.
General examples
A passivation structure applied to a contact passivation battery comprises an N-type substrate 1, two positive electrodes 2 arranged on the front surface of the N-type substrate 1, and two negative electrodes 3 arranged on the back surface of the N-type substrate 1, wherein the back surface of the N-type substrate 1 is provided with SiO 2 Layer 4, the SiO 2 Layer 4 is provided with doped polycrystalline SiO x N y Layer 5.
The front surface of the N-type substrate 1 is sequentially provided with a P+ layer 7 and AlO from inside to outside x Layer 8 and SiN x Layer 6. The positive electrode 2 sequentially passes through SiN x Layer 6, alO x Layer 8 is in contact with p+ layer 7. The back surface of the N-type substrate 1 is sequentially provided with SiO from inside to outside 2 Layer 4, doped polycrystalline SiO x N y Layer 5 and SiN x Layer 6. The negative electrode 3 sequentially passes through the SiN x Layer 6 and partial thickness of doped polycrystalline SiO x N y Layer 5, and doped polycrystalline SiO x N y The layers 5 are in contact.
The preparation method of the passivation structure applied to the contact passivation battery comprises the following preparation steps:
A. adopting an N-type monocrystalline silicon wafer, adopting groove type double-sided texturing, and reducing the weight to 0.3-0.35g;
B. boron-expanding the front surface, and controlling the surface concentration to be 1E+19-2E+19/cm 3 ;
C. Using acids (acids HF or HNO 3 ) Removing the back BSG and performing back etching, cleaning and reserving the front BSG layer, wherein the back etching weight is reduced by 0.2-0.5g, and the reflectivity after back etching is more than 32%;
D. adopting tubular oxidation to deposit a layer of SiO with the thickness of 1.4-1.6nm on the back surface of the silicon wafer 2 A layer, then SiO is deposited under a gas flow x N y The layers are doped in situ at the same time, and the doped rear resistance is about 20-40 omega/sq; the flow rate of the air flow is NH 3 With SiH 4 Flow ratio or N of (2) 2 O and SiH 4 The flow ratio of (2) is 0.2-5; siO (SiO) x N y The thickness of the layer is 120-140nm;
E. then carrying out front surface detour plating on the doped silicon wafer and annealing in the environment of 900-920 ℃;
F. depositing a thin layer of AlO on the front side of a silicon wafer x And double-sided SiN is performed x Coating a layer;
G. and (5) screen printing, then carrying out optical annealing and sintering test to finish the preparation of the battery piece.
Example 1
A passivation structure applied to a contact passivation battery comprises an N-type substrate 1, two positive electrodes 2 arranged on the front surface of the N-type substrate 1 and a passivation layer arranged on the front surface of the N-type substrate 1Two negative electrodes 3 on the back of the N-type substrate 1, wherein the back of the N-type substrate 1 is provided with SiO 2 Layer 4, the SiO 2 Layer 4 is provided with doped polycrystalline SiO x N y Layer 5.
The front surface of the N-type substrate 1 is sequentially provided with a P+ layer 7 and AlO from inside to outside x Layer 8 and SiN x Layer 6. The positive electrode 2 sequentially passes through SiN x Layer 6, alO x Layer 8 is in contact with p+ layer 7. The back surface of the N-type substrate 1 is sequentially provided with SiO from inside to outside 2 Layer 4, doped polycrystalline SiO x N y Layer 5 and SiN x Layer 6. The negative electrode 3 sequentially passes through the SiN x Layer 6 and partial thickness of doped polycrystalline SiO x N y Layer 5, and doped polycrystalline SiO x N y The layers 5 are in contact.
The preparation method of the passivation structure applied to the contact passivation battery comprises the following preparation steps:
A. an N-type monocrystalline silicon wafer is adopted, groove type double-sided texturing is adopted, and the weight reduction is 0.32g;
B. boron expansion is carried out on the front surface, and the surface concentration is controlled to be 1.5E+19/cm 3 ;
C. Removing the back BSG by adopting HF acid and performing back etching, then cleaning and reserving a front BSG layer, wherein the weight reduction of the back etching is 0.35g, and the reflectivity after the back etching is more than 32%;
D. a layer of SiO with the thickness of 1.5nm is deposited on the back surface of the silicon wafer by adopting tubular oxidation 2 A layer, then SiO is deposited under a gas flow x N y The layer is doped in situ, and the doped rear resistor is about 30 omega/sq; the flow rate of the air flow is NH 3 With SiH 4 The flow ratio of (2) is 2.5; siO (SiO) x N y The thickness of the layer was 130nm;
E. then carrying out front surface detour plating on the doped silicon wafer and annealing in the environment of 910 ℃;
F. depositing a thin layer of AlO on the front side of a silicon wafer x And double-sided SiN is performed x Coating a layer;
G. and (5) screen printing, then carrying out optical annealing and sintering test to finish the preparation of the battery piece.
Example 2
A passivation structure applied to a contact passivation battery comprises an N-type substrate 1, two positive electrodes 2 arranged on the front surface of the N-type substrate 1, and two negative electrodes 3 arranged on the back surface of the N-type substrate 1, wherein the back surface of the N-type substrate 1 is provided with SiO 2 Layer 4, the SiO 2 Layer 4 is provided with doped polycrystalline SiO x N y Layer 5.
The front surface of the N-type substrate 1 is sequentially provided with a P+ layer 7 and AlO from inside to outside x Layer 8 and SiN x Layer 6. The positive electrode 2 sequentially passes through SiN x Layer 6, alO x Layer 8 is in contact with p+ layer 7. The back surface of the N-type substrate 1 is sequentially provided with SiO from inside to outside 2 Layer 4, doped polycrystalline SiO x N y Layer 5 and SiN x Layer 6. The negative electrode 3 sequentially passes through the SiN x Layer 6 and partial thickness of doped polycrystalline SiO x N y Layer 5, and doped polycrystalline SiO x N y The layers 5 are in contact.
The preparation method of the passivation structure applied to the contact passivation battery comprises the following preparation steps:
A. an N-type monocrystalline silicon wafer is adopted, groove type double-sided texturing is adopted, and the weight reduction is 0.3g;
B. boron-expanding the front surface, and controlling the surface concentration to be 1E+19/cm 3 ;
C. By HNO 3 Removing the back BSG and performing back etching, cleaning and reserving the front BSG layer, wherein the back etching weight is reduced to 0.2g, and the reflectivity after back etching is more than 32%;
D. a layer of SiO with the thickness of 1.4nm is deposited on the back surface of the silicon wafer by adopting tubular oxidation 2 A layer, then SiO is deposited under a gas flow x N y The layer is doped in situ, and the doped rear resistor is about 20 omega/sq; the N is 2 O and SiH 4 The flow ratio of (2) is 0.2; siO (SiO) x N y The thickness of the layer was 120nm;
E. then carrying out front surface detour plating on the doped silicon wafer and annealing in the environment of 900 ℃;
F. depositing a thin layer of AlO on the front side of a silicon wafer x And double-sided SiN is performed x Coating a layer;
G. and (5) screen printing, then carrying out optical annealing and sintering test to finish the preparation of the battery piece.
Example 3
A passivation structure applied to a contact passivation battery comprises an N-type substrate 1, two positive electrodes 2 arranged on the front surface of the N-type substrate 1, and two negative electrodes 3 arranged on the back surface of the N-type substrate 1, wherein the back surface of the N-type substrate 1 is provided with SiO 2 Layer 4, the SiO 2 Layer 4 is provided with doped polycrystalline SiO x N y Layer 5.
The front surface of the N-type substrate 1 is sequentially provided with a P+ layer 7 and AlO from inside to outside x Layer 8 and SiN x Layer 6. The positive electrode 2 sequentially passes through SiN x Layer 6, alO x Layer 8 is in contact with p+ layer 7. The back surface of the N-type substrate 1 is sequentially provided with SiO from inside to outside 2 Layer 4, doped polycrystalline SiO x N y Layer 5 and SiN x Layer 6. The negative electrode 3 sequentially passes through the SiN x Layer 6 and partial thickness of doped polycrystalline SiO x N y Layer 5, and doped polycrystalline SiO x N y The layers 5 are in contact.
The preparation method of the passivation structure applied to the contact passivation battery comprises the following preparation steps:
A. an N-type monocrystalline silicon wafer is adopted, groove type double-sided texturing is adopted, and the weight reduction is 0.35g;
B. boron expansion is carried out on the front surface, and the surface concentration is controlled to be 2E+19/cm 3 ;
C. Using acid as HF or HNO 3 Removing the back BSG and performing back etching, cleaning and reserving the front BSG layer, wherein the back etching weight is reduced to 0.5g, and the reflectivity after back etching is more than 32%;
D. a layer of SiO with the thickness of 1.6nm is deposited on the back surface of the silicon wafer by adopting tubular oxidation 2 A layer, then SiO is deposited under a gas flow x N y The layer is doped in situ at the same time, and the doped rear resistor is about 40 omega/sq; the flow rate of the air flow is NH 3 With SiH 4 The flow ratio of (2) is 5; siO (SiO) x N y The thickness of the layer was 140nm;
E. then carrying out front surface detour plating on the doped silicon wafer and annealing in the environment of 920 ℃;
F. depositing a thin layer of AlO on the front side of a silicon wafer x And double-sided SiN is performed x Coating a layer;
G. and (5) screen printing, then carrying out optical annealing and sintering test to finish the preparation of the battery piece.
Example 4
A passivation structure applied to a contact passivation battery comprises an N-type substrate 1, two positive electrodes 2 arranged on the front surface of the N-type substrate 1, and two negative electrodes 3 arranged on the back surface of the N-type substrate 1, wherein the back surface of the N-type substrate 1 is provided with SiO 2 Layer 4, the SiO 2 Layer 4 is provided with doped polycrystalline SiO x N y Layer 5.
The front surface of the N-type substrate 1 is sequentially provided with a P+ layer 7 and AlO from inside to outside x Layer 8 and SiN x Layer 6. The positive electrode 2 sequentially passes through SiN x Layer 6, alO x Layer 8 is in contact with p+ layer 7. The back surface of the N-type substrate 1 is sequentially provided with SiO from inside to outside 2 Layer 4, doped polycrystalline SiO x N y Layer 5 and SiN x Layer 6. The negative electrode 3 sequentially passes through the SiN x Layer 6 and partial thickness of doped polycrystalline SiO x N y Layer 5, and doped polycrystalline SiO x N y The layers 5 are in contact.
The preparation method of the passivation structure applied to the contact passivation battery comprises the following preparation steps:
A. an N-type monocrystalline silicon wafer is adopted, groove type double-sided texturing is adopted, and the weight reduction is 0.31g;
B. boron expansion is carried out on the front surface, and the surface concentration is controlled to be 1.2E+19/cm 3 ;
C. Removing the back BSG by adopting HF and performing back etching, then cleaning and reserving a front BSG layer, wherein the weight reduction of the back etching is 0.3g, and the reflectivity after the back etching is more than 32%;
D. a layer of SiO with the thickness of 1.45nm is deposited on the back surface of the silicon wafer by adopting tubular oxidation 2 A layer, then SiO is deposited under a gas flow x N y The layer is doped in situ, and the doped rear resistor is about 35 omega/sq; the N is 2 O and SiH 4 The flow ratio of (2) is 0.5; siO (SiO) x N y The thickness of the layer was 125nm;
E. then carrying out front surface detour plating on the doped silicon wafer and annealing in the environment of 905 ℃;
F. depositing a thin layer of AlO on the front side of a silicon wafer x And double-sided SiN is performed x Coating a layer;
G. and (5) screen printing, then carrying out optical annealing and sintering test to finish the preparation of the battery piece.
Example 5
A passivation structure applied to a contact passivation battery comprises an N-type substrate 1, two positive electrodes 2 arranged on the front surface of the N-type substrate 1, and two negative electrodes 3 arranged on the back surface of the N-type substrate 1, wherein the back surface of the N-type substrate 1 is provided with SiO 2 Layer 4, the SiO 2 Layer 4 is provided with doped polycrystalline SiO x N y Layer 5.
The front surface of the N-type substrate 1 is sequentially provided with a P+ layer 7 and AlO from inside to outside x Layer 8 and SiN x Layer 6. The positive electrode 2 sequentially passes through SiN x Layer 6, alO x Layer 8 is in contact with p+ layer 7. The back surface of the N-type substrate 1 is sequentially provided with SiO from inside to outside 2 Layer 4, doped polycrystalline SiO x N y Layer 5 and SiN x Layer 6. The negative electrode 3 sequentially passes through the SiN x Layer 6 and partial thickness of doped polycrystalline SiO x N y Layer 5, and doped polycrystalline SiO x N y The layers 5 are in contact.
The preparation method of the passivation structure applied to the contact passivation battery comprises the following preparation steps:
A. an N-type monocrystalline silicon wafer is adopted, groove type double-sided texturing is adopted, and the weight reduction is 0.34g;
B. boron expansion is carried out on the front surface, and the surface concentration is controlled to be 1.8E+19/cm 3 ;
C. Using acid as HF or HNO 3 Removing the back BSG and performing back etching, cleaning and reserving the front BSG layer, wherein the back etching weight is reduced to 0.4g, and the reflectivity after back etching is more than 32%;
D. by tubular oxidationDepositing a layer of SiO with the thickness of 1.55nm on the back surface of the silicon wafer 2 A layer, then SiO is deposited under a gas flow x N y The layer is doped in situ, and the doped rear resistor is about 35 omega/sq; the flow rate of the air flow is NH 3 With SiH 4 The flow ratio of (2) is 4.5; siO (SiO) x N y The thickness of the layer was 135nm;
E. then carrying out front surface detour plating on the doped silicon wafer and annealing in the environment of 915 ℃;
F. depositing a thin layer of AlO on the front side of a silicon wafer x And double-sided SiN is performed x Coating a layer;
G. and (5) screen printing, then carrying out optical annealing and sintering test to finish the preparation of the battery piece.
Comparative example 1 (differing from example 1 in that the doped polycrystalline SiO was prepared x N y The layer is replaced by a polysilicon layer. ) A passivation structure applied to a contact passivation battery comprises an N-type substrate 1, two positive electrodes 2 arranged on the front surface of the N-type substrate 1, and two negative electrodes 3 arranged on the back surface of the N-type substrate 1, wherein the back surface of the N-type substrate 1 is provided with SiO 2 Layer 4, the SiO 2 A polysilicon layer 5 is provided on layer 4.
The front surface of the N-type substrate 1 is sequentially provided with a P+ layer 7 and AlO from inside to outside x Layer 8 and SiN x Layer 6. The positive electrode 2 sequentially passes through SiN x Layer 6, alO x Layer 8 is in contact with p+ layer 7. The back surface of the N-type substrate 1 is sequentially provided with SiO from inside to outside 2 Layer 4, doped polycrystalline SiO x N y Layer 5 and SiN x Layer 6. The negative electrode 3 sequentially passes through the SiN x Layer 6 is in contact with a portion of the thickness of polysilicon layer 5, and with polysilicon layer 5.
The preparation method of the passivation structure applied to the contact passivation battery comprises the following preparation steps:
A. an N-type monocrystalline silicon wafer is adopted, groove type double-sided texturing is adopted, and the weight reduction is 0.32g;
B. boron expansion is carried out on the front surface, and the surface concentration is controlled to be 1.5E+19/cm 3 ;
C. Removing the back BSG by adopting HF acid and performing back etching, then cleaning and reserving a front BSG layer, wherein the weight reduction of the back etching is 0.35g, and the reflectivity after the back etching is more than 32%;
D. a layer of SiO with the thickness of 1.5nm is deposited on the back surface of the silicon wafer by adopting tubular oxidation 2 The layer, then deposit the polycrystalline silicon layer under the airstream, carry on the in situ doping at the same time, the doped rear block is about 30 omega/sq; the flow rate of the air flow is NH 3 With SiH 4 The flow ratio of (2) is 2.5; siO (SiO) x N y The thickness of the layer was 130nm;
E. then carrying out front surface detour plating on the doped silicon wafer and annealing in the environment of 910 ℃;
F. depositing a thin layer of AlO on the front side of a silicon wafer x And double-sided SiN is performed x Coating a layer;
G. and (5) screen printing, then carrying out optical annealing and sintering test to finish the preparation of the battery piece.
Comparative example 2 (differing from example 1 in that the gas flow rate in step D was NH 3 With SiH 4 The flow ratio of (2) was 7.5. )
A passivation structure applied to a contact passivation battery comprises an N-type substrate 1, two positive electrodes 2 arranged on the front surface of the N-type substrate 1, and two negative electrodes 3 arranged on the back surface of the N-type substrate 1, wherein the back surface of the N-type substrate 1 is provided with SiO 2 Layer 4, the SiO 2 Layer 4 is provided with doped polycrystalline SiO x N y Layer 5.
The front surface of the N-type substrate 1 is sequentially provided with a P+ layer 7 and AlO from inside to outside x Layer 8 and SiN x Layer 6. The positive electrode 2 sequentially passes through SiN x Layer 6, alO x Layer 8 is in contact with p+ layer 7. The back surface of the N-type substrate 1 is sequentially provided with SiO from inside to outside 2 Layer 4, doped polycrystalline SiO x N y Layer 5 and SiN x Layer 6. The negative electrode 3 sequentially passes through the SiN x Layer 6 and partial thickness of doped polycrystalline SiO x N y Layer 5, and doped polycrystalline SiO x N y The layers 5 are in contact.
The preparation method of the passivation structure applied to the contact passivation battery comprises the following preparation steps:
A. an N-type monocrystalline silicon wafer is adopted, groove type double-sided texturing is adopted, and the weight reduction is 0.32g;
B. boron expansion is carried out on the front surface, and the surface concentration is controlled to be 1.5E+19/cm 3 ;
C. Removing the back BSG by adopting HF acid and performing back etching, then cleaning and reserving a front BSG layer, wherein the weight reduction of the back etching is 0.35g, and the reflectivity after the back etching is more than 32%;
D. a layer of SiO with the thickness of 1.5nm is deposited on the back surface of the silicon wafer by adopting tubular oxidation 2 A layer, then SiO is deposited under a gas flow x N y The layer is doped in situ, and the doped rear resistor is about 30 omega/sq; the flow rate of the air flow is NH 3 With SiH 4 The flow ratio of (2) is 7.5; siO (SiO) x N y The thickness of the layer was 130nm;
E. then carrying out front surface detour plating on the doped silicon wafer and annealing in the environment of 910 ℃;
F. depositing a thin layer of AlO on the front side of a silicon wafer x And double-sided SiN is performed x Coating a layer;
G. and (5) screen printing, then carrying out optical annealing and sintering test to finish the preparation of the battery piece.
Comparative example 3 (differing from example 1 in that the thickness of the SiOxNy layer is 170 nm.)
A passivation structure applied to a contact passivation battery comprises an N-type substrate 1, two positive electrodes 2 arranged on the front surface of the N-type substrate 1, and two negative electrodes 3 arranged on the back surface of the N-type substrate 1, wherein the back surface of the N-type substrate 1 is provided with SiO 2 Layer 4, the SiO 2 Layer 4 is provided with doped polycrystalline SiO x N y Layer 5.
The front surface of the N-type substrate 1 is sequentially provided with a P+ layer 7 and AlO from inside to outside x Layer 8 and SiN x Layer 6. The positive electrode 2 sequentially passes through SiN x Layer 6, alO x Layer 8 is in contact with p+ layer 7. The back surface of the N-type substrate 1 is sequentially provided with SiO from inside to outside 2 Layer 4, doped polycrystalline SiO x N y Layer 5 and SiN x Layer 6. The negative electrode 3 sequentially passes through the SiN x Layer 6 and partial thickness of doped polycrystalline SiO x N y Layer 5, anddoping polycrystalline SiO x N y The layers 5 are in contact.
The preparation method of the passivation structure applied to the contact passivation battery comprises the following preparation steps:
A. an N-type monocrystalline silicon wafer is adopted, groove type double-sided texturing is adopted, and the weight reduction is 0.32g;
B. boron expansion is carried out on the front surface, and the surface concentration is controlled to be 1.5E+19/cm 3 ;
C. Removing the back BSG by adopting HF acid and performing back etching, then cleaning and reserving a front BSG layer, wherein the weight reduction of the back etching is 0.35g, and the reflectivity after the back etching is more than 32%;
D. a layer of SiO with the thickness of 1.5nm is deposited on the back surface of the silicon wafer by adopting tubular oxidation 2 A layer, then SiO is deposited under a gas flow x N y The layer is doped in situ, and the doped rear resistor is about 30 omega/sq; the flow rate of the air flow is NH 3 With SiH 4 The flow ratio of (2) is 2.5; siO (SiO) x N y The thickness of the layer was 170nm;
E. then carrying out front surface detour plating on the doped silicon wafer and annealing in the environment of 910 ℃;
F. depositing a thin layer of AlO on the front side of a silicon wafer x And double-sided SiN is performed x Coating a layer;
G. and (5) screen printing, then carrying out optical annealing and sintering test to finish the preparation of the battery piece.
Comparative example 4 (differing from example 1 in that the negative electrode was doped with polycrystalline SiO x N y The layer surfaces are in contact. ) A passivation structure applied to a contact passivation battery comprises an N-type substrate 1, two positive electrodes 2 arranged on the front surface of the N-type substrate 1, and two negative electrodes 3 arranged on the back surface of the N-type substrate 1, wherein the back surface of the N-type substrate 1 is provided with SiO 2 Layer 4, the SiO 2 Layer 4 is provided with doped polycrystalline SiO x N y Layer 5.
The front surface of the N-type substrate 1 is sequentially provided with a P+ layer 7 and AlO from inside to outside x Layer 8 and SiN x Layer 6. The positive electrode 2 sequentially passes through SiN x Layer 6, alO x Layer 8 is in contact with p+ layer 7. The N-type linerThe back surface of the bottom 1 is sequentially provided with SiO from inside to outside 2 Layer 4, doped polycrystalline SiO x N y Layer 5 and SiN x Layer 6. The negative electrode 3 sequentially passes through the SiN x Layer 6 and doped polycrystalline SiO x N y The surfaces of the layers 5 are in contact.
The preparation method of the passivation structure applied to the contact passivation battery comprises the following preparation steps:
A. an N-type monocrystalline silicon wafer is adopted, groove type double-sided texturing is adopted, and the weight reduction is 0.32g;
B. boron expansion is carried out on the front surface, and the surface concentration is controlled to be 1.5E+19/cm 3 ;
C. Removing the back BSG by adopting HF acid and performing back etching, then cleaning and reserving a front BSG layer, wherein the weight reduction of the back etching is 0.35g, and the reflectivity after the back etching is more than 32%;
D. a layer of SiO with the thickness of 1.5nm is deposited on the back surface of the silicon wafer by adopting tubular oxidation 2 A layer, then SiO is deposited under a gas flow x N y The layer is doped in situ, and the doped rear resistor is about 30 omega/sq; the flow rate of the air flow is NH 3 With SiH 4 The flow ratio of (2) is 2.5; siO (SiO) x N y The thickness of the layer was 130nm;
E. then carrying out front surface detour plating on the doped silicon wafer and annealing in the environment of 910 ℃;
F. depositing a thin layer of AlO on the front side of a silicon wafer x And double-sided SiN is performed x Coating a layer;
G. and (5) screen printing, then carrying out optical annealing and sintering test to finish the preparation of the battery piece.
Table 1 items and passivation Structure of contact passivation cell
Conclusion analysis: the results of examples 1-5 show that only the passivation structure of the contact passivation battery prepared by the structure of the invention has higher battery efficiency and current density, higher sunlight conversion efficiency and greatly reduced breakage rate of sunlight.
Comparative example 1 differs from example 1 in that the doped polycrystalline SiO was prepared x N y The layer is replaced by a polysilicon layer;
comparative example 2 differs from example 1 in that the gas flow rate in step D is NH 3 With SiH 4 The flow ratio of (2) is 7.5; if the ratio exceeds 5, the passivation effect of the polycrystalline SiOxNy layer becomes poor, the annealing temperature required becomes relatively high, and if NH 3 、N 2 The O flow is too large, the layer is difficult to form a polycrystal form, so that the contact passivation effect is poor, and the related performance is reduced.
Comparative example 3 differs from example 1 in that SiO x N y The thickness of the layer was 170nm; when the thickness is too large, light absorption is enhanced, parasitic current is increased, and the corresponding performance is reduced compared with that of example 1.
Comparative example 4 differs from example 1 in that the negative electrode was doped with polycrystalline SiO x N y The surfaces of the layers are contacted; the contact area thereof becomes smaller, the current collecting ability becomes worse, and the corresponding performance is lowered as compared with example 1.
From the data of examples 1 to 5 and comparative examples 1 to 4, it is understood that the above requirements can be satisfied in all aspects only by the schemes within the scope of the claims of the present invention, and an optimized scheme can be obtained, resulting in a highly efficient passivation structure battery with optimal performance. And the replacement/addition of each deposition layer or the change of the preparation sequence can bring about corresponding negative effects.
The raw materials and equipment used in the invention are common raw materials and equipment in the field unless specified otherwise; the methods used in the present invention are conventional in the art unless otherwise specified.
The foregoing description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and any simple modification, variation and equivalent transformation of the above embodiment according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.