CN109065639A

CN109065639A - N-type crystalline silicon solar battery and preparation method, photovoltaic module

Info

Publication number: CN109065639A
Application number: CN201810649226.2A
Authority: CN
Inventors: 陈孝业; 薛文娟; 尹海鹏
Original assignee: JA Solar Technology Yangzhou Co Ltd
Current assignee: JA Solar Technology Yangzhou Co Ltd
Priority date: 2018-06-22
Filing date: 2018-06-22
Publication date: 2018-12-21

Abstract

The invention discloses a kind of N-type crystalline silicon solar battery and preparation methods, photovoltaic module, belong to technical field of solar batteries.The N-type crystalline silicon solar battery includes the front electrode set gradually, front passivation layer, emitter, N-type crystalline silicon matrix, backside passivation layer and rear electrode, wherein the front passivation layer includes the gallium oxide layer directly contacted with the emitter.In the solar battery, the negative electrical charge being had using gallium oxide layer carries out chemical passivation to the P-type silicon surface of the emitter of N-type crystalline silicon solar battery and field is passivated, reduce the minority carrier recombination rate at P-type silicon surface, and the photogenerated current density of battery is improved to the absorption of incident ray using the reduction of gallium oxide layer, to improve the voltage and electric current of solar battery, promote the photoelectric conversion efficiency of solar battery, and then improve the output power of photovoltaic module, reduction degree electricity cost, improves the cost performance of photovoltaic power generation.

Description

N-type crystalline silicon solar cell, preparation method and photovoltaic module

Technical Field

The invention relates to the technical field of solar cells, in particular to an N-type crystalline silicon solar cell, a preparation method and a photovoltaic module.

Background

Photovoltaic power generation, namely, directly converting solar energy into electric energy, is a clean power generation mode with relatively high sustainability and cost performance. The crystalline silicon solar cell is an important component of a photovoltaic power generation system, and the photoelectric conversion efficiency of the crystalline silicon solar cell has important influence on the output power and the electricity consumption cost of photovoltaic power generation.

The crystalline silicon solar cells can be classified into P-type crystalline silicon solar cells and N-type crystalline silicon solar cells according to the type of a central crystalline silicon substrate in the crystalline silicon solar cells. The N-type crystalline silicon solar cell mainly comprises a front electrode, a front passivation layer, an emitting electrode, an N-type crystalline silicon substrate, a back passivation layer and a back electrode which are sequentially arranged, wherein the front passivation layer is usually made of silicon oxide, silicon carbide, silicon nitride, silicon oxynitride and the like.

The existing N-type crystalline silicon solar cell has high minority carrier recombination rate, and the photoelectric conversion efficiency of the solar cell is limited.

Disclosure of Invention

The embodiment of the invention provides an N-type crystalline silicon solar cell, a preparation method and a photovoltaic module, which are used for solving the problem that the minority carrier recombination rate in the existing N-type crystalline silicon solar cell is high.

Specifically, the method comprises the following technical scheme:

in a first aspect, an embodiment of the present invention provides an N-type crystalline silicon solar cell, including a front electrode, a front passivation layer, an emitter, an N-type crystalline silicon substrate, a back passivation layer, and a back electrode, which are sequentially disposed, where the front passivation layer includes a gallium oxide layer directly contacting the emitter.

Optionally, the thickness of the gallium oxide layer is 1 nm to 120 nm.

Optionally, the thickness of the gallium oxide layer is 10 nm to 60 nm.

Optionally, the thickness of the gallium oxide layer is 20 nm to 40 nm.

Optionally, the front passivation layer further includes a covering layer disposed on the gallium oxide layer, the covering layer includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer, and the thickness of the covering layer is 10 nm to 120 nm.

Optionally, the solar cell further comprises: the N-type doping layer is arranged on the back surface of the N-type crystal silicon substrate; the back passivation layer is arranged on the N-type doping layer, and the back electrode penetrates through the back passivation layer to form ohmic contact with the N-type doping layer; the back passivation layer comprises at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer and a silicon carbide layer, and the thickness of the back passivation layer is 30-200 nanometers.

Optionally, the solar cell further comprises: the tunneling oxide layer is arranged on the back surface of the N-type crystal silicon substrate, and the doped silicon layer is arranged on the tunneling oxide layer; the doping source of the doped silicon layer is a V-group element;

the back passivation layer is arranged on the doped silicon layer, and the back electrode penetrates through the back passivation layer to form ohmic contact with the doped silicon layer;

the back passivation layer comprises at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer and a silicon carbide layer;

the thickness of the tunneling oxide layer is 0.5-6 nanometers, the thickness of the doped silicon layer is 10-1000 nanometers, and the thickness of the back passivation layer is 60-120 nanometers.

Optionally, the doped silicon layer is a doped amorphous silicon layer or a doped polysilicon layer;

optionally, in the doped silicon layer, the sheet resistance of the doped silicon is 10 Ω/□ -1000 Ω/□.

In a second aspect, an embodiment of the present invention provides a method for manufacturing an N-type crystalline silicon solar cell, including:

providing an N-type crystalline silicon substrate;

forming an emitter on the front surface of the N-type crystal silicon substrate;

and forming a gallium oxide layer directly contacted with the emitter on the emitter.

Optionally, the gallium oxide layer is formed by a monoatomic layer deposition method, a plasma enhanced chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, or a low pressure chemical vapor deposition method.

Optionally, between the forming of the emitter on the front surface of the N-type crystalline silicon substrate and the forming of the gallium oxide layer on the emitter, the preparation method further includes:

flattening the back surface of the N-type crystal silicon substrate;

doping the back of the N-type crystal silicon substrate to form an N-type doping layer;

optionally, after forming the gallium oxide layer directly contacting with the emitter on the emitter, the preparation method further includes:

forming a covering layer on the gallium oxide layer, and forming a back passivation layer on the N-type doped layer;

and printing the back electrode and the front electrode, and sintering.

flattening the back surface of the N-type crystal silicon substrate;

growing a tunneling oxide layer on the back surface of the N-type crystal silicon substrate;

forming a doped silicon layer on the tunneling oxide layer;

forming a covering layer on the gallium oxide layer, and forming a back passivation layer on the doped silicon layer;

and printing the back electrode and the front electrode, and sintering.

In a third aspect, an embodiment of the present invention provides a photovoltaic module, which includes a cover plate, a first packaging adhesive film, a battery string, a second packaging adhesive film, and a back plate, which are sequentially disposed, where the battery string includes a plurality of solar cells, and the solar cells are the above-mentioned N-type crystalline silicon solar cells.

Optionally, the first packaging adhesive film and the second packaging adhesive film are made of EVA.

Optionally, the backing sheet is glass or a TPT sheet.

The technical scheme provided by the embodiment of the invention has the beneficial effects that:

in the embodiment of the invention, the gallium oxide layer which is directly contacted with the emitter is arranged on the emitter, on one hand, the emitter in the N-type crystalline silicon solar cell is P-type silicon, negative charges carried by the gallium oxide layer can carry out chemical passivation and field passivation on the surface of the P-type silicon, and the number of dangling bonds and minority carriers of silicon atoms on the surface of the P-type silicon is reduced, so that the recombination rate of the minority carriers on the surface of the P-type silicon is reduced, the voltage and the current of the solar cell are improved, on the other hand, the gallium oxide layer has wider forbidden bandwidth and proper optical refraction coefficient, and the absorption of incident light can be reduced, so that the photo-generated current density of the cell is; the effects of the two aspects are integrated, the photoelectric conversion efficiency of the N-type crystalline silicon solar cell is improved, the output power of the photovoltaic module is further improved, the power consumption cost is reduced, and the cost performance of photovoltaic power generation is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below.

Fig. 1 is a schematic diagram of a setting mode of a gallium oxide layer in an N-type crystalline silicon solar cell according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an N-type crystalline silicon bifacial solar cell provided by an embodiment of the invention;

fig. 3 is a schematic structural diagram of a tunnel oxidation passivation contact solar cell according to an embodiment of the present invention.

The reference numerals in the drawings denote:

a 1N-type crystalline silicon substrate;

2a front passivation layer;

21 a gallium oxide layer;

22 a cover layer;

3, an emitter;

a 41N type doped layer;

42 tunneling through the oxide layer;

43 a doped silicon layer;

5a back passivation layer;

6a front electrode;

7a back electrode;

thickness of the T1 gallium oxide layer;

thickness of T2 blanket;

thickness of the T3 back passivation layer;

t4 tunnel thickness of oxide layer;

t5 thickness of doped silicon layer.

Detailed Description

In order to make the technical solutions and advantages of the present invention clearer, the following will describe embodiments of the present invention in further detail with reference to the accompanying drawings. Unless defined otherwise, all technical terms used in the examples of the present invention have the same meaning as commonly understood by one of ordinary skill in the art.

The improvement of the photoelectric conversion efficiency of the crystalline silicon solar cell is an effective way for improving the output power of photovoltaic power generation and reducing the power consumption cost. At present, one of the important factors limiting the photoelectric conversion efficiency of a single crystalline silicon solar cell is the recombination annihilation of minority carriers in the solar cell. The recombination annihilation of minority carriers causes the loss of the voltage and current of the solar cell, thereby reducing the photoelectric conversion efficiency of the cell. A large number of unsaturated dangling bonds exist on the surface of crystalline silicon, and are serious recombination centers. The passivation layer is arranged on the surface of the silicon wafer to passivate the surface of the silicon wafer, so that the recombination probability of minority carriers on the surface of the silicon wafer can be reduced, and the photoelectric conversion efficiency of the solar cell can be improved.

Based on the above, the embodiment of the invention provides an N-type crystalline silicon solar cell, a preparation method thereof and a photovoltaic module based on the N-type crystalline silicon solar cell.

Referring to fig. 1 in combination with fig. 2 and 3, the N-type crystalline silicon solar cell includes a front surface electrode 6, a front surface passivation layer 2, an emitter electrode 3, an N-type crystalline silicon substrate 1, a back surface passivation layer 5, and a back surface electrode 7, which are sequentially disposed, wherein the front surface passivation layer 2 includes gallium oxide (GaO) directly contacting the emitter electrode 3_x) Layer 21.

For an N-type crystalline silicon solar cell, the emitter 3 is P-type silicon, negative charges carried by the gallium oxide layer 21 can perform chemical passivation and field passivation on the surface of the P-type silicon, and the number of dangling bonds and minority carriers of silicon atoms on the surface of the P-type silicon is reduced, so that the recombination rate of the minority carriers on the surface of the P-type silicon is reduced, and the voltage and the current of the solar cell are further improved.

Meanwhile, the gallium oxide layer 21 has a wider forbidden band width and a proper optical refractive index, and is arranged on the front surface of the solar cell, so that the absorption of incident light can be reduced, and the photo-generated current density of the cell can be improved.

By integrating the effects of the gallium oxide layer 21 and the above two aspects, the photoelectric conversion efficiency of the N-type crystalline silicon solar cell is improved, so that the output power of the photovoltaic module is improved, the power consumption cost is reduced, and the cost performance of photovoltaic power generation is improved.

Further, in the embodiment of the present invention, the thickness of the gallium oxide layer 21 (i.e., the dimension indicated by T1 in fig. 1) may be 1 nm to 120 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, and the like. Preferably, the thickness of the gallium oxide layer 21 may be 10 nm to 60 nm; more preferably, the thickness of the gallium oxide layer 21 may be 20 nm to 40 nm.

Further, as shown in fig. 1, in the embodiment of the present invention, the front passivation layer 2 may further include a capping layer 22 disposed on the gallium oxide layer 21. The capping layer 22 may comprise silicon nitride (SiN)_x) Layer, silicon oxynitride (SiO)_xN_y) Layer, silicon oxide (SiO)_x) Layer and silicon carbide (SiC)_x) At least one of the layers may be a separate silicon nitride layer, a separate silicon oxynitride layer, a separate silicon oxide layer, orThe single silicon carbide layer may be formed by stacking two or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer. The thickness of the entire cover layer 22 (i.e., the thickness indicated by T2 in fig. 1) is 10 nm to 120 nm, for example, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, or the like. It will be appreciated that the provision of the cover layer 22 serves to reduce reflection. When the cover layer 22 is of a laminate structure, the thickness of each layer is not critical and may be set as desired (e.g., refractive index requirement) as long as the overall thickness satisfies the requirement.

In the embodiment of the invention, the structures of the back passivation layer 5 and the back electrode 7 of the N-type crystalline silicon solar cell can be set according to the specific type of the cell. The following description will be made by taking an N-type crystalline silicon bifacial solar cell and a tunnel oxide passivation contact (Topcon) solar cell as examples.

N-type crystalline silicon double-sided solar cell

As shown in fig. 2, for the N-type crystalline silicon bifacial solar cell, the cell structure further comprises an N-type doped layer 41 disposed on the back surface of the N-type crystalline silicon substrate 1. A back passivation layer 5 is disposed on the N-type doped layer 41, and a back electrode 7 forms an ohmic contact with the N-type doped layer 41 through the back passivation layer 5. It can be understood that in the N-type crystalline silicon double-sided solar cell, the back electrode 7 is the same as the front electrode 6, and a grid line structure including a main grid line and a secondary grid line is adopted.

The back passivation layer 5 includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer, that is, the back passivation layer 5 may be a single silicon nitride layer, a single silicon oxynitride layer, a single silicon oxide layer, and a single silicon carbide layer, or may be two or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer stacked on top of each other. In the N-type crystalline silicon bifacial solar cell, the thickness of the back passivation layer as a whole (i.e., the dimension indicated by T3 in fig. 1) may be 30 nm to 200 nm, such as 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, and 135 nm. When the back passivation layer 5 has a stacked structure, the thickness of each layer is not strictly required, and may be set as needed as long as the overall thickness satisfies the requirements.

The N-type doped layer 41 may be a group V element doped layer (e.g., a phosphorus doped layer), and the sheet resistance after doping may be 20 Ω/□ -500 Ω/□, such as 20 Ω/□, 30 Ω/□, 40 Ω/□, 50 Ω/□, 60 Ω/□, 70 Ω/□, 80 Ω/□, 90 Ω/□, 100 Ω/□, 150 Ω/□, 200 Ω/□, 250 Ω/□, 300 Ω/□, 350 Ω/□, 400 Ω/□, 450 Ω/□, 500 Ω/□, and the like.

(II) Topcon solar cell

As shown in fig. 3, for the Topcon solar cell, the cell structure further includes a tunnel oxide layer 42 (which may be substantially a silicon oxide layer) disposed on the back surface of the N-type crystalline silicon substrate 1, and a doped silicon layer 43 disposed on the tunnel oxide layer 42. A back passivation layer 5 is disposed on the doped silicon layer 43, and a back electrode 7 forms an ohmic contact with the doped silicon layer 43 through the back passivation layer 5.

In the Topcon solar cell, the back electrode 7 may be in the form of a conventional electrode with silver as a main electrode and a region other than the main electrode covered with metallic silver; the same grid line structure as the front electrode 6 can also be adopted, thereby realizing double-sided power generation.

The back passivation layer 5 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer, that is, a single silicon nitride layer, a single silicon oxynitride layer, a single silicon oxide layer, or a single silicon carbide layer, or two or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a silicon carbide layer may be stacked,

in a Topcon solar cell, the thickness of the back passivation layer 5 may be 60 nm to 120 nm (e.g., 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, etc.). When the back passivation layer 5 is a stacked structure, the thickness of each layer is not strictly limited and may be set as needed as long as the overall thickness satisfies the requirements.

Meanwhile, the thickness of the tunneling oxide layer 42 (i.e., the size indicated by T4 in fig. 3) may be 0.5 nm to 6 nm (e.g., 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, etc.), the thickness of the doped silicon layer 43 (i.e., the size indicated by T5 in fig. 3) may be 10 nm to 1000 nm (e.g., 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, etc.),

in a Topcon solar cell, the doped silicon layer 43 may be specifically a doped polysilicon layer or a doped amorphous silicon layer, or a mixed layer of polysilicon and amorphous silicon. The dopant source of the doped silicon layer 43 may be a group V element such as nitrogen, phosphorus, arsenic, antimony, bismuth. The sheet resistance of the doped silicon can be 10 omega/□ -1000 omega/□, such as 10 omega/□, 20 omega/□, 30 omega/□, 40 omega/□, 50 omega/□, 60 omega/□, 70 omega/□, 80 omega/□, 90 omega/□, 100 omega/□, 150 omega/□, 200 omega/□, 250 omega/□, 300 omega/□, 350 omega/□, 400 omega/□, 450 omega/□, 500 omega/□, 550 omega/□, 600 omega/□, 650 omega/□, 700 omega/□, 750 omega/□, 800 omega/□, 850 omega/□, 900 omega/□, 950/□, 1000 omega/□ and the like.

In the present embodiment, the N-type crystalline silicon substrate 1 may be single-crystal silicon or polycrystalline silicon, and the resistivity may be 0.1 Ω · cm to 10 Ω · cm (for example, 0.1 Ω · cm, 0.2 Ω · cm, 0.3 Ω · cm, 0.4 Ω · cm, 0.5 Ω · cm, 0.6 Ω · cm, 0.7 Ω · cm, 0.8 Ω · cm, 0.9 Ω · cm, 1 Ω · cm, 2 Ω · cm, 3 Ω · cm, 4 Ω · cm, 5 Ω · cm, 6 Ω · cm, 7 Ω · cm, 8 Ω · cm, 9 Ω · cm, 10 Ω · cm, or the like). The emitter 3 of the N-type crystalline silicon solar cell may be formed by doping group III elements (including but not limited to boron), the sheet resistance value of the emitter 3 formed after doping may be 40 Ω/□ -200 Ω/□ (e.g., 40 Ω/□, 50 Ω/□, 60 Ω/□, 70 Ω/□, 80 Ω/□, 90 Ω/□, 100 Ω/□, 110 Ω/□, 120 Ω/□, 130 Ω/□, 140 Ω/□, 150 Ω/□, 160 Ω/□, 170 Ω/□, 180 Ω/□, 190 Ω/□, 200 Ω/□, etc.), and the sheet resistance values of different regions of the emitter 3 may be the same or different.

It should be further noted that the N-type crystalline silicon solar cell provided by the embodiment of the present invention may be understood as including: an N-type crystalline silicon substrate 1, an emitter electrode 3 disposed on the front surface (i.e., light receiving surface) of the N-type crystalline silicon substrate 1, a front passivation layer 2 disposed on the emitter electrode 3, a front electrode 6 disposed on the front passivation layer 2, a back passivation layer 5 disposed on the back surface (i.e., backlight surface) of the N-type crystalline silicon substrate 1, and a back electrode 7 disposed on the back passivation layer 5. Namely, in the N-type crystalline silicon solar cell, the front surface of an N-type crystalline silicon substrate 1 is sequentially provided with an emitter 3, a front passivation layer 2 and a front electrode 6 from inside to outside, and the back surface of the N-type crystalline silicon substrate 1 is sequentially provided with a back passivation layer 5 and a back electrode 7 from inside to outside. The front passivation layer 2 includes a gallium oxide layer 21 in contact with the emitter 3, and may further include a capping layer 22 disposed on the gallium oxide layer 21. The front electrode 6 forms an ohmic contact with the emitter 3 through the front passivation layer 2. According to different cell types, the N-type crystalline silicon solar cell provided by the embodiment of the invention may further include an N-type doped layer 41 disposed on the back surface of the N-type crystalline silicon substrate 1, the back passivation layer 5 is disposed on the N-type doped layer 41, and the back electrode 7 passes through the back passivation layer 5to form ohmic contact with the N-type doped layer 41; or, the N-type crystal silicon substrate may further include a tunnel oxide layer 42 disposed on the back surface of the N-type crystal silicon substrate 1 and a doped silicon layer 43 disposed on the tunnel oxide layer 42, wherein a back passivation layer 45 is disposed on the doped silicon layer 43, and the back electrode 7 forms an ohmic contact with the doped silicon layer 43 through the back passivation layer 5.

The following is a description of a method for manufacturing an N-type crystalline silicon solar cell provided in an embodiment of the present invention.

The preparation method of the N-type crystalline silicon solar cell provided by the embodiment of the invention comprises the following steps:

step S1, providing an N-type crystal silicon substrate 1;

step S2, forming an emitter 3 on the front surface of the N-type crystal silicon substrate 1;

in step S3, the gallium oxide layer 21 is formed on the emitter 3 so as to be in direct contact with the emitter 3.

As described above, in the N-type crystalline silicon solar cell prepared by the preparation method provided by the embodiment of the present invention, the gallium oxide layer 21 with negative charges directly contacts with the surface of the P-type silicon (the emission electrode in the N-type crystalline silicon solar cell is P-type silicon), on one hand, chemical passivation and field passivation are performed on the surface of the P-type silicon, so as to reduce the minority carrier recombination rate at the surface of the P-type silicon, on the other hand, absorption of incident light is reduced, so as to improve the photo-generated current density of the cell, and by combining the above two aspects, the photoelectric conversion efficiency of the solar cell is improved, so as to improve the output power of the photovoltaic module, reduce the electricity consumption cost, and improve the cost performance of photovoltaic power.

In the embodiment of the present invention, the gallium oxide layer 21 may be formed by an Atomic Layer Deposition (ALD), a Plasma Enhanced Chemical Vapor Deposition (PECVD), an Atmospheric Pressure Chemical Vapor Deposition (APCVD), or a Low Pressure Chemical Vapor Deposition (LPCVD). After the deposition of the gallium oxide layer 21 is completed, an annealing step may also be performed.

Further, in this embodiment of the present invention, step S1 may specifically include:

in step S11, an N-type single crystal silicon wafer or an N-type polycrystalline silicon wafer having an appropriate resistivity is selected as the N-type crystal silicon substrate 1.

Step S12, the N-type crystal silicon substrate 1 is cleaned and the front surface of the N-type crystal silicon substrate 1 is textured to reduce the reflectivity of the front surface of the N-type crystal silicon substrate. After texturing, the reflectivity of the surface of the monocrystalline silicon wafer may be between 10% and 18% (e.g., 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, etc.), and the reflectivity of the surface of the polycrystalline silicon wafer may be between 6% and 20% (e.g., 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, etc.).

Further, in the embodiment of the present invention, in step S2, for example, doping with boron element, the emitter 3 may be formed on the front surface of the N-type crystalline silicon substrate by furnace boron diffusion, APCVD deposition of borosilicate glass (BSG), or boron ion implantation.

Further, in the embodiment of the present invention, for preparing an N-type crystalline silicon bifacial solar cell, the following steps are further included between step S2 and step S3:

1) the back surface of the N-type crystal silicon substrate 1 is planarized by flattening the back surface of the N-type crystal silicon substrate 1 with a chemical solution to appropriately reduce the specific surface area of the back surface of the N-type crystal silicon substrate 1, and thereafter the silicon wafer is cleaned with hydrofluoric acid (e.g., an aqueous solution of HF). Wherein, the chemical solution for leveling the back surface of the N-type crystal silicon substrate 1 can be an alkali solution, including but not limited to a tetramethylammonium hydroxide (TMAH) solution, a sodium hydroxide (NaOH) solution, a potassium hydroxide (KOH), etc., and the concentration of the alkali solution can be adjusted as required; it may also be an acid solution, such as nitric acid (HNO)₃) Hydrofluoric acid (HF) and sulfuric acid (H)₂SO₄) The concentration of each acid liquid in the mixed solution and the proportion of each acid liquid can be adjusted according to the requirement.

2) The back surface of the N-type crystal silicon substrate 1 is doped to form an N-type doped layer 41, and for example, phosphorus doping is performed by depositing PSG by phosphorus ion implantation or APCVD and annealing.

For the preparation of a Topcon solar cell, the following steps are also included between step S2 and step S3:

1) the back surface of the N-type crystal silicon substrate 1 is planarized by a chemical solution to appropriately reduce the specific surface area of the back surface of the N-type crystal silicon substrate 1, and then the silicon wafer is cleaned with hydrofluoric acid (aqueous HF solution). Wherein, the chemical solution for leveling the back surface of the N-type crystal silicon substrate 1 may be an alkali solution, including but not limited to a tetramethylammonium hydroxide (TMAH) solution, a sodium hydroxide (NaOH) solution, potassium hydroxide (KOH), etc.; it may also be nitric acid (HNO)₃) Hydrofluoric acid (HF) and sulfuric acid (H)₂SO₄) The mixed acid solution of (1).

2) The tunneling oxide layer 42 is grown on the back surface of the N-type crystal silicon substrate 1, and may be grown by a thermal oxidation method.

3) A doped silicon layer 43 is formed on the tunnel oxide layer 42, for example, by growing a silicon layer (amorphous layer or polysilicon layer) by LPCVD and doping the silicon layer with phosphorus.

Further, in the embodiment of the present invention, after step S3, the method further includes the following steps:

1) a cap layer 22 is formed on the gallium oxide layer 21, and a back passivation layer 5 is formed on the N-type doped layer 41 (or the doped silicon layer 43). If the composition of the cover layer 22 and the back passivation layer 5 is the same, the steps of forming the cover layer 22 and the back passivation layer 5 may be performed simultaneously.

2) Back electrode printing and front electrode printing, and then performing rapid high-temperature sintering. The sintering temperature may be 600 to 900 ℃ (for example, 600 ℃, 650 ℃, 700 ℃, 750 ℃, 800 ℃, 850 ℃, 900 ℃, etc.), and the sintering time may be 10 seconds to 3 minutes, for example, 10 seconds, 20 seconds, 30 seconds, 40 seconds, 60 seconds, 70 seconds, 80 seconds, 90 seconds, 100 seconds, 110 seconds, 120 seconds, 130 seconds, 140 seconds, 150 seconds, 160 seconds, 170 seconds, 180 seconds, etc.

Based on the N-type crystalline silicon solar cell, an embodiment of the invention provides a photovoltaic module, which comprises a cover plate, a first packaging adhesive film, a cell string, a second packaging adhesive film and a back plate, wherein the cover plate, the first packaging adhesive film, the cell string, the second packaging adhesive film and the back plate are sequentially arranged, the cell string comprises a plurality of solar cells, and the solar cells are the N-type crystalline silicon solar cells provided by the embodiment of the invention.

The N-type crystalline silicon solar cell provided by the embodiment of the invention is provided with the gallium oxide layer which is directly contacted with the P-type emitter, the negative charge carried by the gallium oxide layer is utilized to carry out chemical passivation and field passivation on the surface of the P-type silicon, and the absorption of incident light is reduced to improve the photo-generated current density of the cell, so that the photoelectric conversion efficiency of the solar cell is obtained, therefore, a photovoltaic module using the N-type crystalline silicon solar cell has higher output power, the electricity consumption cost is favorably reduced, and the cost performance of photovoltaic power generation is improved.

In the embodiment of the invention, the cover plate is a glass plate, the first packaging adhesive film and the second packaging adhesive film are made of EVA (ethylene-vinyl acetate copolymer), and the back plate can be a glass plate or a TPT (PVF/PET/PVF) plate. When the back plate adopts a TPT plate, the photovoltaic module further comprises a frame, and silica gel is filled in the frame.

The N-type crystalline silicon solar cell and the method for manufacturing the N-type crystalline silicon solar cell provided by the embodiment of the invention are further described below by taking an N-type crystalline silicon double-sided solar cell and a Topcon solar cell as examples.

Example 1

The present embodiment provides a gallium oxide passivated N-type crystalline silicon bifacial solar cell, which comprises a front electrode 6, a front passivation layer 2, an emitter 3, an N-type crystalline silicon substrate 1, an N-type doped layer 41, a back passivation layer 5 and a back electrode 7, which are sequentially arranged from the front side (i.e. the light receiving surface of the solar cell) to the back side (i.e. the back light surface of the solar cell), as shown in fig. 2.

Wherein the N-type crystalline silicon substrate 1 is an N-type single crystal silicon wafer having a resistivity of 2.0. omega. cm and a size of 156.75 mm. times.156.75 mm. The emitter 3 is formed by furnace tube boron diffusion, and the resistance value of the doped rear block is 80 omega/□.

The front passivation layer 2 comprises a gallium oxide layer 21 in direct contact with the emitter 3 and a silicon nitride capping layer 22 disposed on the gallium oxide layer 21, wherein the gallium oxide layer 21 has a thickness of 20 nm and the silicon nitride capping layer 22 has a thickness of 65 nm.

The N-type doped layer 41 on the back surface of the N-type crystalline silicon substrate 1 is formed by a phosphorus ion implantation method, and the square resistance after doping is 110 omega/□.

The back passivation layer 5 on the N-doped layer 41 is a silicon nitride layer with a thickness of 75 nm.

The front electrode 6 and the back electrode 7 are both of a grid line structure, wherein the width of each main grid line is 4, the width of each main grid line is 1.1 mm, the width of each secondary grid line is 102, the width of each secondary grid line is 40 micrometers, the distance between every two adjacent secondary grid lines is 1.5 mm, and the front electrode and the back electrode are both formed by Helelis (Heraeus) SOL9360 type silver paste.

The preparation method of the solar cell provided in this embodiment is as follows:

step 101, using NaOH and H₂O₂Mixed aqueous solution of (NaOH, H)₂O₂And H₂O is mixed according to the mass ratio of 0.5 to 1 to 98.5 percent) to clean the N-type monocrystalline silicon wafer (the cleaning time is 2min), then, the front side of the N-type monocrystalline silicon wafer is subjected to wool making by using a sodium hydroxide aqueous solution with the mass concentration of 3 percent, and after the wool making, the reflectivity of the front side of the N-type monocrystalline silicon wafer is 12 percent.

And step 102, carrying out boron doping on the front side of the textured N-type monocrystalline silicon wafer by using a furnace tube boron diffusion method to prepare an emitter so as to form a P-N junction. Wherein, furnace tube boron diffusion adopts TS-81255 type diffusion furnace of Tempress company, and the diffusion condition is: by BBr₃As a boron source, stone in a diffusion furnace at 940 ℃BBr is introduced into quartz tube₃(passage time 20min), after which the passage of BBr is stopped₃And incubated at 960 deg.C for 20 min.

And 103, soaking the diffused N-type monocrystalline silicon piece in a TMAH solution with the mass concentration of 20% at 70 ℃ for 5min, flattening the back surface of the N-type monocrystalline silicon piece, and cleaning the silicon piece for 2min by using an HF aqueous solution with the mass concentration of 10%.

Step 104, implanting phosphorus ions into the back surface of the N-type monocrystalline silicon wafer by using an iPV-2000 type ion implanter of Kingston corporation (Shanghai Kaiki semiconductor corporation), and doping phosphorus to form an N-type doped layer, wherein the implantation conditions are as follows: ion acceleration voltage is 10kV, beam current is 120mA after acceleration, and the vacuum degree of an ion implantation chamber is 2 multiplied by 10^-5Torr。

Step 105, depositing a gallium oxide film on the emitter by a PEALD method, wherein the equipment is a TFS 200 type atomic layer deposition film system of Finland times of gram (Beneq) company, and the deposition conditions are as follows: temperature of 75 deg.C, pressure of 0.25Torr, volume flow rate of trimethyl gallium (TMGa) of 70sccm (normal state ml/min), O₂The volume flow of (2) is 200 sccm.

106, forming a silicon nitride film on the emitter and the N-type doped layer by adopting a PECVD method, wherein the equipment is ROTH&SINA type PECVD equipment of RAU company, the deposition conditions are as follows: temperature 400 deg.C, pressure 0.25mBar, SiH₄The volume flow of (2) is 100sccm, NH₃The volume flow of (3) is 180 sccm.

Step 107, screen printing paste for forming the back electrode using a Baccini speed inking type printer (the same below) of applied materials.

Step 108, screen printing paste for forming the front electrode.

Step 109, sintering at 820 ℃ for 10 seconds; after sintering, the front metal silver penetrates through the silicon nitride/gallium oxide film to form local ohmic contact with the emitter, and the back silver paste corrodes the silicon nitride film to form ohmic contact with the N-type doped layer.

The performance of the solar cell provided in this example was tested using the I-V test method (type I-V tester CetisPV-XF2-PB from Halm, Germany) (test conditions 25 ℃ C., spectral conditions AM1.5) and the results were: the open-circuit voltage is 0.668V, the short-circuit current is 9.77A, and the photoelectric conversion efficiency is 21.1%.

Example 2

The present embodiment provides a gallium oxide passivated N-type crystalline silicon bifacial solar cell, and the solar cell provided in the present embodiment is different from the solar cell provided in embodiment 1 in that the thickness of the gallium oxide layer in the solar cell provided in the present embodiment is 1 nm.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage was 0.661V, the short-circuit current was 9.79A, and the photoelectric conversion efficiency was 20.92%.

Example 3

The embodiment provides a gallium oxide passivated N-type crystalline silicon double-sided solar cell, and the solar cell provided by the embodiment is different from the solar cell provided by the embodiment 1 in that the thickness of a gallium oxide layer in the solar cell provided by the embodiment is 40 nanometers.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.668V, the short-circuit current is 9.75A, and the photoelectric conversion efficiency is 21.06%.

Example 4

The embodiment provides a gallium oxide passivated N-type crystalline silicon double-sided solar cell, and the solar cell provided by the embodiment is different from the solar cell provided by the embodiment 1 in that the thickness of a gallium oxide layer in the solar cell provided by the embodiment is 80 nanometers.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.668V, the short-circuit current is 9.73A, and the photoelectric conversion efficiency is 20.69%.

Example 5

The embodiment provides a gallium oxide passivated N-type crystalline silicon double-sided solar cell, and the solar cell provided by the embodiment is different from the solar cell provided by the embodiment 1 in that the thickness of a gallium oxide layer in the solar cell provided by the embodiment is 120 nanometers.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.667V, the short-circuit current is 9.58A, and the photoelectric conversion efficiency is 19.87%.

Comparative example 1

The present comparative example provides an N-type crystalline silicon bifacial solar cell without a gallium oxide layer, and the solar cell provided by the present comparative example is different from the solar cell provided in example 1 in that no gallium oxide layer is provided in the solar cell provided by the present comparative example. When the solar cell is prepared, a silicon nitride film is directly formed on the emitter.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.656V, the short-circuit current is 9.8A, and the photoelectric conversion efficiency is 20.78%.

Comparative example 2

This comparative example provides a zirconia passivated N-type crystalline silicon bifacial solar cell that differs from the solar cell provided in example 1 in that it isComparative example provides a solar cell using zirconium oxide (ZrO)_x) The film replaces the gallium oxide film. When the solar cell is prepared, a zirconium oxide film is firstly formed on the emitter, and then a silicon nitride film is formed on the zirconium oxide film.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open circuit voltage was 0.658V, the short circuit current was 9.62A, and the photoelectric conversion efficiency was 20.47%.

Comparative example 3

The comparative example provides a tantalum oxide passivated N-type crystalline silicon bifacial solar cell, which differs from the solar cell provided in example 1 in that tantalum oxide (TaO) is used in the solar cell provided in the comparative example_x) The film replaces the gallium oxide film. When the solar cell is prepared, a tantalum oxide film is firstly formed on the emitter, and then a silicon nitride film is formed on the tantalum oxide film.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.66V, the short-circuit current is 9.68A, and the photoelectric conversion efficiency is 20.66%.

Comparative example 4

The present comparative example provides a hafnium oxide passivated N-type crystalline silicon bifacial solar cell, which differs from the solar cell provided in example 1 in that hafnium oxide (HfO) is employed in the solar cell provided by the present comparative example_x) The film replaces the gallium oxide film. When the solar cell is prepared, a hafnium oxide film is formed on the emitter, and then a silicon nitride film is formed on the hafnium oxide film.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.665V, the short-circuit current is 9.73A, and the photoelectric conversion efficiency is 20.92%.

In the following table 1, the results of the performance test of the solar cells of the above examples 1 to 5 and comparative examples 1 to 4 are summarized.

TABLE 1 summary of solar Performance test results

Serial number	Oxide type	Thickness of oxide film	Open circuit voltage	Short circuit current	Photoelectric conversion efficiency
						Example 1	Gallium oxide	20 nm	0.668V	9.77A	21.1％
Example 2	Gallium oxide	1 nm	0.661V	9.79A	20.92％
						Example 3	Gallium oxide	40 nm	0.668V	9.75A	21.06％
Example 4	Gallium oxide	80 nm	0.668V	9.73A	20.69％
						Example 5	Gallium oxide	120 nm	0.667V	9.58A	19.87％
Comparative example 1	——	——	0.656V	9.8A	20.78％
						Comparative example 2	Zirconium oxide	20 nm	0.658V	9.62A	20.47％
Comparative example 3	Tantalum oxide	20 nm	0.66V	9.68A	20.66％
						Comparative example 4	Hafnium oxide	20 nm	0.665V	9.73A	20.92％

Example 6

The present embodiment provides a gallium oxide passivated Topcon solar cell, as shown in fig. 3, which includes a front electrode 6, a front passivation layer 2, an emitter 3, an N-type crystalline silicon substrate 1, a tunnel oxide layer 42, a doped polysilicon layer, a back passivation layer 5 and a back electrode 7, which are sequentially arranged from the front side (i.e. the light receiving surface of the solar cell) to the back side (i.e. the back light surface of the solar cell).

The thickness of the tunneling oxide layer 42 is 1.8 nm; the thickness of the doped polysilicon layer is 100 nm and is doped with phosphorus, and the square resistance after doping is 38 omega/□.

The back passivation layer is a silicon nitride layer with a thickness of 70 nm.

The front electrode and the back electrode are both of a grid line structure, wherein 4 main grid lines are provided, the width of each main grid line is 1.1 mm, 102 auxiliary grid lines are provided, the width of each auxiliary grid line is 40 micrometers, the distance between every two adjacent auxiliary grid lines is 1.5 mm, the front electrode is formed by silver paste of Hello (Heraeus) SOL9360 type, and the back electrode is formed by silver paste of Heraeus (Heraeus) SOL9621 type.

step 601, using NaOH and H₂O₂Mixed aqueous solution of (NaOH, H)₂O₂And H₂O is mixed according to the mass ratio of 0.5 to 1 to 98.5 percent) to clean the N-type monocrystalline silicon wafer (the cleaning time is 2min), then, the front side of the N-type monocrystalline silicon wafer is subjected to wool making by using a sodium hydroxide aqueous solution with the mass concentration of 3 percent, and after the wool making, the reflectivity of the front side of the N-type monocrystalline silicon wafer is 12 percent.

Step 602, performing boron doping on the front side of the textured N-type monocrystalline silicon wafer by using a furnace tube boron diffusion method to prepare an emitter, so as to form a P-N junction. Wherein, furnace tube boron diffusion adopts TS-81255 type diffusion furnace of Tempress company, and the diffusion condition is: by BBr₃As a boron source, BBr is introduced into a quartz tube in a diffusion furnace at 940 DEG C₃(passage time 20min), after which the passage of BBr is stopped₃And incubated at 960 deg.C for 20 min.

And 603, soaking the diffused N-type monocrystalline silicon piece in 20 mass percent TMAH solution at 40 ℃ for 30s, flattening the back surface of the N-type monocrystalline silicon piece, and cleaning the silicon piece for 2min by using 10 mass percent HF aqueous solution.

Step 604, growing a tunneling oxide layer on the back surface of the N-type monocrystalline silicon wafer by a thermal oxidation method, wherein the specific process parameters are as follows: heating at 610 deg.C for 2min under oxygen atmosphere.

Step 605, growing a polysilicon layer on the tunnel oxide layer by LPCVD method, and performing phosphorus doping on the polysilicon layer by phosphorus ion implantation to form a doped polysilicon layer.

Wherein,the equipment for growing the polysilicon layer is 997-AAK LPCVD equipment of Tempress company, and the growth conditions are as follows: at a temperature of 600 ℃ SiH₄The volume flow rate of (2) is 600sccm, and the pressure is 0.25 Torr.

The equipment for injecting phosphorus ions is an iPV-2000 type ion implanter of Kingston company, and the injection conditions are as follows: ion acceleration voltage is 10kV, beam current is 120mA after acceleration, and the vacuum degree of an ion implantation chamber is 2 multiplied by 10^-5Torr。

Step 606, depositing a gallium oxide thin film on the emitter by PEALD using a TFS 200 atomic layer deposition thin film system of finland double-resistant-gram (Beneq) company, under the following deposition conditions: temperature of 75 deg.C, pressure of 0.25Torr, volume flow rate of trimethyl gallium (TMGa) of 70sccm (normal state ml/min), O₂The volume flow of (2) is 200 sccm.

Step 607, forming a silicon nitride film on the emitter and the doped polysilicon layer by PECVD using a ROTH equipment&SINA type PECVD equipment of RAU company, the deposition conditions are as follows: temperature 400 deg.C, pressure 0.25mBar, SiH₄The volume flow of (2) is 100sccm, NH₃The volume flow of (3) is 180 sccm.

Step 608, screen printing a paste for forming the back electrode using a Baccini speed inking type printer from applied materials.

In step 609, a paste for forming the front electrode is screen printed.

Step 610, sintering at 820 ℃ for 10 seconds; after sintering, the front metal silver penetrates through the silicon nitride/gallium oxide film to form local ohmic contact with the emitter, and the back silver paste corrodes the silicon nitride film to form ohmic contact with the doped polycrystalline silicon layer.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.689V, the short-circuit current is 9.98A, and the photoelectric conversion efficiency is 22.23%.

Example 7

This example provides a Topcon solar cell passivated with gallium oxide, and the solar cell provided in this example is different from the solar cell provided in example 6 in that the thickness of the gallium oxide layer in the solar cell provided in this example is 1 nm.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.687V, the short-circuit current is 9.99A, and the photoelectric conversion efficiency is 22.19%.

Example 8

This example provides a Topcon solar cell passivated with gallium oxide, and the solar cell provided in this example is different from the solar cell provided in example 6 in that the thickness of the gallium oxide layer in the solar cell provided in this example is 40 nm.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.688V, the short-circuit current is 9.896A, and the photoelectric conversion efficiency is 22.01%.

Example 9

This example provides a Topcon solar cell passivated with gallium oxide, and the solar cell provided in this example is different from the solar cell provided in example 6 in that the thickness of the gallium oxide layer in the solar cell provided in this example is 80 nm.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.688V, the short-circuit current is 9.73A, and the photoelectric conversion efficiency is 21.64%.

Example 10

The present embodiment provides a Topcon solar cell passivated with gallium oxide, and the solar cell provided in the present embodiment is different from the solar cell provided in embodiment 6 in that the thickness of the gallium oxide layer in the solar cell provided in the present embodiment is 120 nm.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.688V, the short-circuit current is 9.48A, and the photoelectric conversion efficiency is 20.77%.

Comparative example 5

The present comparative example provides a Topcon solar cell without a gallium oxide layer, and the solar cell provided by the present comparative example is different from the solar cell provided by example 6 in that the solar cell provided by the present comparative example does not have a gallium oxide layer. When the solar cell is prepared, a silicon nitride film is directly formed on the emitter.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.682V, the short-circuit current is 9.99A, and the photoelectric conversion efficiency is 22.03 percent.

Comparative example 6

This comparative example provides a zirconia passivated Topcon solar cell that differs from the solar cell provided in example 6 in that zirconia (ZrO) is used in the solar cell provided in this comparative example_x) The film replaces the gallium oxide film. When the solar cell is prepared, a zirconium oxide film is firstly formed on the emitter, and then a silicon nitride film is formed on the zirconium oxide film.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.680V, the short-circuit current is 9.86A, and the photoelectric conversion efficiency is 21.68%.

Comparative example 7

This comparative example provides a tantalum oxide passivated Topcon solar cell that differs from the solar cell provided in example 6 in that tantalum oxide (TaO) is used in the solar cell provided in this comparative example_x) The film replaces the gallium oxide film. When the solar cell is prepared, a tantalum oxide film is firstly formed on the emitter, and then a silicon nitride film is formed on the tantalum oxide film.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.682V, the short-circuit current is 9.97A, and the photoelectric conversion efficiency is 21.99 percent.

Comparative example 8

This comparative example provides a hafnium oxide passivated Topcon solar cell that differs from the solar cell provided in example 6 in that hafnium oxide (HfO) is employed in the solar cell provided by this comparative example_x) The film replaces the gallium oxide film. When the solar cell is prepared, a hafnium oxide film is formed on the emitter, and then a silicon nitride film is formed on the hafnium oxide film.

The performance of the solar cell provided in this example was tested according to the test method and test conditions of example 1, and the results were: the open-circuit voltage is 0.684V, the short-circuit current is 9.95A, and the photoelectric conversion efficiency is 22.0%.

In the following table 2, the results of the performance test of the solar cells of the above examples 6 to 10 and comparative examples 5to 8 are summarized.

TABLE 2 summary of solar Performance test results

Serial number	Oxide type	Thickness of oxide film	Open circuit voltage	Short circuit current	Photoelectric conversion efficiency
						Example 6	Gallium oxide	20 nm	0.689V	9.98A	22.23％
Example 7	Gallium oxide	1 nm	0.687V	9.99A	22.19％
						Example 8	Gallium oxide	40 nm	0.688V	9.896A	22.01％
Example 9	Gallium oxide	80 nm	0.688V	9.73A	21.64％
						Example 10	Gallium oxide	120 nm	0.688V	9.48A	20.77％
Comparative example 5	——	——	0.682V	9.99A	22.03％
						Comparative example 6	Zirconium oxide	20 nm	0.680V	9.86A	21.68％
Comparative example 7	Tantalum oxide	20 nm	0.682V	9.97A	21.99％
						Comparative example 8	Hafnium oxide	20 nm	0.684V	9.95A	22.0％

As can be seen from the test data of the above examples and comparative examples, the gallium oxide passivated N-type crystalline silicon solar cell provided by the example of the present invention has higher photoelectric conversion efficiency than an N-type crystalline silicon solar cell which is not provided with a gallium oxide layer and is passivated by replacing gallium oxide with other oxides.

The above description is only for facilitating the understanding of the technical solutions of the present invention by those skilled in the art, and is not intended to limit the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The N-type crystalline silicon solar cell comprises a front electrode (6), a front passivation layer (2), an emitting electrode (3), an N-type crystalline silicon substrate (1), a back passivation layer (5) and a back electrode (7) which are sequentially arranged, and is characterized in that the front passivation layer (2) comprises a gallium oxide layer (21) which is in direct contact with the emitting electrode (3).

2. Solar cell according to claim 1, characterized in that the thickness of the gallium oxide layer (21) is comprised between 1 nm and 120 nm.

3. Solar cell according to claim 2, characterized in that the thickness of the gallium oxide layer (21) is comprised between 10 and 60 nanometers.

4. The solar cell according to claim 1, characterized in that the front side passivation layer (2) further comprises a capping layer (22) disposed on the gallium oxide layer (21), the capping layer (22) comprising at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer and a silicon carbide layer, the capping layer (22) having a thickness of 10 nm to 120 nm.

5. The solar cell of claim 1, further comprising: an N-type doped layer (41) disposed on the back surface of the N-type crystalline silicon substrate (1);

the back passivation layer (5) is arranged on the N-type doping layer (41), and the back electrode (7) penetrates through the back passivation layer (5) to form ohmic contact with the N-type doping layer (41);

the back passivation layer (5) comprises at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer and a silicon carbide layer, and the thickness of the back passivation layer (5) is 30-200 nanometers.

6. The solar cell of claim 1, further comprising: a tunneling oxide layer (42) arranged on the back surface of the N-type crystal silicon substrate (1) and a doped silicon layer (43) arranged on the tunneling oxide layer (42); the doping source of the doped silicon layer (43) is a V-group element;

the back passivation layer (45) is arranged on the doped silicon layer (43), and the back electrode (7) forms ohmic contact with the doped silicon layer (43) through the back passivation layer (5);

the back passivation layer (5) comprises at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer and a silicon carbide layer;

the thickness of the tunneling oxide layer (42) is 0.5-6 nanometers, the thickness of the doped silicon layer (43) is 10-1000 nanometers, and the thickness of the back passivation layer (5) is 60-120 nanometers.

7. Solar cell according to claim 6, characterized in that the doped silicon layer (43) is a doped amorphous silicon layer or a doped polysilicon layer.

8. A preparation method of an N-type crystalline silicon solar cell is characterized by comprising the following steps:

providing an N-type crystalline silicon substrate (1);

forming an emitter (3) on the front surface of the N-type crystal silicon substrate (1);

a gallium oxide layer (21) is formed on the emitter (3) in direct contact with the emitter (3).

9. The production method according to claim, wherein the gallium oxide layer (21) is formed by a monoatomic layer deposition method, a plasma-enhanced chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, or a low pressure chemical vapor deposition method.

10. A photovoltaic module comprises a cover plate, a first packaging adhesive film, a battery string, a second packaging adhesive film and a back plate which are sequentially arranged, wherein the battery string comprises a plurality of solar batteries, and the photovoltaic module is characterized in that the solar batteries are the N-type crystalline silicon solar batteries according to any one of claims 1-7.