CN115692517A - P-type Topcon back junction battery metallized by electroplating process and preparation method thereof - Google Patents
P-type Topcon back junction battery metallized by electroplating process and preparation method thereof Download PDFInfo
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- 238000009713 electroplating Methods 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 82
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 168
- 239000002184 metal Substances 0.000 claims abstract description 168
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 238000002161 passivation Methods 0.000 claims abstract description 70
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 65
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 55
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- 230000005641 tunneling Effects 0.000 claims abstract description 32
- 239000013078 crystal Substances 0.000 claims abstract description 27
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 229910004205 SiNX Inorganic materials 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
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- 238000000151 deposition Methods 0.000 claims description 24
- 238000005245 sintering Methods 0.000 claims description 24
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 21
- 229910052698 phosphorus Inorganic materials 0.000 claims description 21
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Abstract
The invention provides a P-type Topcon back junction battery metalized by adopting an electroplating process and a preparation method thereof, and the P-type Topcon back junction battery is characterized by comprising the following steps: the P-type crystalline silicon substrate comprises a P-type crystalline silicon substrate, and a P + high-low junction, a silicon oxide passivation layer, an aluminum oxide passivation layer, a SiNx antireflection passivation layer, a first metal layer, a second metal layer and a third metal layer which are sequentially grown on the front surface of the P-type crystalline silicon substrate; and a silicon oxide tunneling layer, a polysilicon layer, a SiNx antireflection passivation layer, a first metal layer, a second metal layer and a third metal layer are sequentially grown on the back surface of the P-type crystal silicon substrate. The invention has the advantages that the traditional method for screen printing silver paste is replaced by the electroplating method, so that better electrical property is realized, and the battery can obtain calling efficiency of more than 24%; and the manufacturing cost of the non-silicon part of the cell can be greatly reduced, so that the P-type Topcon back junction solar cell is more competitive than the PERC, N-type Topcon and other cells.
Description
Technical Field
The invention belongs to the field of chemical detection and analysis equipment, and particularly relates to a P-type Topcon back junction battery metallized by an electroplating process and a preparation method thereof.
Background
Compared with the IBC battery and the N-type Topcon battery which are in cross contact with the back surfaces, the P-type Topcon back junction solar battery has the advantages of thin silicon wafer, simple structure, low cost and excellent efficiency performance, and is very suitable for the technical development direction of the solar industry. The main problem of the P-type Topcon back junction solar cell is still the cost problem of silver paste, and in addition, the contact problem between the P-type silicon substrate and metal on the front surface of the Topcon cell is also an important problem.
The screen printing mode that generally adopts in the trade at present, the high cost of silver thick liquid and silver-aluminum thick liquid is the problem that needs to solve, and P type Topcon back junction solar cell front metallization uses current screen printing technology grid line width can't accomplish below 20um simultaneously, highly can't accomplish more than 18 um. In the prior art, metallization is carried out through an electroplating process to replace screen printing for metallization, so that the problem of emitter damage is easily caused during slotting, and the condition that the final use effect of the battery is poor or even the battery cannot be used is caused.
Disclosure of Invention
The invention aims to provide a P-type Topcon back junction solar cell metallized by an electroplating process and a preparation method thereof, effectively solve the problems that the grid line width cannot be less than 20um and the height cannot be more than 18um when the front side of the P-type Topcon back junction solar cell is metallized by the existing screen printing process, solve the problem that the cost of silver paste and silver-aluminum paste of the P-type Topcon back junction solar cell is high, and simultaneously avoid the problem of emitter damage caused by laser grooving of the electroplating process.
In order to solve the technical problems, the invention adopts the technical scheme that: a P type Topcon back junction battery metallized by electroplating process is characterized by comprising: the P-type crystalline silicon substrate comprises a P-type crystalline silicon substrate, and a P + high-low junction, a silicon oxide passivation layer, an aluminum oxide passivation layer, a SiNx antireflection passivation layer, a first metal layer, a second metal layer and a third metal layer which are sequentially grown on the front surface of the P-type crystalline silicon substrate; and a silicon oxide tunneling layer, a polysilicon layer, a SiNx antireflection passivation layer, a first metal layer, a second metal layer and a third metal layer are sequentially grown on the back surface of the P-type crystal silicon substrate.
Preferably, the front surface of the P-type crystal silicon substrate is provided with a first groove, wherein the P + high-low junction, the first metal layer, the second metal layer and the third metal layer are sequentially grown in the first groove.
Preferably, a second groove is formed in the back surface of the P-type crystal silicon substrate, wherein the first metal layer, the second metal layer and the third metal layer are grown in the second groove in sequence.
A method for preparing a P-type Topcon back junction battery of claim 1 metallized by an electroplating process, comprising:
texturing the surface of the P-type crystal silicon substrate;
growing a layer of the silicon oxide tunneling layer on the back surface of the P-type crystal silicon substrate, depositing an amorphous silicon layer on the silicon oxide tunneling layer, doping phosphorus into the amorphous silicon layer, and annealing to obtain a phosphorus-doped polycrystalline silicon layer;
removing the phosphorus-doped polycrystalline silicon layer on the front surface and the edge winding part of the P-type crystalline silicon substrate, and preparing a silicon oxide passivation layer on the front surface of the P-type crystalline silicon substrate;
growing an aluminum oxide passivation layer on the silicon oxide passivation layer, and depositing a SiNx antireflection passivation layer on the aluminum oxide passivation layer and the polysilicon layer;
respectively grooving the front surface and the back surface of the processed P-type crystal silicon substrate, forming a first groove on the front surface, and forming a second groove on the back surface;
carrying out boron diffusion treatment on the first groove, preparing the p + high-low junction, and immersing the p + high-low junction into an active agent;
taking out the P-type crystal silicon substrate, electroplating a first metal layer in the first groove and the second groove to obtain an electroplating sample, and sintering the electroplating sample in a high-temperature furnace;
cleaning after sintering is finished, and electroplating the second metal layer on the first metal layer;
and cleaning after the electroplating is finished, and electroplating the third metal layer on the second metal layer to obtain the P-type Topcon back junction battery metalized by adopting an electroplating process.
Preferably, the P-type crystalline silicon substrate has a resistivity of 0.5 to 5 Ω · cm and a thickness of 80 to 200um.
Preferably, in the step of growing a layer of the silicon oxide tunneling layer on the back surface of the P-type crystalline silicon substrate, the silicon oxide tunneling layer is made of silicon dioxide, and the silicon oxide tunneling layer is grown on the back surface of the P-type crystalline silicon substrate by thermal oxidation, HN03 oxidation or atomic layer deposition, wherein the thickness of the silicon oxide tunneling layer is 0.5-3nm.
Preferably, in the process of depositing the phosphorus-doped amorphous silicon layer, the phosphorus-doped amorphous silicon layer is deposited on the silicon oxide tunneling layer by a magnetron sputtering method, an LPCVD method, or a PECVD method.
Preferably, the deposition temperature of the amorphous silicon layer doped with phosphorus is 250-650 ℃; the thickness of the amorphous silicon layer doped with phosphorus is 60-150nm.
Preferably, the SiN deposited on the polysilicon layer x The thickness of the anti-reflection passivation layer is 60-120nm, the thickness of the aluminum oxide passivation layer grown on the front surface is 1-5nm, and the SiN deposited on the aluminum oxide passivation layer x The thickness of the antireflection passivation layer is 60-110nm.
Preferably, in the step of respectively grooving the front surface and the back surface of the processed P-type crystal silicon substrate, the first groove is formed to the surface of the P-type crystal silicon substrate, the second groove is formed to the surface of the polysilicon layer, and then the first groove and the second groove are cleaned to remove impurities remaining during grooving.
Preferably, the first metal layer is a Ni metal layer, a Ti metal layer or a Cr metal layer, and the thickness is 0.1-5 μm; sending the electroplating sample into a high-temperature furnace protected by inert gas for sintering, wherein the sintering temperature is 200-400 ℃;
the second metal layer is a Cu metal layer, and the thickness of the second metal layer is 5-15 mu m;
the third metal layer is an Ag metal layer, and the weight of the third metal layer is 3-5mg.
More preferably, the first metal layer, the second metal layer and the third metal layer are electroplated into the first groove and/or the second groove by chemical plating or light induction electroplating; the widths of the first metal layer, the second metal layer and the third metal layer are +/-3 mu m of the width of the first groove or the second groove.
By adopting the technical scheme, the P-type Topcon back junction solar cell adopts an electroplating metallization process, and due to the unique design of the front surface without PN junction and the back surface with epitaxial polycrystalline silicon layer, the problem of emitter damage caused by laser grooving of the electroplating process is avoided, and meanwhile, the perfect combination of contact and passivation is achieved by combining the low contact resistivity of the electroplating process on the silicon-based cell.
Optical design is optimized, the problems that the width of a grid line cannot be reduced to be less than 20um and the height cannot be increased to be more than 18um in the existing screen printing process for front metallization of the P-type Topcon back junction solar cell are solved, and meanwhile, the problem that silver paste and silver-aluminum paste of the P-type Topcon back junction solar cell are high in cost is solved by replacing a screen printing scheme with an electrical metallization scheme.
Drawings
FIG. 1 is a schematic structural diagram of a P-type Topcon back junction battery metallized by an electroplating process according to an embodiment of the present invention
In the figure:
1. third metal layer 2, second metal layer 3, first metal layer
4、SiN x Antireflection passivation layer 5, aluminum oxide passivation layer 6 and silicon oxide passivation layer
7. Silicon oxide tunneling layer 8, P + high-low junction 9, P-type crystalline silicon substrate
10. Polycrystalline silicon layer
Detailed Description
The invention is further illustrated by the following examples and figures:
in the description of the embodiments of the present invention, it should be understood that the terms "top," "bottom," and the like refer to orientations and positional relationships illustrated in the drawings, which are used for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present invention.
As shown in fig. 1, a schematic structural diagram of a P-type Topcon back junction battery metallized by an electroplating process, comprising: the solar cell comprises a P-type crystalline silicon substrate 9, and a P + high-low junction 8, a silicon oxide passivation layer 6, an aluminum oxide passivation layer 5, a SiNx antireflection passivation layer 4, a first metal layer 3, a second metal layer 2 and a third metal layer 1 which are sequentially grown on the front surface of the P-type crystalline silicon substrate 9; and a silicon oxide tunneling layer 7, a polycrystalline silicon layer 10, a SiNx antireflection passivation layer 4, a first metal layer 3, a second metal layer 2 and a third metal layer 1 are sequentially grown on the back surface of the P-type crystalline silicon substrate 9.
Specifically, a first groove is formed in the front surface of the P-type crystal silicon substrate 9, wherein the P + high-low junction 8, the first metal layer 3, the second metal layer 2 and the third metal layer 1 sequentially grow in the first groove, the first groove is formed in the surface of the P-type crystal silicon substrate, all films inside the first groove are thoroughly removed, the surface of the P-type crystal silicon substrate is not damaged, and then boron diffusion operation is performed on the surface of the P-type crystal silicon substrate, so that the P + high-low junction 8 is obtained.
The back of the P-type crystal silicon substrate is provided with a second groove, wherein the first metal layer 3, the second metal layer 2 and the third metal layer 1 are sequentially grown in the second groove, the second groove is formed to the phosphorus-doped polycrystalline silicon layer 10, the surface of the polycrystalline silicon layer 10 is not damaged, and the stable metallization is ensured.
Compared with a screen printing mode generally adopted in the industry, the electroplating metallization process of the solar cell can well solve the cost problem of silver paste, and laser grooving required by the electroplating process cannot damage a front emitter and a rear Poly passivation contact layer of the P-type Topcon back junction solar cell.
The following describes a method for preparing a P-type Topcon back junction battery, comprising:
s1: selecting a P-type crystalline silicon substrate with the resistivity of 0.5-5 omega-cm and the thickness of 80-200 um, and performing texturing treatment on the surface of the P-type crystalline silicon substrate 9.
S2: growing a silicon oxide tunneling layer 7 on the back surface of a P-type crystalline silicon substrate 9, depositing an amorphous silicon layer on the silicon oxide tunneling layer 7, doping phosphorus in the amorphous silicon layer, and annealing to obtain a phosphorus-doped polycrystalline silicon layer 10; wherein,
in the step of growing a silicon oxide tunneling layer 7 on the back surface of the P-type crystalline silicon substrate 9, the silicon oxide tunneling layer 7 is made of silicon dioxide, the silicon oxide tunneling layer 7 is deposited on the back surface of the P-type crystalline silicon substrate 9 by thermal oxidation, HN03 oxidation or atomic layer deposition, and the thickness of the silicon oxide tunneling layer 7 is 0.5-3nm.
In the process of depositing the amorphous silicon layer doped with phosphorus, depositing the amorphous silicon layer doped with phosphorus on the silicon oxide tunneling layer 7 by adopting a magnetron sputtering method, an LPCVD method or a PECVD method; the deposition temperature of the amorphous silicon layer doped with phosphorus is 250-650 ℃; the thickness of the phosphorus-doped amorphous silicon layer is 60-150nm.
And annealing the amorphous silicon layer to activate phosphorus atoms as substitutional impurities, or performing phosphorus diffusion doping treatment to obtain a phosphorus-doped polycrystalline silicon layer 10.
S3: removing the phosphorus-doped polycrystalline silicon layer 10 on the front surface and the edge of the P-type crystalline silicon substrate 9, and preparing a silicon oxide passivation layer 6 on the front surface of the P-type crystalline silicon substrate 9 by adopting a wet method;
s4: growing an aluminum oxide passivation layer 5 on the silicon oxide passivation layer 6, and depositing a SiNx antireflection passivation layer 4 on the aluminum oxide passivation layer 5 and the polysilicon layer 10; wherein,
SiN deposited on the polysilicon layer 10 x The thickness of the antireflection passivation layer 4 is 60-120nm, and SiN is deposited on the aluminum oxide passivation layer 5 x The thickness of the anti-reflection passivation layer 4 is 60-110nm.
S5: respectively slotting the front surface and the back surface of the processed P-type crystalline silicon matrix 9 by adopting laser, forming a first groove on the front surface according to a designed pattern, forming a second groove on the back surface according to the designed pattern, wherein,
the first groove is formed in the surface of the P-type crystalline silicon substrate 9, and the surface of the P-type crystalline silicon substrate 9 is not damaged; the second groove is formed on the surface of the polycrystalline silicon layer 10 without damaging the surface of the polycrystalline silicon layer 10, and then the first groove and the second groove are cleaned to remove the residual impurities during grooving.
S6: carrying out boron diffusion treatment on the first groove, preparing a P + high-low junction 8 in the first groove through an SE (selective emitter) process, and immersing a treated P-type crystalline silicon substrate 9 into an active agent after the preparation is finished;
s7: taking out the P-type crystalline silicon substrate 9, electroplating the first metal layer 3 in the first groove and the second groove to obtain an electroplating sample, and sintering the electroplating sample in a high-temperature furnace; the first metal layer 3 is a Ni metal layer, a Ti metal layer or a Cr metal layer, and the thickness is 0.1-5 μm; and (3) putting the electroplating sample into a high-temperature furnace protected by inert gas for sintering, wherein the sintering temperature is 200-400 ℃, and the inert gas can be nitrogen or argon.
S8: cleaning after sintering is finished, and electroplating a second metal layer 2 on the first metal layer 3; wherein,
the second metal layer 2 is a Cu metal layer, and the thickness is 5-15 mu m;
s9: after the electroplating is finished, cleaning is carried out, a third metal layer 1 is electroplated on the second metal layer 2, wherein,
the third metal layer 1 is an Ag metal layer, and the weight is 3-5mg;
the first metal layer 3, the second metal layer 2 and the third metal layer 1 are electroplated into the first groove and/or the second groove by chemical plating or light induction; the widths of the first metal layer 3, the second metal layer 2 and the third metal layer 1 are +/-3 mu m of the width of the first groove or the width of the second groove, and the P-type Topcon back junction battery metallized by the electroplating process is obtained.
According to the invention, through a metallization scheme of laser grooving on the front surface and the back surface of the P-type Topcon back junction solar cell and electroplating of Ni, cu and Ag, the semiconductor metal contact of silicon and Ni is realized, and the battery has very excellent contact resistivity by electroplating, wherein the contact resistivity can reach 0.5m omega cm 2 Compared with other batteries with other structures, the electroplating process is more suitable for being combined with the P-type Topcon back junction solar battery and reaches 1+1>2.
Meanwhile, the Ni layer effectively blocks the diffusion of Cu metal in silicon, and the metal on the front surface of the battery is compounded at 200-500 fA/cm -2 The back surface metal is compounded at 50-250 fA/cm -2 Thereby reducing the metal recombination on the surface of the battery while achieving good contact. Through electroplating the Cu metal, can reach than the higher aspect ratio of screen printing, traditional screen printing height 10 um/wide 40um, electroplating metal height 20 um/wide 15um, the light that the strickle line was positive to the battery that has significantly reduced shelters from, and electroplating Cu's conducting power is higher than the silver-colored line that has added glass material and other compositions simultaneously, and the surface of electroplating Cu plates Ag, satisfies solder strip welding and protects the purpose that Cu does not receive the oxidation.
The method for electroplating Ni, cu and Ag replaces the traditional method for screen printing Ag, realizes better electrical property and obtains more than 24 percent of battery conversion efficiency.
The electroplating method is adopted on the double sides of the P-type Topcon back junction solar cell, and the Ag metal is replaced by the cheap Cu metal, so that the non-silicon cost of the cell manufacture is greatly reduced, and the P-type Topcon back junction solar cell is more competitive than the PERC, n-type Topcon and other cells.
Several specific examples are listed below:
example 1
S1: a P-type crystalline silicon substrate with the resistivity of 1 omega cm and the thickness of 150um is selected, and the surface of the P-type crystalline silicon substrate 9 is subjected to texturing treatment.
S2: putting a P-type crystalline silicon substrate 9 into PEALD (plasma enhanced chemical vapor deposition) in-situ doping equipment, growing a silicon oxide tunneling layer 7 with the thickness of 1nm on the back surface of the P-type crystalline silicon substrate 9, depositing an amorphous silicon layer with the thickness of 120nm on the silicon oxide tunneling layer 7 by adopting a magnetron sputtering method, doping phosphorus on the amorphous silicon layer, wherein the deposition temperature is 400 ℃, then annealing, the annealing temperature is 850 ℃, activating phosphorus atoms to form substitutional impurities, or performing phosphorus diffusion doping treatment to obtain a phosphorus-doped polycrystalline silicon layer 10, and the sheet resistance is 200 omega/sqr after annealing.
S3: removing the phosphorus-doped polycrystalline silicon layer 10 on the front surface and the edge of the P-type crystalline silicon substrate 9, and preparing a silicon oxide passivation layer 6 with the thickness of 1nm on the front surface of the P-type crystalline silicon substrate 9 by adopting a wet method;
s4: performing ALD deposition of an aluminum oxide passivation layer 5 with the thickness of 1nm on the silicon oxide passivation layer 6, and depositing a SiNx antireflection passivation layer 4 on the aluminum oxide passivation layer 5 and the polysilicon layer 10; wherein,
SiN deposited on the polysilicon layer 10 x The thickness of the antireflection passivation layer 4 is 90nm, and the refractive index is 2.1; siN deposited on the alumina passivation layer 5 x The antireflection passivation layer 4 has a thickness of 80nm and a refractive index of 2.1.
S5: respectively slotting the front surface and the back surface of the processed P-type crystalline silicon matrix 9 by laser, forming a first groove on the front surface according to a designed pattern, forming a second groove on the back surface according to the designed pattern, wherein the widths of the first groove and the second groove are both 15 mu m,
the first groove is formed to the surface of the P-type crystalline silicon substrate 9, and the surface of the P-type crystalline silicon substrate 9 is not damaged; the second groove is formed on the surface of the polycrystalline silicon layer 10 without damaging the surface of the polycrystalline silicon layer 10, and then the first groove and the second groove are cleaned to remove the residual impurities during grooving.
S6: carrying out boron diffusion treatment on the first groove, preparing a P + high-low junction 8 in the first groove through an SE (selective emitter) process, and immersing a treated P-type crystalline silicon substrate 9 into an active agent after the preparation is finished;
s7: taking out the P-type crystalline silicon substrate 9, electroplating the first metal layer 3 in the first groove and the second groove to obtain an electroplating sample, and sintering the electroplating sample in a high-temperature furnace; the first metal layer 3 is a Ni metal layer with the thickness of 0.5 μm; and (3) putting the electroplating sample into a high-temperature furnace protected by inert gas for sintering, wherein the sintering temperature is 300 ℃, and the inert gas is nitrogen.
S8: cleaning after sintering is finished, and electroplating a second metal layer 2 on the first metal layer 3; wherein,
the second metal layer 2 is a Cu metal layer and has the thickness of 15 mu m;
s9: after the electroplating is finished, cleaning is carried out, a third metal layer 1 is electroplated on the second metal layer 2, wherein,
the third metal layer 1 was an Ag metal layer, weighing 4mg and having a thickness of 1 μm.
The first metal layer 3, the second metal layer 2 and the third metal layer 1 are electroplated into the first groove and/or the second groove by chemical plating or light induction; the widths of the first metal layer 3, the second metal layer 2 and the third metal layer 1 are 18 μm, and the P-type Topcon back junction battery metallized by the electroplating process is obtained.
Example 2
S1: selecting a P-type crystalline silicon substrate with the resistivity of 0.5 omega cm and the thickness of 80um, and performing texturing treatment on the surface of the P-type crystalline silicon substrate 9.
S2: putting a P-type crystalline silicon substrate 9 into PEALD (plasma enhanced chemical vapor deposition) in-situ doping equipment, growing a silicon oxide tunneling layer 7 with the thickness of 0.5nm on the back surface of the P-type crystalline silicon substrate 9, depositing an amorphous silicon layer with the thickness of 60nm on the silicon oxide tunneling layer 7 by adopting a magnetron sputtering method, doping phosphorus on the amorphous silicon layer, wherein the deposition temperature is 550 ℃, then annealing, the annealing temperature is 850 ℃, activating phosphorus atoms to be substitutional impurities, or performing phosphorus diffusion doping treatment to obtain a phosphorus-doped polycrystalline silicon layer 10, and the sheet resistance is 200 omega/sqr after annealing.
And annealing the amorphous silicon layer to activate phosphorus atoms as substitutional impurities, or performing phosphorus diffusion doping treatment to obtain the phosphorus-doped polycrystalline silicon layer 10.
S3: removing the phosphorus-doped polycrystalline silicon layer 10 on the front surface and the edge of the P-type crystalline silicon substrate 9, and preparing a silicon oxide passivation layer 6 with the thickness of 1nm on the front surface of the P-type crystalline silicon substrate 9 by adopting a wet method;
s4: growing an aluminum oxide passivation layer 5 on the silicon oxide passivation layer 6, and depositing a SiNx antireflection passivation layer 4 on the aluminum oxide passivation layer 5 and the polysilicon layer 10; wherein,
SiN deposited on the polysilicon layer 10 x An antireflective passivation layer 4 of thickness 60nm, siN deposited on the alumina passivation layer 5 x The thickness of the antireflective passivation layer 4 is 60nm.
S5: respectively slotting the front surface and the back surface of the processed P-type crystalline silicon matrix 9 by adopting laser, forming a first groove on the front surface according to a designed pattern, forming a second groove on the back surface according to the designed pattern, wherein the width of the first groove and the second groove is 15 mu m,
the first groove is formed to the surface of the P-type crystalline silicon substrate 9, and the surface of the P-type crystalline silicon substrate 9 is not damaged; the second groove is formed on the surface of the polycrystalline silicon layer 10 without damaging the surface of the polycrystalline silicon layer 10, and then the first groove and the second groove are cleaned to remove the residual impurities during grooving.
S6: carrying out boron diffusion treatment on the first groove, preparing a P + high-low junction 8 in the first groove through an SE (selective emitter) process, and immersing a treated P-type crystalline silicon substrate 9 into an active agent after the preparation is finished;
s7: taking out the P-type crystalline silicon substrate 9, electroplating the first metal layer 3 in the first groove and the second groove to obtain an electroplating sample, and sintering the electroplating sample in a high-temperature furnace; the first metal layer 3 is a Ni metal layer with the thickness of 0.1 μm; and (3) putting the electroplating sample into a high-temperature furnace protected by inert gas for sintering, wherein the sintering temperature is 200 ℃, and the inert gas is argon.
S8: cleaning after sintering is finished, and electroplating a second metal layer 2 on the first metal layer 3; wherein,
the second metal layer 2 is a Cu metal layer with the thickness of 5 mu m;
s9: after the electroplating is finished, cleaning is carried out, a third metal layer 1 is electroplated on the second metal layer 2, wherein,
the third metal layer 1 is an Ag metal layer with a weight of 4mg and a thickness of 1 μm,
the first metal layer 3, the second metal layer 2 and the third metal layer 1 are electroplated into the first groove and/or the second groove by chemical plating or light induction; the widths of the first metal layer 3, the second metal layer 2 and the third metal layer 1 are 12 micrometers, and the P-type Topcon back junction battery metalized by adopting an electroplating process is obtained.
Example 3
S1: selecting a P-type crystalline silicon substrate with the resistivity of 5 omega cm and the thickness of 200um, and performing texturing treatment on the surface of the P-type crystalline silicon substrate 9.
S2: putting a P-type crystalline silicon substrate 9 into PEALD (plasma enhanced chemical vapor deposition) in-situ doping equipment, growing a silicon oxide tunneling layer 7 with the thickness of 3nm on the back surface of the P-type crystalline silicon substrate 9, depositing an amorphous silicon layer with the thickness of 150nm on the silicon oxide tunneling layer 7 by adopting a magnetron sputtering method, doping phosphorus on the amorphous silicon layer, wherein the deposition temperature is 650 ℃, then annealing, the annealing temperature is 850 ℃, activating phosphorus atoms to form substitutional impurities, or performing phosphorus diffusion doping treatment to obtain a phosphorus-doped polycrystalline silicon layer 10, and the sheet resistance is 200 omega/sqr after annealing.
And annealing the amorphous silicon layer to activate phosphorus atoms as substitutional impurities, or performing phosphorus diffusion doping treatment to obtain a phosphorus-doped polycrystalline silicon layer 10.
S3: removing the phosphorus-doped polycrystalline silicon layer 10 on the front surface and the edge of the P-type crystalline silicon substrate 9, and preparing a silicon oxide passivation layer 6 with the thickness of 1nm on the front surface of the P-type crystalline silicon substrate 9 by adopting a wet method;
s4: growing an aluminum oxide passivation layer 5 on the silicon oxide passivation layer 6, and depositing a SiNx antireflection passivation layer 4 on the aluminum oxide passivation layer 5 and the polysilicon layer 10; wherein,
SiN deposited on the polysilicon layer 10 x An anti-reflection passivation layer 4 of thickness 120nm, siN deposited on the alumina passivation layer 5 x The thickness of the antireflective passivation layer 4 is 110nm.
S5: respectively slotting the front surface and the back surface of the processed P-type crystalline silicon matrix 9 by laser, forming a first groove on the front surface according to a designed pattern, forming a second groove on the back surface according to the designed pattern, wherein the width of the first groove and the second groove is 15 mu m,
the first groove is formed to the surface of the P-type crystalline silicon substrate 9, and the surface of the P-type crystalline silicon substrate 9 is not damaged; the second groove is formed on the surface of the polycrystalline silicon layer 10 without damaging the surface of the polycrystalline silicon layer 10, and then the first groove and the second groove are cleaned to remove the residual impurities during grooving.
S6: carrying out boron diffusion treatment on the first groove, preparing a P + high-low junction 8 in the first groove through an SE (selective emitter) process, and immersing a treated P-type crystalline silicon substrate 9 into an active agent after the preparation is finished;
s7: taking out the P-type crystalline silicon substrate 9, electroplating the first metal layer 3 in the first groove and the second groove to obtain an electroplating sample, and sintering the electroplating sample in a high-temperature furnace; the first metal layer 3 is a Cr metal layer with the thickness of 5 μm; and (3) putting the electroplating sample into a high-temperature furnace protected by inert gas for sintering, wherein the sintering temperature is 400 ℃, and the inert gas is argon.
S8: cleaning after sintering is finished, and electroplating a second metal layer 2 on the first metal layer 3; wherein,
the second metal layer 2 is a Cu metal layer and has the thickness of 15 mu m;
s9: after the electroplating is finished, cleaning is carried out, a third metal layer 1 is electroplated on the second metal layer 2, wherein,
the third metal layer 1 is an Ag metal layer with a weight of 4mg and a thickness of 1 μm,
the first metal layer 3, the second metal layer 2 and the third metal layer 1 are electroplated into the first groove and/or the second groove by chemical plating or light induction; the widths of the first metal layer 3, the second metal layer 2 and the third metal layer 1 are 15 micrometers, and the P-type Topcon back junction battery metalized by adopting an electroplating process is obtained.
Although the embodiments of the present invention have been described in detail, the description is only for the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention shall fall within the scope of the present invention.
Claims (12)
1. A P type Topcon back junction battery metallized by electroplating process is characterized by comprising: the P-type crystalline silicon substrate comprises a P-type crystalline silicon substrate, and a P + high-low junction, a silicon oxide passivation layer, an aluminum oxide passivation layer, a SiNx antireflection passivation layer, a first metal layer, a second metal layer and a third metal layer which are sequentially grown on the front surface of the P-type crystalline silicon substrate; and a silicon oxide tunneling layer, a polysilicon layer, a SiNx antireflection passivation layer, a first metal layer, a second metal layer and a third metal layer are sequentially grown on the back surface of the P-type crystal silicon substrate.
2. The P-type Topcon back junction cell metallized by an electroplating process according to claim 1, wherein: the front surface of the P-type crystal silicon substrate is provided with a first groove, wherein the P + high-low junction, the first metal layer, the second metal layer and the third metal layer are grown in the first groove in sequence.
3. The P-type Topcon back junction cell metallized by an electroplating process according to claim 1, wherein: and a second groove is formed in the back surface of the P-type crystal silicon substrate, wherein the first metal layer, the second metal layer and the third metal layer are grown in the second groove in sequence.
4. A method of making a P-type Topcon back junction cell of claim 1 metallized by an electroplating process, comprising:
texturing the surface of the P-type crystal silicon substrate;
growing a layer of the silicon oxide tunneling layer on the back surface of the P-type crystal silicon substrate, depositing an amorphous silicon layer on the silicon oxide tunneling layer, doping phosphorus into the amorphous silicon layer, and annealing to obtain a phosphorus-doped polycrystalline silicon layer;
removing the phosphorus-doped polycrystalline silicon layer on the front surface and the edge winding part of the P-type crystalline silicon substrate, and preparing a silicon oxide passivation layer on the front surface of the P-type crystalline silicon substrate;
growing an aluminum oxide passivation layer on the silicon oxide passivation layer, and depositing a SiNx antireflection passivation layer on the aluminum oxide passivation layer and the polysilicon layer;
respectively grooving the front surface and the back surface of the processed P-type crystal silicon substrate, forming a first groove on the front surface, and forming a second groove on the back surface;
carrying out boron diffusion treatment on the first groove, preparing the p + high-low junction, and immersing the p + high-low junction into an active agent;
taking out the P-type crystal silicon substrate, electroplating a first metal layer in the first groove and the second groove to obtain an electroplating sample, and sintering the electroplating sample in a high-temperature furnace;
cleaning after sintering is finished, and electroplating the second metal layer on the first metal layer;
and cleaning after the electroplating is finished, and electroplating the third metal layer on the second metal layer to obtain the P-type Topcon back junction battery metalized by adopting an electroplating process.
5. The method for preparing a P-type Topcon back junction battery metalized by an electroplating process according to claim 4, wherein the method comprises the following steps: the resistivity of the P-type crystal silicon substrate is 0.5-5 omega cm, and the thickness is 80-200 um.
6. The method for manufacturing a P-type Topcon back junction battery metallized by an electroplating process according to claim 4, wherein: in the step of growing a layer of the silicon oxide tunneling layer on the back surface of the P-type crystal silicon substrate, the silicon oxide tunneling layer is made of silicon dioxide, and the silicon oxide tunneling layer is grown on the back surface of the P-type crystal silicon substrate through a thermal oxidation method, a HN03 oxidation method or an atomic layer deposition method, wherein the thickness of the silicon oxide tunneling layer is 0.5-3nm.
7. The method for manufacturing a P-type Topcon back junction battery metallized by an electroplating process according to claim 4, wherein: and in the process of depositing the amorphous silicon layer doped with phosphorus, depositing the amorphous silicon layer doped with phosphorus on the silicon oxide tunneling layer by adopting a magnetron sputtering method, an LPCVD method or a PECVD method.
8. The method according to claim 7, wherein the P-type Topcon back junction battery is metallized by an electroplating process, and the method comprises the following steps: the deposition temperature of the amorphous silicon layer doped with phosphorus is 250-650 ℃; the thickness of the amorphous silicon layer doped with phosphorus is 60-150nm.
9. The method for manufacturing a P-type Topcon back junction battery metallized by an electroplating process according to claim 4, wherein: the SiN deposited on the polysilicon layer x The thickness of the antireflection passivation layer is 60-120nmThe SiN deposited on the aluminum oxide passivation layer x The thickness of the antireflection passivation layer is 60-110nm.
10. The method for preparing a P-type Topcon back junction battery metalized by an electroplating process according to claim 4, wherein the method comprises the following steps: in the step of respectively grooving the front surface and the back surface of the processed P-type crystal silicon substrate, the first groove is formed to the surface of the P-type crystal silicon substrate, the second groove is formed to the surface of the polycrystalline silicon layer, and then the first groove and the second groove are cleaned to remove impurities remained in grooving.
11. The method for preparing a P-type Topcon back junction battery metalized by an electroplating process according to claim 4, wherein the method comprises the following steps: the first metal layer is a Ni metal layer, a Ti metal layer or a Cr metal layer, and the thickness of the first metal layer is 0.1-5 mu m; sending the electroplating sample into a high-temperature furnace protected by inert gas for sintering, wherein the sintering temperature is 200-400 ℃;
the second metal layer is a Cu metal layer, and the thickness of the second metal layer is 5-15 mu m;
the third metal layer is an Ag metal layer, and the weight of the third metal layer is 3-5mg.
12. The method of claim 11, wherein the method comprises the steps of: the first metal layer, the second metal layer and the third metal layer are electroplated into the first groove and/or the second groove by chemical plating or light induction; the widths of the first metal layer, the second metal layer and the third metal layer are +/-3 mu m of the width of the first groove or the width of the second groove.
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| CN116805655B (en) * | 2023-07-26 | 2024-05-31 | 环晟光伏(江苏)有限公司 | Preparation method of TOPCon battery and TOPCon battery prepared by preparation method |
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