CN116525708B - Front-side wide band gap doped combined passivation back contact solar cell and preparation method thereof - Google Patents
Front-side wide band gap doped combined passivation back contact solar cell and preparation method thereof Download PDFInfo
- Publication number
- CN116525708B CN116525708B CN202310814819.0A CN202310814819A CN116525708B CN 116525708 B CN116525708 B CN 116525708B CN 202310814819 A CN202310814819 A CN 202310814819A CN 116525708 B CN116525708 B CN 116525708B
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor
- semiconductor layer
- silicon wafer
- doped polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002161 passivation Methods 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 276
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 125
- 239000010703 silicon Substances 0.000 claims abstract description 125
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 123
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 100
- 229920005591 polysilicon Polymers 0.000 claims abstract description 93
- 238000006243 chemical reaction Methods 0.000 claims abstract description 47
- 230000005641 tunneling Effects 0.000 claims abstract description 47
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 29
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 19
- 239000011574 phosphorus Substances 0.000 claims abstract description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000001301 oxygen Substances 0.000 claims abstract description 9
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 66
- 238000000151 deposition Methods 0.000 claims description 61
- 238000004140 cleaning Methods 0.000 claims description 41
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 41
- 239000007789 gas Substances 0.000 claims description 39
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 37
- 230000008021 deposition Effects 0.000 claims description 37
- 238000000137 annealing Methods 0.000 claims description 28
- 230000008569 process Effects 0.000 claims description 21
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 20
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 20
- 230000007704 transition Effects 0.000 claims description 18
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 16
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- 239000002253 acid Substances 0.000 claims description 14
- 238000011065 in-situ storage Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 13
- 229910000077 silane Inorganic materials 0.000 claims description 13
- 239000001257 hydrogen Substances 0.000 claims description 11
- 229910052739 hydrogen Inorganic materials 0.000 claims description 11
- 230000035484 reaction time Effects 0.000 claims description 10
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 9
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 8
- 229910052786 argon Inorganic materials 0.000 claims description 8
- 239000001569 carbon dioxide Substances 0.000 claims description 8
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 8
- 239000005922 Phosphane Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- 229910000064 phosphane Inorganic materials 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 150000002431 hydrogen Chemical class 0.000 claims description 4
- 235000013842 nitrous oxide Nutrition 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 19
- 238000010521 absorption reaction Methods 0.000 abstract description 17
- 230000003071 parasitic effect Effects 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 357
- 239000010408 film Substances 0.000 description 40
- 238000010586 diagram Methods 0.000 description 13
- 239000000463 material Substances 0.000 description 9
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 9
- 230000009286 beneficial effect Effects 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 239000012459 cleaning agent Substances 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 2
- 229910001195 gallium oxide Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052810 boron oxide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/208—Particular post-treatment of the devices, e.g. annealing, short-circuit elimination
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Energy (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention belongs to the technical field of back contact solar cells, and particularly relates to a front-side wide-bandgap doped combined passivation back contact solar cell and a preparation method thereof, wherein the front-side wide-bandgap doped combined passivation back contact solar cell comprises a silicon wafer, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer arranged on the front side of the silicon wafer; the third semiconductor layer comprises a second tunneling oxide layer and a third doped polysilicon layer which are sequentially arranged from inside to outside, the third doped polysilicon layer is a doped polysilicon layer containing a first doping element and a second doping element, the first doping element is phosphorus, the second doping element comprises any one of carbon and oxygen, and the band gap width of the third doped polysilicon layer is 1.6-2.1eV. The invention can greatly reduce the equipment investment cost, greatly reduce the parasitic absorption of the third semiconductor layer on the front surface of the battery and improve the short-circuit current of the battery while ensuring the passivation effect, thereby improving the conversion efficiency of the battery.
Description
Technical Field
The invention belongs to the technical field of back contact solar cells, and particularly relates to a front-side wide-bandgap doped combined passivation back contact solar cell and a preparation method thereof.
Background
Currently, a back-contact heterojunction solar cell generally needs to prepare a silicon wafer with a polished back and a textured front, then form a first semiconductor layer and a second semiconductor layer on the back of the silicon wafer, and form a third semiconductor layer on the front of the silicon wafer, wherein the third semiconductor layer comprises a front passivation layer and an anti-reflection layer, and the front passivation layer comprises an intrinsic amorphous silicon layer and an N-type doped amorphous or microcrystalline silicon layer. The preparation process flow is longer, and the first semiconductor layer on the back and the third semiconductor layer on the front are an intrinsic amorphous silicon layer and an N-type doped amorphous/microcrystalline silicon layer.
However, since the third semiconductor layer is an intrinsic amorphous silicon layer and an N-type doped amorphous/microcrystalline silicon layer, a good passivation effect is achieved mainly through a large amount of hydrogen, and the hydrogen overflows in a large amount after the temperature exceeds 250 ℃, so that the passivation effect is affected, the intrinsic amorphous silicon layer and the N-type doped amorphous/microcrystalline silicon layer are generally formed by adopting plate type PECVD (plasma enhanced chemical vapor deposition) coating films respectively, the plate type PECVD is formed by adopting radio frequency power starting and low-temperature (about 200 ℃) deposition, the radio frequency power has high requirements on shielding/grounding of a cavity and the like, and plate type PECVD equipment is very expensive, so that the back contact battery has the problems of long process flow, high equipment investment and the like at present. In addition, the band gap width of the amorphous silicon on the front side of the battery is generally between 1.5 and 1.7ev, but the absorption coefficient is very large and is about 10 times that of monocrystalline or polycrystalline silicon, so that parasitic absorption is very large, the absorption and utilization rate of the silicon chip to light is reduced, the short-circuit current of the battery is reduced, and the conversion efficiency of the battery is further reduced.
Disclosure of Invention
The invention aims to overcome the defects that the equipment investment is high, the parasitic absorption of amorphous silicon on the front side of a battery is very large and the conversion efficiency of the battery is reduced due to the fact that a semiconductor layer in a conventional battery structure in the prior art needs to be plated with a plate PECVD film for many times, and provides the front-side wide-band gap doped combined passivation back-contact solar battery and the preparation method thereof.
In order to achieve the above object, in a first aspect, the present invention provides a front-side wide bandgap doped combined passivation back contact solar cell, which includes a silicon wafer, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are disposed on the back side of the silicon wafer; the first semiconductor layer comprises a first tunneling oxide layer and a first doped polysilicon layer which are sequentially arranged from inside to outside, the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon layer which are sequentially arranged from inside to outside, the third semiconductor layer comprises a second tunneling oxide layer and a third doped polysilicon layer which are sequentially arranged from inside to outside, the third doped polysilicon layer is a doped polysilicon layer containing a first doping element and a second doping element, the first doping element is phosphorus, the second doping element comprises any one of carbon and oxygen, and the ratio of the effective doping concentration of the first doping element to the effective doping concentration of the second doping element is 0.5-20:1, a step of; the band gap width of the third doped polysilicon layer is 1.6-2.1eV, the thickness ratio of the third doped polysilicon layer to the first doped polysilicon layer is 2% -10%, and the thickness of the third doped polysilicon layer is 4-15nm.
In some preferred embodiments of the present invention, the third doped polysilicon layer has a bandgap width of 1.7-2.0eV.
In some preferred embodiments of the present invention, the thickness of the third doped polysilicon layer is 5-15nm.
In some preferred embodiments of the present invention, the effective doping concentration of the second doping element in the third doped polysilicon layer is 1e19-4e21 cm -3 The effective doping concentration of the first doping element is 1e19-9e20 cm -3 。
In some preferred embodiments of the present invention, the first doped polysilicon layer and the third doped polysilicon layer are both N-type and the second doped polysilicon layer is P-type.
In some more preferred embodiments of the present invention, the third doped polysilicon layer is a carbon doped N-type doped polysilicon layer.
In some preferred embodiments of the present invention, the first semiconductor layer is provided with a second semiconductor opening area, the back surface of the silicon wafer where the second semiconductor opening area is located is textured, and the front surface of the silicon wafer is textured.
In the invention, a first semiconductor opening area is arranged on the second semiconductor layer, and the first semiconductor opening area and the second semiconductor opening area are arranged at intervals.
In some preferred embodiments of the present invention, the thickness of the first tunneling oxide layer and the second tunneling oxide layer is 0.5-1.25:1, the thickness of the second tunneling oxide layer is 1-3nm.
In some preferred embodiments of the inventionThe effective doping concentration of the first doped polysilicon layer is 1e19-9e20 cm -3 。
In some preferred embodiments of the invention, the back surface of the silicon wafer is divided into a first emitter region, in which the first semiconductor layer is in contact with the silicon wafer, a second emitter region, in which the second semiconductor layer is in contact with the silicon wafer, and a transition region between the first emitter region and the second emitter region, wherein the first semiconductor layer and the second semiconductor layer are arranged in sequence from inside to outside in the transition region. More preferably, the first semiconductor layer and the second semiconductor layer are in direct contact with each other.
In some embodiments of the invention, the combined passivation back contact solar cell further comprises: and the transparent conductive film is arranged on the outer surfaces of the first semiconductor layer or the second semiconductor layer which are respectively positioned on the outermost layer in the first emitter region, the second emitter region and the transition region, and the part of the transparent conductive film in the transition region is provided with an insulating groove.
In some embodiments of the invention, the combined passivation back contact solar cell further comprises: and an anti-reflection layer disposed on an outer surface of the third semiconductor layer.
In some embodiments of the invention, the combined passivation back contact solar cell further comprises: and metal electrodes disposed in the first and second emitter regions and on outer surfaces of the respective transparent conductive films.
In a second aspect, the invention provides a method for preparing a combined passivation back contact solar cell, wherein the combined passivation back contact solar cell is the front-side wide bandgap doped combined passivation back contact solar cell in the first aspect.
The preparation method of the invention comprises the following steps:
s1, providing a silicon wafer;
s2, forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer;
s3, opening the back surface obtained in the step S2, and removing the first semiconductor layer and the mask layer to form a second semiconductor opening area;
s4, cleaning the back surface obtained in the step S3, and removing the residual first semiconductor layer and mask layer in the second semiconductor opening area;
s5, forming a third semiconductor layer on the front surface of the silicon wafer obtained in the S4, and then cleaning to remove the back surface of the silicon wafer for coiling plating; the third semiconductor layer is formed by annealing after tubular PECVD in-situ doping deposition or by doping a first doping element and a second doping element after LPCVD deposition;
And S6, depositing a second semiconductor layer on the back surface of the silicon wafer obtained in the step S5.
In some embodiments of the present invention, in S5, the process of forming the third semiconductor layer by in-situ doping deposition by tube PECVD and annealing includes a first stage and a second stage and annealing.
Preferably, a first gas comprising silane and laughing gas is introduced in the first stage, glow is turned on, and a second tunneling oxide layer is formed by chemical reaction deposition. Preferably, the reaction temperature in the first stage is 400-450 ℃, the reaction pressure is 100-2000mtorr, and the reaction time is 10-60s.
Further preferably, a second stage is then entered, wherein a second gas comprising silane, a first dopant element source, hydrogen, a second dopant element source is introduced, the glow is turned on, and a third doped polysilicon layer is formed by chemical reaction deposition. Preferably, the reaction temperature of the second stage is 400-450 ℃, the reaction pressure is 100-2000mtorr, and the reaction time is 30-200s. Preferably, the second dopant element source gas comprises methane or carbon dioxide and the first dopant element source gas comprises a phosphine.
It is further preferred that annealing is performed after the above-mentioned deposition is completed, the annealing pressure is 2000 mtorr-1 atm, the annealing temperature is 750-900 deg.c, and the annealing time is 5-60min.
In some embodiments of the present invention, in S5, the process of forming the third semiconductor layer by doping the first doping element and the second doping element after the LPCVD deposition includes: firstly, depositing a second tunneling oxide layer and an intrinsic polycrystalline silicon layer; then ion-implanting the first doping element and the second doping element, or then diffusing the first doping element and the second doping element.
In some embodiments of the present invention, in S2, the forming the first semiconductor layer includes: the first tunneling oxide layer is formed by adopting a wet method or a dry method, and then the first doped polysilicon layer is formed by adopting any one of the following modes: the intrinsic polysilicon layer is deposited by LPCVD and then diffused, the intrinsic polysilicon layer is deposited by PECVD and then annealed, the intrinsic polysilicon layer is deposited by PVD and then ion implanted.
In some embodiments of the invention, the depositing of the second semiconductor layer in S6 is performed by plate CVD.
In some embodiments of the invention, the method further comprises the step of post-texturing: providing a silicon wafer with double-sided polishing and cleaning in S1; and S4, cleaning is texturing cleaning, so that texturing is formed in the second semiconductor opening areas on the front surface and the back surface of the silicon wafer at the same time.
In some embodiments of the present invention, the preparation method further includes a step of removing the mask layer: and after the cleaning in the step S4, removing the mask layer in the area except the opening area of the second semiconductor on the back surface through acid cleaning.
In some embodiments of the invention, the method of preparing further comprises: and S5, after the third semiconductor layer is formed, depositing an anti-reflection layer on the front surface of the silicon wafer through tubular PECVD, and then cleaning the silicon wafer to remove the back surface of the silicon wafer.
In some embodiments of the invention, the method of preparing further comprises: s7, etching an opening on the back surface of the silicon wafer obtained in the S6 to form a first semiconductor opening area which is arranged with the second semiconductor opening area at intervals, and then cleaning.
In some embodiments of the invention, the method of preparing further comprises: s8, depositing a transparent conductive film on the back surface of the silicon wafer obtained in the S7.
In some embodiments of the invention, the method of preparing further comprises: s9, etching openings on the surface of a transition region between the second semiconductor opening region and the first semiconductor opening region on the back surface of the silicon wafer obtained in the step S8, and forming an insulating groove between the second semiconductor opening region and the first semiconductor opening region.
In some embodiments of the invention, the method of preparing further comprises: s10, forming metal electrodes on the surfaces of the second semiconductor opening area and the first semiconductor opening area on the back surface of the silicon wafer obtained in the step S9.
The beneficial effects are that:
according to the invention, in the combined passivation back contact battery structure, the second tunneling oxide layer and the third doped polysilicon layer with high band gap width and proper thickness are particularly adopted as the third semiconductor layer, and the third doped polysilicon layer is doped with the second doping element comprising carbon or oxygen in a mode of being matched with the ratio of doped phosphorus to specific effective doping concentration, so that the band gap width of the third doped polysilicon layer is 1.6-2.1eV, and meanwhile, the absorption coefficient of polysilicon is only one tenth of that of amorphous silicon which is conventionally adopted, therefore, parasitic absorption of the third semiconductor layer on the front side of the battery can be greatly reduced, the short circuit current of the battery is improved, and the battery conversion efficiency is improved; meanwhile, the third semiconductor layer with the specific structure is matched with the first semiconductor layer and the second semiconductor layer which are jointly passivated, so that the equipment investment cost can be further reduced, mass production popularization is facilitated, and meanwhile, the battery conversion efficiency is improved. The invention requires that the third doped polysilicon layer is doped with phosphorus and is doped with carbon or oxygen, so that the forbidden bandwidth of the third doped polysilicon layer can be increased, the absorption of the front surface of the battery can be reduced, and the short-circuit current of the battery can be increased; the first doping element and the second doping element are required to meet the specific effective doping concentration ratio, so that the forbidden bandwidth and the passivation effect of the battery can be considered, and the efficiency of the battery can be improved; while under the same conditions, if the ratio of the effective doping concentration is too large, the passivation effect is affected, and if too small, parasitic absorption is increased, thereby reducing the battery efficiency. In the combined passivation structure, if the band gap width of the third doped polysilicon layer in the third semiconductor layer is too large, the front passivation effect is reduced to reduce the open circuit of the battery, and too small, the front parasitic absorption is increased to reduce the short circuit current of the battery; if the thickness ratio of the third doped polysilicon layer to the first doped polysilicon layer in the third semiconductor layer is too large, the front parasitic absorption is increased, so that the current of the battery is reduced, and if the thickness ratio is too small, the front passivation effect is reduced, so that the open-circuit voltage of the battery is reduced; if the thickness of the third doped polysilicon layer in the third semiconductor layer is too large, parasitic absorption is increased, so that short-circuit current of the battery is reduced, the efficiency of the battery is further reduced, and if the thickness is too small, the front passivation effect is reduced, so that open-circuit voltage of the battery is reduced, and the efficiency of the battery is further reduced.
Meanwhile, in the combined passivation back contact solar cell, as the third semiconductor layer does not adopt amorphous silicon, the first semiconductor layer and the third semiconductor layer can be formed by adopting tubular PECVD, plate PECVD is not required, and the equipment cost is greatly reduced. In the prior art, the tubular PECVD generally adopts an intermediate frequency power source for starting, and cannot meet the requirements of a radio frequency power source of the plate-type PECVD on shielding/grounding of a cavity, so that the third semiconductor layer in the prior art is an intrinsic amorphous silicon layer and an N-type doped amorphous/microcrystalline silicon layer, and needs to be formed by adopting the plate-type PECVD.
According to the preparation method, the steps are cooperated, so that the equipment investment cost is greatly reduced while the passivation effect is ensured, the parasitic absorption of the third semiconductor layer on the front side of the battery is greatly reduced, the short-circuit current of the battery is improved, and the conversion efficiency of the battery is improved. The third semiconductor layer is prepared by adopting tubular PECVD, so that the equipment investment cost is greatly reduced; and the preparation of the second semiconductor layer (needing low-temperature preparation) is carried out after the sequential preparation of the first semiconductor layer and the third semiconductor layer (the highest temperature of tubular PECVD preparation exceeds 800 ℃), and the specific steps have at least the following advantages:
In the first aspect, compared with the mode of preparing the first semiconductor layer and the second semiconductor layer and then preparing the third semiconductor layer in the conventional heterojunction battery, the technical problem that the passivation effect is affected because the second semiconductor layer is formed in a plate-type CVD mode, the plate-type CVD deposition temperature is less than 250 ℃, and a large amount of hydrogen atoms overflow can be caused when the temperature is greater than 250 ℃ can be avoided.
In the second aspect, compared with the existing back contact solar cell passivated by double-sided tunneling silicon oxide (the tunneling oxide layer and the doped polycrystalline layer are formed on the front side and the back side at the same time), the method can be beneficial to different requirements of the front side and the back side on the doped polycrystalline layer, not only can the effect of reducing parasitic absorption and improving passivation on the front side be met, but also the special requirements of interface contact (namely interface contact between the transparent conductive film and the first semiconductor layer, which is beneficial to current extraction) and conductive effect on the back side are met; in the back contact solar cell passivated by double-sided tunneling silicon oxide in the prior art, a tunneling oxide layer and a doped polycrystalline layer are formed on the front side and the back side simultaneously, namely a first semiconductor layer and a third semiconductor layer are formed simultaneously, excessive carbon or oxygen element doping in the doped polycrystalline layer can not only improve the band gap width of a film layer and influence interface contact, but also cause the obvious increase and even insulation of the resistivity, and cannot meet the special requirements of interface contact and conductive effect of the back side;
In the back contact solar cell passivated by double-sided tunneling silicon oxide in the prior art, the doped polycrystalline layer formed on the front side and the back side is formed by depositing an intrinsic polycrystalline layer by LPCVD firstly and then forming the doped polycrystalline layer by phosphorus diffusion, wherein the deposition of the intrinsic polycrystalline layer by LPCVD realizes silicon atomic deposition by completely decomposing silane at a high temperature, and the deposition temperature is generally 550-650 ℃; and the carbon doping or oxygen doping needs to use methane or carbon dioxide and other gases, the decomposition temperature of the methane or the carbon dioxide is higher than 900 ℃, and the methane or the carbon dioxide is incompatible with the prior art for simultaneously forming the first semiconductor layer and the third semiconductor layer on the front side and the back side and the LPCVD process adopted. The preparation of the second semiconductor layer is carried out after the first semiconductor layer and the third semiconductor layer are sequentially prepared, so that the preparation of the third semiconductor layer can be compatible with an LPCVD process, and the preparation of the third semiconductor layer can also be carried out by adopting tubular PECVD with lower preparation cost, wherein the tubular PECVD is mainly deposited after gas forms plasma under the action of a power supply, so that the doped deposition of different elements is easier to realize, and the equipment investment cost is greatly reduced.
In addition, the invention can avoid the technical problem that the passivation effect of the second semiconductor layer is affected because the second semiconductor opening area on the back surface of the silicon wafer is formed into a thicker oxide layer due to the high temperature treatment of 800 ℃ at most in the tubular PECVD process of preparing the third doped polysilicon layer with wide band gap on the front surface by particularly cleaning the back surface of the silicon wafer after forming the third semiconductor layer and before depositing the second semiconductor layer.
In the preferred post-texturing preparation method, the specific battery structure can be subjected to texturing cleaning after the second semiconductor opening area is formed, namely, the post-texturing mode is adopted to form the texturing surface on the second semiconductor opening area and the front surface simultaneously, so that the process flow is greatly simplified, the equipment use amount of plate PECVD is reduced, and the equipment investment cost is greatly reduced; preferably, the structure of the back maskless layer is matched, so that the adhesive force of the second semiconductor layer on the first semiconductor layer is greatly improved, the surface cleanliness of the silicon wafer substrate is improved, the yield and stability of products are improved, and the process flow is simplified.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a conventional back contact heterojunction solar cell;
FIG. 2 is a process flow diagram of a combined passivation back contact solar cell made in accordance with example 1 of the present invention;
FIG. 3 is a schematic diagram of the structure of a silicon wafer polished and cleaned in step S1 of the embodiment 1 of the present invention;
FIG. 4 is a schematic diagram of a structure of a first semiconductor layer and a mask layer formed on the back surface of a silicon wafer in step S2 of the embodiment 1 of the present invention;
FIG. 5 is a schematic diagram of a structure of forming a second semiconductor opening region on the back surface of a silicon wafer in step S3 of embodiment 1 of the present invention;
FIG. 6 is a schematic diagram of the structure of a silicon wafer after the etching and cleaning of step S4 in the embodiment 1 of the present invention;
FIG. 7 is a schematic diagram of the structure of the step S5 of the embodiment 1 of the present invention in which a third semiconductor layer and an anti-reflection layer are formed on the front surface of a silicon wafer;
FIG. 8 is a schematic diagram of a structure of a second semiconductor layer formed on the back surface of a silicon wafer in step S6 of the embodiment 1 of the present invention;
FIG. 9 is a schematic diagram of a structure of forming a first semiconductor opening region on the back surface of a silicon wafer in step S7 of embodiment 1 of the present invention;
FIG. 10 is a schematic diagram of the structure of a transparent conductive film deposited on the back surface of a silicon wafer in step S8 of the embodiment 1 of the present invention;
FIG. 11 is a schematic diagram of a mask pattern for forming an insulation trench on the back surface of a silicon wafer in step S9 of embodiment 1 of the present invention;
FIG. 12 is a schematic diagram of the structure of an insulating trench formed on the back surface of a silicon wafer in step S9 of embodiment 1 of the present invention;
fig. 13 is a schematic diagram of a structure of forming a metal electrode on the back surface of a silicon wafer in step S10 of embodiment 1 of the present invention.
Description of the reference numerals
10. The semiconductor device comprises an N-type silicon wafer, 11, a first tunneling oxide layer, 12, a back N-type doped polycrystalline silicon layer, 13, a mask layer, 14, a second tunneling oxide layer, 15, a front N-type doped polycrystalline layer, 16, an anti-reflection layer, 17, an intrinsic amorphous silicon layer, 18, a P-type doped amorphous silicon layer, 19, a transparent conductive film, 20, a mask material, 21 and a metal electrode; 01. a first semiconductor film layer, 02, a second semiconductor film layer, 03, and a third semiconductor film layer.
Detailed Description
In the present disclosure, the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
The endpoints and any values of the ranges disclosed herein are not limited to the precise range or value, and are understood to encompass values approaching those ranges or values. For numerical ranges, one or more new numerical ranges may be found between the endpoints of each range, between the endpoint of each range and the individual point value, and between the individual point value, in combination with each other, and are to be considered as specifically disclosed herein. Wherein the terms "optional" and "optionally" mean either comprising or not comprising (or may not be present).
In the invention, the silicon wafer is used as the inner part, and the other is used as the outer part.
In a first aspect, the invention provides a front-side wide bandgap doped combined passivation back contact solar cell, which comprises a silicon wafer, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are arranged on the back side of the silicon wafer, and the third semiconductor layer is arranged on the front side of the silicon wafer.
The first semiconductor layer comprises a first tunneling oxide layer and a first doped polysilicon layer which are sequentially arranged from inside to outside, the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon layer which are sequentially arranged from inside to outside, and the third semiconductor layer comprises a second tunneling oxide layer and a third doped polysilicon layer which are sequentially arranged from inside to outside.
The third doped polysilicon layer is a doped polysilicon layer containing a first doping element and a second doping element, wherein the first doping element is phosphorus, the second doping element comprises any one of carbon and oxygen, and the effective doping concentration ratio of the first doping element to the second doping element is 0.5-20:1. the band gap width of the third doped polysilicon layer is 1.6-2.1eV, the thickness ratio of the third doped polysilicon layer to the first doped polysilicon layer is 2% -10%, and the thickness of the third doped polysilicon layer is 4-15nm.
The band gap width of the third doped polysilicon layer is 1.6-2.1eV, and specifically may be, for example, 1.6eV,1.7eV,1.8eV,1.9eV,2.0eV,2.1eV, or the like.
In some preferred embodiments of the present invention, the third doped polysilicon layer has a bandgap width of 1.7-2.0eV. Under the preferred scheme, the band gap width of the third doped polysilicon layer is proper, so that the parasitic absorption and passivation effects of the battery with lower front side can be considered, and the improvement of the battery efficiency is facilitated.
In some preferred embodiments of the present invention, the thickness of the third doped polysilicon layer is 5-15nm. Under the preferred scheme, the thickness of the third doped polysilicon layer is proper, and the parasitic absorption and passivation effects of the lower front side of the battery can be considered, so that the efficiency of the battery is improved.
In some preferred embodiments of the present invention, the effective doping concentration of the second doping element in the third doped polysilicon layer is 1e19-4e21 cm -3 The effective doping concentration of the first doping element is 1e19-9e20 cm -3 . Under the preferred scheme, the doping concentration of each doping element of the third doped polysilicon layer is proper, so that the parasitic absorption and passivation effects of the front side of the battery are both considered, and the improvement of the battery efficiency is facilitated.
The third doped polysilicon layer of the invention can be divided into a multi-layer structure or a single-layer structure, the multi-layer structure can be realized by doping concentration step change, and the man skilled in the art can further optimize the invention based on the actual requirement. In the case of a multilayer structure, the parameters are within the above-mentioned ranges for the respective doping concentrations.
In some preferred embodiments of the present invention, the silicon wafer is an N-type silicon wafer, the first doped polysilicon layer and the third doped polysilicon layer are both N-type, and the second doped polysilicon layer is P-type.
In some more preferred embodiments of the present invention, the third doped polysilicon layer is a carbon doped N-type doped polysilicon layer. Under the preferred scheme, the doping solubility and the band gap width can be better controlled, and the short-circuit current density and the battery conversion efficiency can be improved more favorably.
In some preferred embodiments of the present invention, the first semiconductor layer is provided with a second semiconductor opening area, the back surface of the silicon wafer where the second semiconductor opening area is located is textured, and the front surface of the silicon wafer is textured.
In the invention, a first semiconductor opening area is arranged on the second semiconductor layer, and the first semiconductor opening area and the second semiconductor opening area are arranged at intervals. The width Wp of the second semiconductor opening region is preferably 0.3-0.6mm, and the width Wn of the first semiconductor opening region is preferably 0.1-0.3mm.
In some preferred embodiments of the present invention, the thickness of the first tunneling oxide layer and the second tunneling oxide layer is 0.5-1.25:1, the thickness of the second tunneling oxide layer is 1-3nm. Under the preferred scheme, the thickness ratio of the two tunneling oxide layers is proper under the combined passivation structure, the passivation effect of the front side and the back side and the tunneling effect of the back side can be considered, and the open-circuit voltage and the battery efficiency of the battery can be improved more favorably.
In some preferred embodiments of the present invention, the first doped polysilicon layer has an effective doping concentration of 1e19 to 9e20 cm -3 。
In some preferred embodiments of the invention, the back surface of the silicon wafer is divided into a first emitter region, in which the first semiconductor layer is in contact with the silicon wafer, a second emitter region, in which the second semiconductor layer is in contact with the silicon wafer, and a transition region between the first emitter region and the second emitter region, wherein the first semiconductor layer and the second semiconductor layer are arranged in sequence from inside to outside in the transition region. It is understood that the second semiconductor layer is not provided in the first emitter region and the first semiconductor layer is not provided in the second emitter region.
A mask layer may be disposed between the first semiconductor layer and the second semiconductor layer in the transition region, and more preferably, a mask layer is not disposed in direct contact between the first semiconductor layer and the second semiconductor layer in the transition region.
The silicon wafer is a Czochralski monocrystalline silicon wafer or a cast monocrystalline silicon wafer.
In some embodiments of the invention, the combined passivation back contact solar cell further comprises: and the transparent conductive film is arranged on the outer surfaces of the first semiconductor layer or the second semiconductor layer which are respectively positioned on the outermost layer in the first emitter region, the second emitter region and the transition region, and the part of the transparent conductive film in the transition region is provided with an insulating groove. The width Wi of the insulating trench of the present invention is preferably 20 to 120. Mu.m. The insulating trench is such that the resistance between the second semiconductor opening region and the first semiconductor opening region is preferably greater than 1kΩ.
The second doped silicon layer in the second semiconductor layer of the present invention may be a doped amorphous or microcrystalline silicon layer. The thickness and doping concentration of the intrinsic amorphous silicon layer and the second doped silicon layer may be in accordance with the ranges in the prior art. Preferably, the thickness of the intrinsic amorphous silicon layer is 5-15nm, the thickness of the second doped silicon layer is 10-35nm, and the effective doping concentration of the second doped silicon layer is 1e19-4e20 cm -3 。
In some embodiments of the invention, the combined passivation back contact solar cell further comprises: and an anti-reflection layer disposed on an outer surface of the third semiconductor layer. The anti-reflection layer can be silicon oxide, fluoride or silicon nitride, and the thickness is preferably 700-850nm.
In some embodiments of the invention, the combined passivation back contact solar cell further comprises: and metal electrodes disposed in the first and second emitter regions and on outer surfaces of the respective transparent conductive films.
In a second aspect, the invention provides a method for preparing a combined passivation back contact solar cell, wherein the combined passivation back contact solar cell is the front-side wide bandgap doped combined passivation back contact solar cell in the first aspect.
The preparation method of the invention comprises the following steps:
s1, providing a silicon wafer;
s2, forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer;
s3, opening the back surface obtained in the step S2, and removing the first semiconductor layer and the mask layer to form a second semiconductor opening area;
s4, cleaning the back surface obtained in the step S3, and removing the residual first semiconductor layer and mask layer in the second semiconductor opening area;
S5, forming a third semiconductor layer on the front surface of the silicon wafer obtained in the S4, and then cleaning to remove the back surface of the silicon wafer for coiling plating;
and S6, depositing a second semiconductor layer on the back surface of the silicon wafer obtained in the step S5.
In S5, the third semiconductor layer is formed by in-situ doping deposition by tube PECVD and annealing, or by doping the first doping element and the second doping element after LPCVD deposition.
In some embodiments of the present invention, the process of forming the third semiconductor layer by tube PECVD in-situ doped post-deposition annealing includes a first stage and a second stage and annealing.
Preferably, a first gas comprising laughing gas is introduced in the first stage, glow is turned on, and a second tunneling oxide layer is formed by chemical reaction deposition.
More preferably, the reaction temperature in the first stage is 350-450 ℃, the reaction pressure is 100-2000mtorr, and the reaction time is 10-360s.
The invention enters the second stage after the first stage, wherein the second stage can be doped with the first doping element and the second doping element at the same time, or the first doping element is doped after the second doping element is doped, and the first doping element is preferable. In the mode of doping the second doping element and then doping the first doping element, the gas containing the second doping element gas source is introduced in the process of doping the second doping element, the gas containing the first doping element gas source and the second doping element gas source or the gas containing the first doping element gas source but not containing the second doping element gas source can be introduced in the process of doping the first doping element and then doping the first doping element, and preferably, the gas containing the first doping element gas source and the second doping element gas source is introduced, so that the short circuit current density and the battery conversion efficiency are improved more than the gas containing the first doping element gas source and the second doping element gas source.
Further preferably, the second stage is to introduce a second gas comprising silane, a first doping element gas source, hydrogen, argon, and a second doping element gas source, turn on glow, and deposit a third doped polysilicon layer by chemical reaction. In the preferred scheme, two doping elements are doped at the same time, so that the short-circuit current density and the battery conversion efficiency are improved remarkably. The volume flow ratio of the silane to the first doping element gas source to the hydrogen to the argon to the second doping element gas source may be selected according to a conventional range, so long as a required film layer can be formed, for example, the volume flow ratio of the silane to the first doping element gas source to the second doping element gas source to the hydrogen to the argon in the second gas may be preferably 1:0-0.5:0-1:0-5:0-5.
Preferably, the reaction temperature of the second stage is 350-450 ℃, the reaction pressure is 100-2000mtorr, and the reaction time is 30-200s.
Preferably, the second dopant element source gas comprises methane or carbon dioxide and the first dopant element source gas comprises a phosphine.
The annealing is performed after the completion of the deposition in the second stage, and it is further preferable that the annealing pressure is 2000 mtorr-1 atm, the annealing temperature is 750-900 deg.c, and the annealing time is 5-70min.
In some embodiments of the present invention, in S5, the process of forming the third semiconductor layer by doping the first doping element and the second doping element after the LPCVD deposition includes: firstly, depositing a second tunneling oxide layer and an intrinsic polycrystalline silicon layer; then ion-implanting the first doping element and the second doping element, or then diffusing the first doping element and the second doping element. The person skilled in the art can choose the corresponding process parameters in the doping of the first doping element and the second doping element after the LPCVD deposition according to the desired formation of the third semiconductor layer.
The method for forming the first semiconductor layer and the mask layer in S2 of the present invention may be any method in the prior art. For example, in some embodiments of the present invention, in S2, the forming the first semiconductor layer includes: the first tunneling oxide layer is formed by adopting a wet method or a dry method, and then the first doped polysilicon layer is formed by adopting any one of the following modes: the intrinsic polysilicon layer is deposited by LPCVD and then diffused, the tube PECVD in-situ doped deposition and then annealed, the PVD in-situ doped deposition and then annealed, and the intrinsic polysilicon layer is deposited by LPCVD and then ion implanted. For example, the mask layer is formed by PECVD deposition.
The first tunneling oxide layer is formed by a wet method or a dry method, wherein the wet method comprises an ozone oxidation method, a nitric acid oxidation method, an ozone water oxidation method and the like, and the dry method comprises a thermal oxidation method, a PECVD in-situ oxidation method and the like, which are all the prior art and are not described herein again.
In S2, the mask layer may be finally left or removed, preferably removed. The mask layer can be at least one of silicon nitride, silicon oxynitride and silicon oxide, and the thickness is preferably 50-200nm.
In some embodiments of the invention, the method further comprises the step of post-texturing: providing a silicon wafer with double-sided polishing and cleaning in S1; and S4, cleaning is texturing cleaning, so that texturing is formed in the second semiconductor opening areas on the front surface and the back surface of the silicon wafer at the same time.
In some embodiments of the present invention, the preparation method further includes a step of removing the mask layer: after the cleaning in S4, the mask layer in the area outside the opening area of the second semiconductor on the back surface is removed by acid cleaning (preferably hydrofluoric acid cleaning).
In the present invention S3, the opening may be etched by laser or mask, so long as the second semiconductor opening region can be formed. The laser can be ultraviolet or green laser, and the pulse width is less than 10ns.
In some embodiments of the invention, the method of preparing further comprises: and S5, after the third semiconductor layer is formed, depositing an anti-reflection layer on the front surface of the silicon wafer through tubular PECVD, and then cleaning the silicon wafer to remove the back surface of the silicon wafer.
In some embodiments of the invention, the depositing of the second semiconductor layer in S6 is performed by plate CVD.
In some embodiments of the invention, the method of preparing further comprises: s7, etching an opening on the back surface of the silicon wafer obtained in the S6 to form a first semiconductor opening area which is arranged with the second semiconductor opening area at intervals, and then cleaning.
In S7, the etching opening may be etched by using a laser or a mask, where the laser is an ultraviolet laser or a green laser, and the pulse width is preferably less than 50ns.
In some embodiments of the invention, the method of preparing further comprises: s8, depositing a transparent conductive film on the back surface of the silicon wafer obtained in the S7. The deposited transparent conductive film may employ, for example, a physical vapor deposition technique (PVD) or an activated plasma deposition technique (RPD). The transparent conductive film thickness is preferably 40 to 80nm. The material of the transparent conductive film may be a thin film of indium oxide doped with tin oxide, titanium oxide, zinc oxide, or gallium oxide, or a thin film of zinc oxide doped with aluminum oxide, gallium oxide, or boron oxide.
In some embodiments of the invention, the method of preparing further comprises: s9, etching openings on the surface of a transition region between the second semiconductor opening region and the first semiconductor opening region on the back surface of the silicon wafer obtained in the step S8, and forming an insulating groove between the second semiconductor opening region and the first semiconductor opening region.
The etching opening in S9 may adopt a mask etching manner, where the mask etching process includes: the method comprises the steps of printing or ink-jet printing acid-resistant mask materials (such as acid-resistant ink) on the back surface of a silicon wafer to form an opening area of an insulating groove pattern, cleaning by an acid solution to remove a transparent conductive film in the opening area of the acid-resistant mask materials, and then cleaning by a cleaning agent to remove the acid-resistant mask materials, wherein the acid solution can be at least one of hydrochloric acid, sulfuric acid and nitric acid, the cleaning agent can be at least one of alkaline cleaning agent and oxidizing agent, and the alkaline cleaning agent can be at least one of sodium hydroxide, potassium hydroxide and the like.
In some embodiments of the invention, the method of preparing further comprises: s10, forming metal electrodes on the surfaces of the second semiconductor opening area and the first semiconductor opening area on the back surface of the silicon wafer obtained in the step S9. The metal electrode may be formed using screen printing or electroplating techniques. The second semiconductor opening region is different in polarity from the corresponding metal electrode in the first semiconductor opening region, thereby forming a second emitter and a first emitter.
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
Example 1
A front side wide bandgap doped, jointly passivated back contact solar cell prepared by the steps shown in fig. 2:
s1, as shown in FIG. 3, the double-sided polishing and cleaning of the N-type monocrystalline silicon piece 10.
S2, as shown in FIG. 4, a first semiconductor layer and a mask layer 13 are formed on the back surface of the silicon wafer 10, wherein the first semiconductor layer comprises a first tunneling oxide layer 11 and a back surface N-type doped polysilicon layer 12. The first tunneling oxide layer 11 is formed by a dry method, and the back N-doped polysilicon layer 12 is formed by LPCVD deposited intrinsic polysilicon and then diffused. The mask layer 13 is formed by PECVD deposition. The thickness of the first tunneling oxide layer 11 is 1.7nm, the thickness of the back N-type doped polysilicon layer 12 is 120nm, and the effective doping concentration of the back N-type doped polysilicon layer 12 is 1e 19-6 e20 cm -3 . The mask layer 13 is silicon nitride and has a thickness of 70nm.
S3, as shown in FIG. 5, an opening is etched on the back surface of the silicon wafer 10 by adopting a laser mode, so as to form a second semiconductor opening area Wp. The width of the second semiconductor opening area Wp is 0.5mm, and the mask layer 13, the back N-type doped polysilicon layer 12 and the first tunneling oxide layer 11 in the second semiconductor opening area Wp are etched away. The laser is 532nm laser with a pulse width of 1ns.
S4, as shown in FIG. 6, removing the mask layer 13, the back N-type doped polysilicon layer 12 and the first tunneling oxide layer 11 remained in the second semiconductor opening area Wp through texturing cleaning, forming textured surfaces on the second semiconductor opening areas Wp on the front and back of the silicon wafer, and then removing the mask layer 13 outside the second semiconductor opening area Wp on the back of the silicon wafer through hydrofluoric acid cleaning.
S5, as shown in FIG. 7, a third semiconductor layer and an anti-reflection layer 16 are formed on the front surface of the silicon wafer 10, wherein the third semiconductor layer is formed on the front surface of the silicon waferThe conductor layer comprises a second tunneling oxide layer 14 and a carbon doped front side N-type doped polycrystalline layer 15, and the third semiconductor layer is formed by tube PECVD in-situ doped deposition and post annealing, and comprises: in the first stage, laughing gas is introduced, glow is started, a second tunneling oxide layer 14 is formed through chemical reaction, the reaction temperature in the first stage is 380 ℃, the reaction pressure is 1000mtorr, the time is 120s, and the thickness of the second tunneling oxide layer 14 is 2nm; then entering a second stage, wherein the volume flow ratio of the second stage is 1:0.2:0.5:1:2, starting glow, and forming a carbon-doped front N-type doped polycrystalline layer 15 through chemical reaction, wherein the reaction temperature of the second stage is 420 ℃, the reaction time is 100s, the reaction pressure is 1000mtorr, and the thickness of the carbon-doped front N-type doped polycrystalline layer 15 is 8nm. Annealing by a low-pressure annealing furnace after the deposition is finished, wherein the annealing pressure is 2000mtorr, the annealing temperature is 850 ℃, the annealing time is 20min, and the effective doping concentration of annealed carbon is 2e20cm -3 The effective doping concentration of phosphorus is 2e20cm -3 The band gap width was 1.9eV. And then depositing a silicon nitride layer on the front surface of the silicon wafer through tubular PECVD, wherein the thickness of the silicon nitride layer is 700nm. And then cleaning to remove the back surface of the silicon wafer.
S6, as shown in FIG. 8, a second semiconductor layer is deposited on the back surface of the silicon wafer 10 by a plate-type Plasma Enhanced Chemical Vapor Deposition (PECVD) technology, wherein the second semiconductor layer comprises an intrinsic amorphous silicon layer 17 and a P-type doped amorphous silicon layer 18. The thickness of the intrinsic amorphous silicon layer 17 is 5nm, the thickness of the P-type doped amorphous silicon layer 18 is 10nm, and the boron doping concentration in the P-type doped amorphous silicon layer 18 is 5e19cm -3 。
S7, as shown in FIG. 9, the back surface of the silicon wafer 10 is etched with an opening by a laser method to form a first semiconductor opening area Wn which is arranged at intervals with the second semiconductor opening area Wp, and then the silicon wafer is cleaned. And the width of the first semiconductor opening area Wn is 0.3mm, and the second semiconductor layer on the upper surface of the first semiconductor opening area Wn is etched and cleaned. The laser is ultraviolet laser, and the pulse width is 1ns.
S8, as shown in FIG. 10, a transparent conductive film 19 is deposited on the back surface of the silicon wafer 10 by adopting a Physical Vapor Deposition (PVD) technology, the thickness of the transparent conductive film 19 is 50nm, and the material of the transparent conductive film 19 is a tin oxide doped indium oxide film.
S9, as shown in FIG. 11 and FIG. 12, an opening is etched on the surface of a transition area Wg on the back surface of the silicon wafer 10 by a mask etching method, so as to form an insulating trench Wi between the first semiconductor and the second semiconductor. The width Wi is 80 mu m, and the resistance between the first semiconductor and the second semiconductor after etching is larger than 1KΩ. The mask etching formation conditions include: the acid-resistant masking material 20 is printed on the back of the silicon wafer 10 to form an opening area of an insulation groove pattern, the transparent conductive film 19 in the opening area of the acid-resistant ink material is removed through acid solution cleaning, then the acid-resistant masking material is removed through ink cleaning agent cleaning, the acid solution is hydrochloric acid, and the cleaning agent is sodium hydroxide.
S10, forming a metal electrode 21 on the surface of a first semiconductor opening area Wn on the back of the silicon wafer 10 by adopting a screen printing technology, forming a metal electrode 21 on the surface of a second semiconductor opening area Wp, wherein the polarities of the second semiconductor opening area and the corresponding metal electrode in the first semiconductor opening area are different. The structure of the resulting combined passivated back contact solar cell is shown in fig. 13.
Example 2
With reference to example 1, unlike example 1, the front side N-type doped polycrystalline layer 15 in the third semiconductor layer in S5 is an oxygen-doped N-type doped polycrystalline layer with an effective doping concentration of 1e19cm -3 The band gap width was 1.7eV. In the corresponding second stage of in-situ doped deposition of the third semiconductor layer by tubular PECVD, silane, phosphane, carbon dioxide, hydrogen and argon are introduced, and the volume flow ratio of the silane to the carbon dioxide is 1:0.2, the other gas flow ratio is unchanged.
Example 3
With reference to example 1, unlike example 1, the second tunneling oxide layer and the intrinsic polysilicon layer were deposited by LPCVD (low pressure chemical vapor deposition), and then formed by ion implantation to dope phosphorus and carbon, and the thickness and doping of the third semiconductor layer obtained were the same as in example 1.
Example 4
With reference to example 1, unlike example 1, the S5 third semiconductor layer was formed by depositing a second tunnel oxide layer and an intrinsic polysilicon layer by LPCVD, and then by diffusion doping with phosphorus and carbon, and the thickness and doping of the obtained third semiconductor layer were the same as those of example 1.
Example 5
With reference to example 1, unlike example 1, in S5, the band gap width of the front side N-doped polycrystalline layer doped with carbon is controlled to be 2.1eV, and the ratio of the effective doping concentration of phosphorus to the effective doping concentration of carbon is controlled to be 0.5:1, correspondingly adjusting the technological parameters to meet the parameters: in the second stage, silane, phosphane, methane, hydrogen and argon are introduced, wherein the volume flow ratio of the silane to the methane is 1:1, the other gas flow ratio is unchanged.
Example 6
With reference to example 1, unlike example 1, in S5, the thickness of the second tunnel oxide layer is adjusted such that the thicknesses of the first tunnel oxide layer and the second tunnel oxide layer are 0.57:1, correspondingly adjusting the technological parameters to meet the parameters: the reaction time in the first stage is 300s, the thickness of the second tunneling oxide layer 14 is 3nm, and the rest parameters are unchanged.
Example 7
With reference to example 1, unlike example 1, the second stage in S5 does not use simultaneous doping of phosphorus and carbon, but uses a method of doping carbon first and then doping phosphorus, and each doping concentration is the same as that in example 1, and the process of doping carbon first and then doping phosphorus includes:
the second stage is divided into two steps, wherein the volume flow ratio of the first step is 1:0.5:1:2, starting glow, forming a carbon-doped front polycrystalline layer through chemical reaction, wherein the reaction temperature of the second stage is 420 ℃, the reaction time is 50s, the reaction pressure is 1000mtorr, the thickness of the carbon-doped front polycrystalline layer is 4nm, and the volume flow ratio of the second step is 1:0.2:1:2, starting glow, and forming a phosphorus-doped front N-type doped polycrystalline layer through chemical reaction, wherein the reaction temperature of the second stage is 420 ℃, the reaction time is 50s, the reaction pressure is 1000mtorr, and the thickness of the phosphorus-doped front N-type doped polycrystalline layer 15 is 4nm.
Example 8
With reference to example 1, unlike example 1, the effective doping concentration of carbon was adjusted so that the ratio of the effective doping concentration of phosphorus to that of carbon was 0.05:1, a band gap width of 1.6eV; to meet the corresponding adjustment process parameters of the parameters: the ratio of the inlet volume flow rate of the second stage is 1:0.2:0.05:1:2, silane, phosphane, methane, hydrogen and argon, and the rest parameters are unchanged.
Comparative example 1
The conventional back contact heterojunction cell with the structure as shown in fig. 1 is obtained by the following steps:
s101, providing a silicon wafer 10 with a single-sided texturing and polishing structure;
s102, a first semiconductor film 01 and a mask layer 13 are plated on the back of the silicon wafer in sequence, wherein the first semiconductor film 01 is formed by adopting a plate PECVD mode, the first semiconductor film 01 comprises an intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer (the effective doping concentration is the same as that of the embodiment 1), and the thicknesses are the same as that of the embodiment 1 respectively. The mask layer 13 is the same as in example 1;
s103, forming a second semiconductor opening area by laser opening on the back surface of the silicon wafer 10 and removing the mask layer 13 and part of the first semiconductor film layer 01;
s104, cleaning the silicon wafer 10 to remove the residual first semiconductor film 01 in the second semiconductor opening area;
S105, forming a second semiconductor film 02 on the back surface of the silicon wafer 10, wherein the second semiconductor film 02 is formed by adopting a plate PECVD mode, the second semiconductor film 02 comprises an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer, and the structural parameters such as the thickness of each layer of the second semiconductor film 02 are the same as those of the embodiment 1;
s106, forming a third semiconductor film 03 on the front surface, wherein the third semiconductor film 03 comprises a front passivation layer and an anti-reflection layer 16, the front passivation layer and the anti-reflection layer are formed in a plate PECVD mode, the front passivation layer comprises an intrinsic amorphous silicon layer and an N-type doped amorphous/microcrystalline silicon layer (without carbon or oxygen), the thickness of the intrinsic amorphous silicon layer is 6nm, the effective doping concentration and the thickness of phosphorus in the N-type doped amorphous silicon layer are the same as those in the embodiment 1, and the anti-reflection layer 16 is the same as that in the embodiment 1;
s107, forming first semiconductor opening areas alternately arranged with the second semiconductor opening areas through laser openings on the back surface of the silicon wafer 10; the second semiconductor opening region and the first semiconductor opening region have the same width as in embodiment 1;
s108, cleaning the silicon wafer 10, and removing the mask layer 13 in the first semiconductor opening area;
s109, depositing a transparent conductive film 19 on the back surface of the silicon wafer 10; the transparent conductive film 19 is the same as in example 1;
S110, forming an insulating groove between the first semiconductor opening area and the second semiconductor opening area by means of laser or etching; the width of the insulation groove is the same as that of the embodiment 1;
s111, a metal electrode 21 is formed on the first semiconductor opening region and the second semiconductor opening region of the silicon wafer 10.
Comparative example 2
With reference to example 1, unlike example 1, the third semiconductor layer was formed by depositing intrinsic amorphous silicon and N-type doped microcrystalline silicon by plate-type PECVD, the intrinsic amorphous silicon having a thickness of 6nm, and the N-type doped microcrystalline silicon having a thickness, phosphorus doping concentration, and carbon doping concentration, respectively, as in example 1.
Comparative example 3
The process of example 1 was performed as described in example 1, except that the N-type doped polysilicon layer in the third semiconductor layer was not doped with carbon, and the band gap width was 1.0 to 1.2. 1.2 eV.
Comparative example 4
With reference to example 1, unlike example 1, the effective doping concentration of carbon was adjusted so that the ratio of the effective doping concentration of phosphorus to that of carbon was 10:1, a band gap width of 2.2eV; to meet the corresponding adjustment process parameters of the parameters: the ratio of the inlet volume flow rate of the second stage is 1:0.2:5:1:2, silane, phosphane, methane, hydrogen and argon, and the rest parameters are unchanged.
Test case
The back contact batteries of the above examples and comparative examples were subjected to the test shown in table 1, and the results are shown in table 1.
TABLE 1
Remarks: the equipment investment amount is calculated with comparative example 1 as a reference.
As can be seen from the test results, compared with the comparative example, the embodiment of the invention can be beneficial to improving the short-circuit current density and the battery conversion efficiency at a higher level under the condition of reducing the equipment cost. While the comparative examples are either high in equipment cost or low in the combination of short circuit current density and battery conversion efficiency.
Further, as can be seen from the embodiments 1 and 2, the preferred embodiment 1 scheme of carbon doping is more beneficial to improving the short-circuit current density and the battery conversion efficiency. As can be seen from the embodiment 1 and the embodiments 3 to 4, the scheme of the preferred embodiment 1 adopting the tubular PECVD process is more beneficial to reduce the equipment cost, and further improves the short-circuit current density and the battery conversion efficiency. As can be seen from examples 1 and 5, the third doped polysilicon layer has a suitable preferred bandgap width, which is more beneficial to improving the conversion efficiency of the battery. As can be seen from examples 1 and 6, the second tunneling oxide layer has a suitable thickness ratio, which is more beneficial to improving the short-circuit current density and the battery conversion efficiency. It can be seen from examples 1 and 7 that the mode of doping carbon and phosphorus simultaneously according to the present invention is more advantageous to significantly improve the short-circuit current density and the battery conversion efficiency while reducing the equipment cost. It can be seen from examples 1 and 8 that the concentrations of the two doping elements are suitable, which is more advantageous for improving the short-circuit current density and the battery conversion efficiency.
The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the scope of the technical idea of the invention, a number of simple variants of the technical solution of the invention are possible, including combinations of the individual technical features in any other suitable way, which simple variants and combinations should likewise be regarded as being disclosed by the invention, all falling within the scope of protection of the invention.
Claims (12)
1. The front-side wide band gap doped combined passivation back contact solar cell comprises a silicon wafer, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are arranged on the back side of the silicon wafer; the first semiconductor layer comprises a first tunneling oxide layer and a first doped polysilicon layer which are sequentially arranged from inside to outside, and the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon layer which are sequentially arranged from inside to outside, and the semiconductor device is characterized in that the third semiconductor layer comprises a second tunneling oxide layer and a third doped polysilicon layer which are sequentially arranged from inside to outside, the third doped polysilicon layer is a doped polysilicon layer containing a first doping element and a second doping element, the first doping element is phosphorus, the second doping element comprises any one of carbon and oxygen, and the effective doping concentration ratio of the first doping element to the second doping element is 0.5-20:1, the effective doping concentration of the second doping element in the third doped polysilicon layer is 1e19-4e21 cm -3 The effective doping concentration of the first doping element is 1e19-9e20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The band gap width of the third doped polysilicon layer is 1.6-2.1eV, the thickness ratio of the third doped polysilicon layer to the first doped polysilicon layer is 2% -10%, and the thickness of the third doped polysilicon layer is 4-15nm.
2. The combined passivation and back contact solar cell according to claim 1, wherein the band gap width of the third doped polysilicon layer is 1.7-2.0eV and/or the thickness of the third doped polysilicon layer is 5-15nm.
3. The combined passivation back contact solar cell of claim 1, wherein the silicon wafer is an N-type silicon wafer, the first doped polysilicon layer and the third doped polysilicon layer are both N-type, and the second doped polysilicon layer is P-type; and/or
The first semiconductor layer is provided with a second semiconductor opening area, the back surface of the silicon wafer where the second semiconductor opening area is located is textured, and the front surface of the silicon wafer is textured; the second semiconductor layer is provided with a first semiconductor opening area, and the first semiconductor opening area and the second semiconductor opening area are arranged at intervals.
4. The combination passivation back contact solar cell of claim 1, wherein the third doped polysilicon layer is a carbon doped N-type doped polysilicon layer, and/or
The thickness of the first tunneling oxide layer and the second tunneling oxide layer is 0.5-1.25:1, the thickness of the second tunneling oxide layer is 1-3nm, and the effective doping concentration of the first doped polysilicon layer is 1e19-9e20 cm -3 。
5. The combined passivation and back contact solar cell according to claim 1, wherein the back side of the silicon wafer is divided into a first emitter region where the first semiconductor layer is in contact with the silicon wafer, a second emitter region where the second semiconductor layer is in contact with the silicon wafer, and a transition region between the first emitter region and the second emitter region, wherein the first semiconductor layer and the second semiconductor layer are arranged in sequence from inside to outside in the transition region and the first semiconductor layer is in direct contact with the second semiconductor layer.
6. The jointly passivated back contact solar cell of claim 5 further comprising:
the transparent conductive film is arranged on the outer surfaces of the first semiconductor layer or the second semiconductor layer which are respectively positioned on the outermost layer in the first emitter region, the second emitter region and the transition region, and the part of the transparent conductive film in the transition region is provided with an insulation groove;
an anti-reflection layer provided on an outer surface of the third semiconductor layer;
And metal electrodes disposed in the first and second emitter regions and on outer surfaces of the respective transparent conductive films.
7. A method for preparing a combined passivation back contact solar cell, wherein the combined passivation back contact solar cell is a front side wide bandgap doped combined passivation back contact solar cell as defined in any one of claims 1 to 6, and the method comprises the steps of:
s1, providing a silicon wafer;
s2, forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer;
s3, opening the back surface obtained in the step S2, and removing the first semiconductor layer and the mask layer to form a second semiconductor opening area;
s4, cleaning the back surface obtained in the step S3, and removing the residual first semiconductor layer and mask layer in the second semiconductor opening area;
s5, forming a third semiconductor layer on the front surface of the silicon wafer obtained in the S4, and then cleaning to remove the back surface of the silicon wafer for coiling plating; the third semiconductor layer is formed by annealing after tubular PECVD in-situ doping deposition or by doping a first doping element and a second doping element after LPCVD deposition;
and S6, depositing a second semiconductor layer on the back surface of the silicon wafer obtained in the step S5.
8. The method of claim 7, wherein in S5, the forming the third semiconductor layer by in-situ doped deposition and annealing by tube PECVD includes a first stage and a second stage and annealing:
A first gas comprising laughing gas is introduced in the first stage, glow is started, a second tunneling oxide layer is formed through chemical reaction deposition, the reaction temperature in the first stage is 350-450 ℃, the reaction pressure is 100-2000mtorr, and the reaction time is 10-360s;
then entering a second stage, wherein a second gas comprising silane, a first doping element gas source, hydrogen, argon and a second doping element gas source is introduced into the second stage, glow is started, a third doping polysilicon layer is formed through chemical reaction deposition, the reaction temperature of the second stage is 350-450 ℃, the reaction pressure is 100-2000mtorr, and the reaction time is 30-200s; the second doping element gas source comprises methane or carbon dioxide, and the first doping element gas source comprises phosphane;
annealing is carried out after the deposition is finished, the annealing pressure is 2000 mtorr-1 atm, the annealing temperature is 750-900 ℃, and the annealing time is 5-70min.
9. The method of claim 7, wherein in S5, the process of forming the third semiconductor layer by doping the first doping element and the second doping element after the LPCVD deposition comprises: firstly, depositing a second tunneling oxide layer and an intrinsic polycrystalline silicon layer; then ion-implanting the first doping element and the second doping element, or then diffusing the first doping element and the second doping element.
10. The method of claim 7, wherein in S2, the forming the first semiconductor layer comprises: the first tunneling oxide layer is formed by adopting a wet method or a dry method, and then the first doped polysilicon layer is formed by adopting any one of the following modes: depositing an intrinsic polycrystalline silicon layer by LPCVD, then diffusing, performing in-situ doping deposition by tubular PECVD, performing in-situ doping deposition by PVD, then performing in-situ doping deposition, then performing annealing, and performing ion implantation after depositing the intrinsic polycrystalline silicon layer by LPCVD; and/or
The deposition of the second semiconductor layer in S6 is performed by means of plate CVD.
11. The method of manufacturing according to claim 7, further comprising the step of post-texturing: providing a silicon wafer with double-sided polishing and cleaning in S1; the cleaning in the step S4 is texturing cleaning, so that texturing is formed in the second semiconductor opening areas on the front and back sides of the silicon wafer at the same time; and/or
The preparation method further comprises the step of removing the mask layer: and after the cleaning in the step S4, removing the mask layer in the area except the opening area of the second semiconductor on the back surface through acid cleaning.
12. The method of manufacturing according to claim 7, further comprising:
S5, after the third semiconductor layer is formed, depositing an anti-reflection layer on the front surface of the silicon wafer through tubular PECVD, and then cleaning the silicon wafer to remove the back surface of the silicon wafer;
s7, etching an opening on the back surface of the silicon wafer obtained in the S6 to form a first semiconductor opening area which is arranged at intervals with the second semiconductor opening area, and then cleaning;
s8, depositing a transparent conductive film on the back surface of the silicon wafer obtained in the S7;
s9, etching openings on the surface of a transition region between the second semiconductor opening region and the first semiconductor opening region on the back surface of the silicon wafer obtained in the step S8, and forming an insulating groove between the second semiconductor opening region and the first semiconductor opening region;
s10, forming metal electrodes on the surfaces of the second semiconductor opening area and the first semiconductor opening area on the back surface of the silicon wafer obtained in the step S9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310814819.0A CN116525708B (en) | 2023-07-05 | 2023-07-05 | Front-side wide band gap doped combined passivation back contact solar cell and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310814819.0A CN116525708B (en) | 2023-07-05 | 2023-07-05 | Front-side wide band gap doped combined passivation back contact solar cell and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116525708A CN116525708A (en) | 2023-08-01 |
| CN116525708B true CN116525708B (en) | 2023-09-12 |
Family
ID=87392600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310814819.0A Active CN116525708B (en) | 2023-07-05 | 2023-07-05 | Front-side wide band gap doped combined passivation back contact solar cell and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116525708B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116759473B (en) * | 2023-08-17 | 2023-11-10 | 福建金石能源有限公司 | Back contact battery capable of reducing back parasitic absorption and preparation method thereof |
| CN117117044B (en) * | 2023-10-24 | 2024-01-09 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery and primary annealing preparation method thereof |
| CN117577697B (en) * | 2024-01-16 | 2024-05-03 | 金阳(泉州)新能源科技有限公司 | Back contact battery with specific front passivation structure and preparation method and application thereof |
| CN117577709B (en) * | 2024-01-19 | 2024-03-29 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery, preparation method thereof and battery assembly |
| CN117650188B (en) * | 2024-01-29 | 2024-06-04 | 天合光能股份有限公司 | Solar cell, preparation method thereof, photovoltaic module and photovoltaic system |
| CN117855345B (en) * | 2024-03-04 | 2024-05-31 | 国电投新能源科技有限公司 | Preparation method of back contact heterojunction solar cell and heterojunction solar cell |
| CN117936652A (en) * | 2024-03-14 | 2024-04-26 | 金阳(泉州)新能源科技有限公司 | Preparation method of back contact battery with continuous plating back film |
| CN118073478A (en) * | 2024-04-19 | 2024-05-24 | 金阳(泉州)新能源科技有限公司 | Preparation method of back contact battery and back contact battery |
| CN118156343A (en) * | 2024-05-10 | 2024-06-07 | 金阳(泉州)新能源科技有限公司 | Back contact battery capable of greatly reducing electric leakage, manufacturing method thereof and photovoltaic module |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108321241A (en) * | 2018-01-05 | 2018-07-24 | 中山大学 | A kind of silicon/crystalline silicon heterogenous joint solar cell of back contacts and preparation method |
| CN108666393A (en) * | 2018-07-16 | 2018-10-16 | 英利能源（中国）有限公司 | The preparation method and solar cell of solar cell |
| CN114068729A (en) * | 2021-11-23 | 2022-02-18 | 浙江爱旭太阳能科技有限公司 | Double-sided back contact solar cell and back structure thereof |
| CN114497241A (en) * | 2021-10-27 | 2022-05-13 | 天合光能股份有限公司 | Solar cell with passivated contact |
| WO2022134991A1 (en) * | 2020-12-23 | 2022-06-30 | 泰州隆基乐叶光伏科技有限公司 | Solar cell and production method, and photovoltaic module |
| CN115207137A (en) * | 2022-09-16 | 2022-10-18 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery and preparation method thereof |
| CN115621333A (en) * | 2022-11-22 | 2023-01-17 | 金阳(泉州)新能源科技有限公司 | Back contact solar cell passivated by double-sided tunneling silicon oxide and preparation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI580058B (en) * | 2016-10-26 | 2017-04-21 | 財團法人工業技術研究院 | Solar cell |
-
2023
- 2023-07-05 CN CN202310814819.0A patent/CN116525708B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108321241A (en) * | 2018-01-05 | 2018-07-24 | 中山大学 | A kind of silicon/crystalline silicon heterogenous joint solar cell of back contacts and preparation method |
| CN108666393A (en) * | 2018-07-16 | 2018-10-16 | 英利能源（中国）有限公司 | The preparation method and solar cell of solar cell |
| WO2022134991A1 (en) * | 2020-12-23 | 2022-06-30 | 泰州隆基乐叶光伏科技有限公司 | Solar cell and production method, and photovoltaic module |
| CN114497241A (en) * | 2021-10-27 | 2022-05-13 | 天合光能股份有限公司 | Solar cell with passivated contact |
| CN114068729A (en) * | 2021-11-23 | 2022-02-18 | 浙江爱旭太阳能科技有限公司 | Double-sided back contact solar cell and back structure thereof |
| CN115207137A (en) * | 2022-09-16 | 2022-10-18 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery and preparation method thereof |
| CN115621333A (en) * | 2022-11-22 | 2023-01-17 | 金阳(泉州)新能源科技有限公司 | Back contact solar cell passivated by double-sided tunneling silicon oxide and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116525708A (en) | 2023-08-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN116525708B (en) | Front-side wide band gap doped combined passivation back contact solar cell and preparation method thereof | |
| CN111029438B (en) | Preparation method of N-type passivated contact solar cell | |
| CN115621333B (en) | Back contact solar cell passivated by double-sided tunneling silicon oxide and preparation method thereof | |
| CN112490304A (en) | Preparation method of high-efficiency solar cell | |
| CN117117044B (en) | Combined passivation back contact battery and primary annealing preparation method thereof | |
| CN117577697B (en) | Back contact battery with specific front passivation structure and preparation method and application thereof | |
| CN112542521A (en) | P-type back localized doped cell and preparation method thereof | |
| CN112670352B (en) | Passivation structure applied to contact passivation battery and preparation method thereof | |
| CN115832069A (en) | Passivation contact structure, solar cell, preparation method and photovoltaic module | |
| CN115332366A (en) | Back passivation contact heterojunction solar cell and preparation method thereof | |
| CN111048625B (en) | Preparation method of passivated contact P-type battery | |
| CN114823973A (en) | P-type back contact solar cell and preparation method thereof | |
| CN115411151A (en) | Novel solar cell and manufacturing method thereof | |
| CN117133834A (en) | Short-process preparation method and application of combined passivation back contact battery | |
| CN116666479B (en) | Efficient selective emitter crystalline silicon battery with double-sided power generation and preparation method thereof | |
| CN117199186A (en) | Manufacturing method of N-TOPCON battery | |
| CN112466960A (en) | Solar cell structure and preparation method thereof | |
| CN116314471A (en) | Preparation method of rear SE structure | |
| CN115377226A (en) | Selective emitter structure, preparation method and selective emitter crystalline silicon battery | |
| CN115692516A (en) | Novel TOPCON battery and manufacturing method thereof | |
| CN114583016A (en) | TOPCon battery and preparation method thereof | |
| CN114597267A (en) | TOPCon battery and preparation method thereof | |
| CN110120434B (en) | Battery piece and preparation method thereof | |
| CN117577708B (en) | Combined passivation back contact battery based on P-type silicon wafer, preparation method thereof and photovoltaic module | |
| CN118099230B (en) | Back contact cell with specific second semiconductor layer, preparation thereof and photovoltaic module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |