CN112669781B - Display processing method, display processing device and display panel - Google Patents
Display processing method, display processing device and display panel Download PDFInfo
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- CN112669781B CN112669781B CN202011472225.9A CN202011472225A CN112669781B CN 112669781 B CN112669781 B CN 112669781B CN 202011472225 A CN202011472225 A CN 202011472225A CN 112669781 B CN112669781 B CN 112669781B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Abstract
The invention provides a display processing method, a display processing device and a display panel, wherein the display processing method comprises the following steps: acquiring data signals of a current line pixel and a next line pixel of a current frame image; determining a charge sharing mode between data channels corresponding to sub-pixels in a next row of pixels according to data signals of a current row of pixels and the next row of pixels, wherein the charge sharing mode comprises global charge sharing and homopolar charge sharing; and carrying out charge sharing between the data channels corresponding to the sub-pixels in the next row of pixels according to the determined charge sharing mode. According to the display processing method provided by the embodiment of the invention, the charge sharing mode required to be adopted in different modes can be determined without the assistance of a time sequence control chip, the display processing method can be simultaneously applied to display panels with different pixel structures, the power consumption of the display panels can be effectively reduced, most of the existing circuits can be reused, and the chip area is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display processing method, a display processing device and a display panel.
Background
Currently, in order to reduce power consumption of a driving chip of a display panel, a Charge sharing (Charge sharing) technology is gradually applied to a liquid crystal display panel. In the conventional charge sharing technology, a switch can be arranged between an odd data channel and an even data channel, and then charge is evenly distributed between the odd data channel and the even data channel by controlling the on-off of the switch, so that the potentials of the odd data channel and the even data channel reach a common voltage, and then the odd data channel and the even data channel are respectively charged or discharged to the level with the corresponding polarity, thereby reducing the power consumption of the driving chip.
However, with the further development of display technology, the conventional charge sharing scheme has a limited reduction in power consumption, and when the charge sharing technology is adopted, a timing control chip (TCON) is required to provide assistance, and the charge sharing technology cannot be directly determined by a driving chip and adopted.
Disclosure of Invention
In view of the above, the present invention provides a display processing method, a display processing apparatus, and a display panel, which can solve the problems that the power consumption reduction capability of the charge sharing scheme in the prior art is limited and the assistance of a timing control chip is required.
In order to solve the technical problems, the invention adopts the following technical scheme:
in a first aspect, an embodiment of the present invention provides a display processing method, including:
acquiring data signals of a current line pixel and a next line pixel of a current frame image;
and determining a charge sharing mode between data channels corresponding to sub-pixels in the next row of pixels according to data signals of the current row of pixels and the next row of pixels, wherein the charge sharing mode comprises global charge sharing and homopolar charge sharing.
And carrying out charge sharing between the data channels corresponding to the sub-pixels in the next row of pixels according to the determined charge sharing mode.
Optionally, the step of determining, according to the data signals of the current row of pixels and the next row of pixels, a charge sharing manner between the data channels corresponding to the sub-pixels in the next row of pixels includes:
extracting the most significant bits of data signals corresponding to two sub-pixels of each data channel in the current row of pixels and the next row of pixels;
determining whether charge sharing is needed between data channels corresponding to sub-pixels in the next row of pixels according to the most significant bits of data signals of two sub-pixels corresponding to the same data channel in the current row of pixels and the next row of pixels, and determining a charge sharing mode between data channels corresponding to sub-pixels in the next row of pixels under the condition that charge sharing is needed.
Optionally, the step of determining, according to the most significant bits of the data signals of two sub-pixels corresponding to the same data channel in the current row of pixels and the next row of pixels, whether charge sharing is required between the data channels corresponding to the sub-pixels in the next row of pixels, and determining, in a case where charge sharing is required, a charge sharing manner between the data channels corresponding to the sub-pixels in the next row of pixels includes:
carrying out XOR operation on the most significant bits of the data signals of two sub-pixels corresponding to the same data channel in the current row of pixels and the next row of pixels to obtain the XOR operation result of each data channel;
respectively carrying out AND operation and OR operation on the XOR operation results of every at least two continuous data channels to obtain a plurality of AND operation results and OR operation results;
performing an and operation on the plurality of and operation results to obtain a first logic result, and performing an and operation on the plurality of or operation results to obtain a second logic result;
and determining whether charge sharing is needed between data channels corresponding to sub-pixels in the next row of pixels according to the first logic result and the second logic result, and determining a charge sharing mode under the condition that the charge sharing is needed.
Optionally, the step of determining, according to the first logic result and the second logic result, whether charge sharing is required between data channels corresponding to sub-pixels in the next row of pixels, and determining a charge sharing mode to be used when charge sharing is required includes:
determining not to perform charge sharing between data channels corresponding to sub-pixels in the next row of pixels under the condition that the first logic result and the second logic result are both 0;
determining that the charge sharing mode is homopolar charge sharing under the condition that the first logic result is 1 and the second logic result is 0;
and under the condition that the first logic result and the second logic result are both 1, determining that the charge sharing mode is global charge sharing.
Optionally, the step of performing charge sharing between data channels corresponding to sub-pixels in the next row of pixels according to the determined charge sharing manner includes:
under the condition that the determined charge sharing mode is same-polarity charge sharing, communicating the data channels corresponding to the same-polarity sub-pixels with each other;
and in the case that the determined sharing mode is global charge sharing, all the data channels are communicated with each other.
In a second aspect, an embodiment of the present invention further provides a display processing apparatus, including:
the acquisition module is used for acquiring data signals of a current line of pixels and a next line of pixels of a current frame image;
the determining module is used for determining a charge sharing mode between data channels corresponding to sub-pixels in a next row of pixels according to data signals of a current row of pixels and the next row of pixels, wherein the charge sharing mode comprises global charge sharing and homopolar charge sharing;
and the processing module is used for carrying out charge sharing between the data channels corresponding to the sub-pixels in the next row of pixels according to the determined charge sharing mode.
Optionally, the determining module includes:
the extraction unit is used for extracting the most significant bits of the data signals corresponding to the two sub-pixels of each data channel in the current row of pixels and the next row of pixels;
the determining unit is used for determining whether charge sharing is needed between data channels corresponding to sub-pixels in the next row of pixels according to the most significant bits of data signals of two sub-pixels corresponding to the same data channel in the current row of pixels and the next row of pixels, and determining a charge sharing mode between the data channels corresponding to the sub-pixels in the next row of pixels under the condition that the charge sharing is needed.
Optionally, the determining unit includes:
the first operation subunit is used for carrying out XOR operation on the most significant bits of the data signals of two sub-pixels corresponding to the same data channel in the current row of pixels and the next row of pixels to obtain the XOR operation result of each data channel;
the second operation subunit is used for respectively carrying out AND operation and OR operation on the XOR operation results of at least two continuous data channels to obtain a plurality of AND operation results and OR operation results;
the third operation subunit is used for performing AND operation on the plurality of AND operation results to obtain a first logic result, and performing AND operation on the plurality of OR operation results to obtain a second logic result;
and the determining subunit is configured to determine, according to the first logic result and the second logic result, whether charge sharing is required between data channels corresponding to sub-pixels in the next row of pixels, and determine a charge sharing mode to be used when charge sharing is required.
Optionally, the determining subunit includes:
the first microcell is used for determining that charge sharing is not performed between data channels corresponding to sub-pixels in the next row of pixels under the condition that the first logic result and the second logic result are both 0;
the second microcell is used for determining that the charge sharing mode is homopolar charge sharing under the condition that the first logic result is 1 and the second logic result is 0;
and the third microcell is used for determining that the charge sharing mode is global charge sharing under the condition that the first logic result and the second logic result are both 1.
Optionally, the processing module includes:
the first communication unit is used for communicating the data channels corresponding to the sub-pixels with the same polarity under the condition that the determined charge sharing mode is charge sharing with the same polarity;
and the second communication unit is used for communicating all the data channels with each other under the condition that the determined sharing mode is the global charge sharing.
In a third aspect, an embodiment of the present invention provides a display panel, including the display processing apparatus according to the second aspect.
The technical scheme of the invention has the following beneficial effects:
the display processing method of the embodiment of the invention can determine the charge sharing mode required to be adopted in different modes without the assistance of a time sequence control chip, can be simultaneously applied to display panels with different structures such as a single-gate type pixel structure, a double-gate type pixel structure and the like, can effectively reduce the power consumption of the display panels, can multiplex most of the existing circuits and reduces the chip area.
Drawings
Fig. 1 is a schematic diagram of a single-gate RGB pixel structure according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a single-gate RGBW pixel structure according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a dual-gate RGB pixel structure according to an embodiment of the invention;
fig. 4 is a schematic diagram of a dual-gate RGBW pixel structure according to an embodiment of the present invention;
FIG. 5 is one of the output voltage waveforms of a single gate type RGB pixel structure;
FIG. 6 shows a second output voltage waveform of the single gate RGB pixel structure;
FIG. 7 shows a third output voltage waveform of a single gate type RGB pixel structure;
FIG. 8 shows four output voltage waveforms for a single gate RGB pixel structure;
FIG. 9 shows a fifth output voltage waveform of a single gate type RGB pixel structure;
FIG. 10 shows six output voltage waveforms for a single gate RGB pixel structure;
fig. 11 is a schematic flowchart of a display processing method according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a detection circuit according to an embodiment of the present invention;
FIG. 13 is a diagram illustrating the classification of the first logical result and the second logical result according to an embodiment of the present invention;
FIG. 14 is a schematic diagram of a charge sharing circuit according to an embodiment of the present invention;
fig. 15 is a schematic temperature diagram of the display driver chip before and after the display processing method is adopted according to the embodiment of the present invention;
fig. 16 is a schematic structural diagram of a display processing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention, are within the scope of the invention.
Referring to fig. 1 to 4, fig. 1 is a schematic diagram of a single-gate RGB pixel structure according to an embodiment of the present invention, fig. 2 is a schematic diagram of a single-gate RGBW pixel structure according to an embodiment of the present invention, fig. 3 is a schematic diagram of a dual-gate RGB pixel structure according to an embodiment of the present invention, and fig. 4 is a schematic diagram of a dual-gate RGBW pixel structure according to an embodiment of the present invention. As shown in fig. 1-4, currently, the pixel arrangement structures in the display panel include a single-gate RGB pixel arrangement structure, a single-gate RGBW pixel arrangement structure, a dual-gate RGB pixel arrangement structure, a dual-gate RGBW pixel arrangement structure, and the like, in the prior art, a conventional charge sharing scheme is proposed for a display panel of a certain pixel arrangement structure, and can only be applied to a display panel of a corresponding single pixel arrangement structure, but cannot be directly applied to display panels of other pixel arrangement structures, which undoubtedly increases the workload of designing the driving circuit chip, and is inconvenient for application and popularization. Moreover, the conventional charge sharing scheme requires the assistance of a timing control chip (TCON), which means that the difficulty of circuit/chip design is increased, the area of the chip is increased, and the power consumption is correspondingly increased. Therefore, how to select a proper charge sharing mode by judging displayed frame picture data without additional assistance of a timing control chip and simultaneously enable the charge sharing method to be applied to display panels with different pixel arrangement structures becomes a problem to be solved urgently at present, and finally the chip design difficulty is reduced, the operation power consumption is reduced, and application scenes are expanded.
Referring to fig. 5-10, fig. 5 shows one of the output voltage waveforms of the single-gate RGB pixel structure, fig. 6 shows the second output voltage waveform of the single-gate RGB pixel structure, fig. 7 shows the third output voltage waveform of the single-gate RGB pixel structure, fig. 8 shows the fourth output voltage waveform of the single-gate RGB pixel structure, fig. 9 shows the fifth output voltage waveform of the single-gate RGB pixel structure, and fig. 10 shows the sixth output voltage waveform of the single-gate RGB pixel structure. As shown in fig. 5-7, CH 1-CH 6 correspond to six data channels (i.e., six columns of data lines) of a single gate type RGB pixel structure, the polarities of the driving data signals in CH1 and CH4 in fig. 5 are opposite, the polarities of the data signals in red subpixels corresponding to the first and fourth columns are changed, the polarities of the driving data signals in CH3 and CH6 in fig. 6 are opposite, the polarities of the data signals in blue subpixels corresponding to the third and sixth columns are changed, the polarities of the driving data signals in CH1 and CH4 in fig. 7 are opposite, the polarities of the data signals in red subpixels corresponding to the first and fourth columns are changed, the polarities of the driving data signals in CH3 and CH6 are opposite, the polarities of the data signals in blue subpixels corresponding to the third and sixth columns are opposite, the polarities of the driving data signals in data channels corresponding to odd and even columns of subpixels in fig. 8 are opposite, the polarity of the data signals corresponding to the odd-column sub-pixels and the even-column sub-pixels changes, in fig. 9, the polarities of the driving data signals in the data channels corresponding to the odd-column sub-pixels and the even-column sub-pixels are the same, in fig. 10, the polarities of the driving data signals in the data channels corresponding to the odd-column sub-pixels and the even-column sub-pixels do not change, and in this case, the charge sharing is not needed. Therefore, the voltage waveform output to the display panel can reflect the polarity change rules of different sub-pixels, namely the polarity change rules of the driving data signals in the data channels corresponding to the different sub-pixels, so that a proper charge sharing mode can be selected according to the polarity change rules, and the power loss of the display panel is saved.
Therefore, please refer to fig. 11, which is a flowchart illustrating a display processing method according to an embodiment of the present invention. As shown in fig. 11, the display processing method in the embodiment of the present invention may specifically include:
step 111: and acquiring data signals of a current row of pixels and a next row of pixels of the current frame image.
Fig. 12 is a schematic diagram of a detection circuit according to an embodiment of the invention. As shown in fig. 12, the data signal output from the first latch is output to the second latch, and the data signal output from the second latch is converted into a level signal having polarity after passing through a level shift circuit (L/S) and an amplifier, and is output to a corresponding data channel. Thus, it is considered that the data signal output from the second latch corresponds to the data signal of the pixel in the current row, and the data signal output from the first latch corresponds to the data signal of the pixel in the next row, so that the data signals of the pixel in the current row and the pixel in the next row of the current frame image can be acquired from the second latch and the first latch. In the embodiment of the present invention, the first latch, the second latch, the level shift circuit, and the amplifier are combined to form a conversion circuit, more specifically, a digital-to-analog conversion circuit, and data signals output from the first latch and the second latch are digital signals.
Step 112: and determining a charge sharing mode between data channels corresponding to sub-pixels in the next row of pixels according to data signals of the current row of pixels and the next row of pixels, wherein the charge sharing mode comprises global charge sharing and homopolar charge sharing.
In the embodiment of the present invention, as can be seen from the foregoing, the voltage waveform output to the display panel can reflect the polarity change rule of different sub-pixels, that is, the polarity change rule of the driving data signal in the data channel corresponding to each of the different sub-pixels, so as to determine whether charge sharing is required according to the polarity change rule, and select a suitable charge sharing mode when charge sharing is required; optionally, the charge sharing manner in this embodiment of the present application includes Global charge sharing (GCS for short) and Polarity charge sharing (PCS for short).
In an embodiment of the present invention, the step of determining, according to data signals of a current row of pixels and a next row of pixels, a charge sharing manner between data channels corresponding to sub-pixels in the next row of pixels includes:
extracting the most significant bits of data signals corresponding to two sub-pixels of each data channel in the current row of pixels and the next row of pixels;
determining whether charge sharing is needed between data channels corresponding to sub-pixels in the next row of pixels according to the most significant bits of data signals of two sub-pixels corresponding to the same data channel in the current row of pixels and the next row of pixels, and determining a charge sharing mode between data channels corresponding to sub-pixels in the next row of pixels under the condition that charge sharing is needed.
Because the driving data signals in the data channels corresponding to different sub-pixels have a certain polarity change rule, and the polarity change rule of the driving data signals can be embodied by the most significant bit, in the embodiment of the invention, only the most significant bit in each data signal needs to be extracted, whether charge sharing is needed between the data channels corresponding to the sub-pixels in the next row of pixels can be determined according to the most significant bit of the data signal, and a proper charge sharing mode is selected under the condition that the charge sharing is needed. Therefore, after acquiring the data signals of the current row of pixels and the next row of pixels of the current frame image, the Most Significant bits of the data signals corresponding to two sub-pixels of each data channel in the current row of pixels and the next row of pixels need to be extracted, wherein each data channel is a data line corresponding to each column of sub-pixels.
In an embodiment of the present invention, the step of determining whether charge sharing is required between data channels corresponding to sub-pixels in a next row of pixels according to most significant bits of data signals of two sub-pixels corresponding to a same data channel in a current row of pixels and a next row of pixels, and determining a charge sharing mode between data channels corresponding to sub-pixels in the next row of pixels when charge sharing is required includes:
carrying out XOR operation on the most significant bits of the data signals of two sub-pixels corresponding to the same data channel in the current row of pixels and the next row of pixels to obtain the XOR operation result of each data channel;
respectively carrying out AND operation and OR operation on the XOR operation results of every at least two continuous data channels to obtain a plurality of AND operation results and OR operation results;
performing an and operation on the plurality of and operation results to obtain a first logic result, and performing an and operation on the plurality of or operation results to obtain a second logic result;
and determining whether charge sharing is needed between data channels corresponding to sub-pixels in the next row of pixels according to the first logic result and the second logic result, and determining a charge sharing mode under the condition that the charge sharing is needed.
With reference to fig. 12, after extracting the most significant bits of the data signals corresponding to the two sub-pixels of each data channel in the current row of pixels and the next row of pixels, performing an exclusive or operation on the most significant bits of the data signals corresponding to the two sub-pixels of the same data channel in the current row of pixels and the next row of pixels to obtain an exclusive or operation result of each data channel, where each row of pixels corresponds to M data channels (only 6 are shown in the figure), and therefore, after the exclusive or operation, M exclusive or operation results are obtained, where M is a positive integer; in the embodiment of the present invention, further, the exclusive-or operation results of each at least two consecutive data channels are respectively subjected to an and operation and an or operation, that is, the M exclusive-or operation results may be grouped by the exclusive-or operation results of each adjacent at least two consecutive data channels, the exclusive-or operation results in the group are respectively subjected to an and operation and an or operation, optionally, as shown in fig. 12, in the embodiment of the present invention, the xor operation result corresponding to each consecutive three data channels is used as a group to perform an and operation and an or operation, of course, in the actual design, the xor operation results corresponding to 2 data channels may be used as a group, which may be changed according to the actual requirement, such a change should also be considered as a range covered by the inventive concept in the present application, and thus N and operation results and N or operation results (M ═ 3N) may be obtained; and finally, performing and operation on the plurality of and operation results to obtain a first logic result iCO, performing and operation on the plurality of or operation results to obtain a second logic result iHP, and finally determining whether charge sharing is required between the data channels corresponding to the sub-pixels in the next row of pixels according to the first logic result iCO and the second logic result iHP, and determining a charge sharing mode between the data channels corresponding to the sub-pixels in the next row of pixels under the condition that the charge sharing is required. It can be seen that in the detection circuit for performing detection processing on the most significant bit in the embodiment of the present invention, each three data channels substantially require 7 additional logic gates to implement the above logic operation and complete the detection, so that the complexity of the circuit is hardly affected, the cost is hardly changed, the occupied area of the circuit can be saved, and the power consumption can be reduced.
In this embodiment of the present invention, the determining, according to the first logic result and the second logic result, whether charge sharing is required between data channels corresponding to sub-pixels in the next row of pixels, and determining a charge sharing manner to be used when charge sharing is required includes:
determining not to perform charge sharing between data channels corresponding to sub-pixels in the next row of pixels under the condition that the first logic result and the second logic result are both 0;
determining that the charge sharing mode is homopolar charge sharing under the condition that the first logic result is 1 and the second logic result is 0;
and under the condition that the first logic result and the second logic result are both 1, determining that the charge sharing mode is global charge sharing.
Please refer to fig. 13, which is a diagram illustrating the classification of the first logic result and the second logic result according to an embodiment of the present invention. As shown in fig. 13, when both the first logic result iCO and the second logic result iHP are 0, the corresponding screen display mode at this time is a Non-switching mode (Non toggle pattern), that is, corresponding to a stable screen such as white or black, in which case, it is not necessary to perform charge sharing between the data channels corresponding to the sub-pixels in the next row of pixels; when the first logic result iCO is 1 and the second logic result iHP is 0, the corresponding screen display mode is a Color mode (Color pattern), in which case, charge sharing is required and the charge sharing mode can be determined to be charge sharing of the same polarity; when the first logic result iCO is 1 and the second logic result iHP is 1, the corresponding screen display mode at this time is an All channel switching mode (All channel toggle pattern), and in this case, it is necessary to perform charge sharing and it is possible to determine that the charge sharing method is global charge sharing.
Step 113: and carrying out charge sharing between the data channels corresponding to the sub-pixels in the next row of pixels according to the determined charge sharing mode.
After the charge sharing is determined to be needed and the corresponding charge sharing mode is determined, the charge sharing can be performed between the data channels corresponding to the sub-pixels in the next row of pixels.
In an embodiment of the present invention, specifically, the step of performing charge sharing between data channels corresponding to sub-pixels in the next row of pixels according to the determined charge sharing manner includes:
under the condition that the determined charge sharing mode is same-polarity charge sharing, communicating the data channels corresponding to the same-polarity sub-pixels with each other;
and in the case that the determined sharing mode is global charge sharing, all the data channels are communicated with each other.
Fig. 14 is a schematic diagram of a charge sharing circuit according to an embodiment of the invention. As shown in fig. 14, 12 data channels O1 to O12 are shown, and after the signals output by the amplifiers are given polarity by the front-end circuits, the signals can be correspondingly output to the corresponding data channels, and finally reach the corresponding sub-pixels for driving. A plurality of polarity selection switches are configured on a path from the front-end circuit, wherein the polarity selection switches comprise P1B, N1B, P2B, N2B, P3B, N3B, N4B, N1, N2, N3, N4, P1, P2, P3 and P4, and the polarity of a signal corresponding to a data channel can be controlled by controlling the on-off of the polarity selection switches; furthermore, a plurality of charge sharing switches including a first switch ST1, a second switch ST2, a third switch ST3, and a fourth switch ST4 are disposed between the data channels, and charge sharing between the data channels can be realized by controlling on/off of the charge sharing switches. For example, when the pixel structure type of the display panel is RGB arrangement, the polarity of each data channel in a row of pixels is +, -, and+, -, whereby charge sharing between data channels of the same polarity can be achieved by controlling the first switch ST1 and the third switch ST3 to be turned on, and the second switch ST2 and the fourth switch ST4 to be turned off, thereby reducing power consumption of the display panel; by analogy, the display panels with other pixel arrangement structures can also realize the charge sharing with the same polarity. It is to be understood that the charge sharing circuit shown in fig. 14 can be used for global charge sharing as well, and when global charge sharing is performed, the first switch ST1, the second switch ST2, the third switch ST3, and the fourth switch ST4 may be all connected.
Fig. 15 is a schematic temperature diagram of the display driver chip before and after the display processing method is adopted according to the embodiment of the present invention. As shown in fig. 15, by measuring the temperatures of the display driver chip using the display processing method in the embodiment of the present invention and the display driver chip not using the display processing method in the embodiment of the present invention, it can be seen that, after the display processing method is used, the temperature of the display driver chip can be reduced by 6 ℃ in the red and blue image display, while the black frame can be reduced by 2.75 ℃, and the white frame can be reduced by 3.5 ℃, and thus, the power consumption of the display driver chip can be effectively reduced.
The display processing method of the embodiment of the invention can determine the charge sharing mode required to be adopted in different modes without the assistance of a time sequence control chip, can be simultaneously applied to display panels with different structures such as a single-gate type pixel structure, a double-gate type pixel structure and the like, can effectively reduce the power consumption of the display panels, can multiplex most of the existing circuits and reduces the chip area.
Fig. 16 is a schematic structural diagram of a display processing apparatus according to an embodiment of the present invention. As shown in fig. 16, another embodiment of the present invention further provides a display processing apparatus, where the display processing apparatus 160 may include:
an obtaining module 161, configured to obtain data signals of a current line of pixels and a next line of pixels of a current frame image;
a determining module 162, configured to determine, according to data signals of a current row of pixels and a next row of pixels, a charge sharing manner between data channels corresponding to sub-pixels in the next row of pixels, where the charge sharing manner includes global charge sharing and homopolar charge sharing;
and the processing module 163 is configured to perform charge sharing between the data channels corresponding to the sub-pixels in the next row of pixels according to the determined charge sharing manner.
The display processing device of the embodiment of the invention can determine the charge sharing mode required to be adopted in different modes without the assistance of a time sequence control chip, can be simultaneously applied to display panels with different structures such as a single-gate type pixel structure, a double-gate type pixel structure and the like, can effectively reduce the power consumption of the display panels, can multiplex most of the existing circuits and reduces the chip area.
Optionally, the determining module 162 includes:
the extraction unit is used for extracting the most significant bits of the data signals corresponding to the two sub-pixels of each data channel in the current row of pixels and the next row of pixels;
the determining unit is used for determining whether charge sharing is needed between data channels corresponding to sub-pixels in the next row of pixels according to the most significant bits of data signals of two sub-pixels corresponding to the same data channel in the current row of pixels and the next row of pixels, and determining a charge sharing mode between the data channels corresponding to the sub-pixels in the next row of pixels under the condition that the charge sharing is needed.
Optionally, the determining unit includes:
the first operation subunit is used for carrying out XOR operation on the most significant bits of the data signals of two sub-pixels corresponding to the same data channel in the current row of pixels and the next row of pixels to obtain the XOR operation result of each data channel;
the second operation subunit is used for respectively carrying out AND operation and OR operation on the XOR operation results of at least two continuous data channels to obtain a plurality of AND operation results and OR operation results;
the third operation subunit is used for performing AND operation on the plurality of AND operation results to obtain a first logic result, and performing AND operation on the plurality of OR operation results to obtain a second logic result;
and the determining subunit is configured to determine, according to the first logic result and the second logic result, whether charge sharing is required between data channels corresponding to sub-pixels in the next row of pixels, and determine a charge sharing mode to be used when charge sharing is required.
Optionally, the determining subunit includes:
the first microcell is used for determining that charge sharing is not performed between data channels corresponding to sub-pixels in the next row of pixels under the condition that the first logic result and the second logic result are both 0;
the second microcell is used for determining that the charge sharing mode is homopolar charge sharing under the condition that the first logic result is 1 and the second logic result is 0;
and the third microcell is used for determining that the charge sharing mode is global charge sharing under the condition that the first logic result and the second logic result are both 1.
Optionally, the processing module includes:
the first communication unit is used for communicating the data channels corresponding to the sub-pixels with the same polarity under the condition that the determined charge sharing mode is charge sharing with the same polarity;
and the second communication unit is used for communicating all the data channels with each other under the condition that the determined sharing mode is the global charge sharing.
The display processing apparatus in the embodiment of the present invention is an apparatus corresponding to the display processing method in the embodiment of the present invention, and can implement each step of the display processing method, and achieve the same technical effect, and in order to avoid repetition, the details are not described here again.
In another aspect, an embodiment of the present invention further provides a display panel, where the display panel includes the display processing apparatus described in the above embodiment, and since the display processing apparatus has the above beneficial effects, the display panel in the embodiment of the present invention also has the above beneficial effects, and in order to avoid repetition, details are not repeated here.
While the foregoing is directed to embodiments of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made without departing from the principles of the invention, and it is intended that all such changes and modifications be considered as within the scope of the invention.
Claims (7)
1. A display processing method, comprising:
acquiring data signals of a current line pixel and a next line pixel of a current frame image;
determining a charge sharing mode between data channels corresponding to sub-pixels in a next row of pixels according to data signals of a current row of pixels and the next row of pixels, wherein the charge sharing mode comprises global charge sharing and homopolar charge sharing, and comprises the following steps: extracting the most significant bits of data signals corresponding to two sub-pixels of each data channel in the current row of pixels and the next row of pixels; carrying out XOR operation on the most significant bits of the data signals of two sub-pixels corresponding to the same data channel in the current row of pixels and the next row of pixels to obtain the XOR operation result of each data channel; respectively carrying out AND operation and OR operation on the XOR operation results of every at least two continuous data channels to obtain a plurality of AND operation results and OR operation results; performing an and operation on the plurality of and operation results to obtain a first logic result, and performing an and operation on the plurality of or operation results to obtain a second logic result; determining whether charge sharing is needed between data channels corresponding to sub-pixels in the next row of pixels according to the first logic result and the second logic result, and determining a charge sharing mode under the condition that the charge sharing is needed;
and carrying out charge sharing between the data channels corresponding to the sub-pixels in the next row of pixels according to the determined charge sharing mode.
2. The method according to claim 1, wherein the step of determining whether charge sharing is required between data channels corresponding to sub-pixels in the next row of pixels according to the first logic result and the second logic result, and determining a charge sharing mode to be used when charge sharing is required comprises:
determining not to perform charge sharing between data channels corresponding to sub-pixels in the next row of pixels under the condition that the first logic result and the second logic result are both 0;
determining that the charge sharing mode is homopolar charge sharing under the condition that the first logic result is 1 and the second logic result is 0;
and under the condition that the first logic result and the second logic result are both 1, determining that the charge sharing mode is global charge sharing.
3. The method according to claim 1, wherein the step of performing charge sharing between data channels corresponding to sub-pixels in the next row of pixels according to the determined charge sharing manner comprises:
under the condition that the determined charge sharing mode is same-polarity charge sharing, communicating the data channels corresponding to the same-polarity sub-pixels with each other;
and in the case that the determined sharing mode is global charge sharing, all the data channels are communicated with each other.
4. A display processing apparatus characterized by comprising:
the acquisition module is used for acquiring data signals of a current line of pixels and a next line of pixels of a current frame image;
the determining module is used for determining a charge sharing mode between data channels corresponding to sub-pixels in a next row of pixels according to data signals of a current row of pixels and the next row of pixels, wherein the charge sharing mode comprises global charge sharing and homopolar charge sharing;
the processing module is used for carrying out charge sharing between the data channels corresponding to the sub-pixels in the next row of pixels according to the determined charge sharing mode;
the determination module comprises an extraction unit and a determination unit:
the extraction unit is used for extracting the most significant bits of the data signals corresponding to the two sub-pixels of each data channel in the current row of pixels and the next row of pixels;
the determination unit includes:
the first operation subunit is used for carrying out XOR operation on the most significant bits of the data signals of two sub-pixels corresponding to the same data channel in the current row of pixels and the next row of pixels to obtain the XOR operation result of each data channel;
the second operation subunit is used for respectively carrying out AND operation and OR operation on the XOR operation results of at least two continuous data channels to obtain a plurality of AND operation results and OR operation results;
the third operation subunit is used for performing AND operation on the plurality of AND operation results to obtain a first logic result, and performing AND operation on the plurality of OR operation results to obtain a second logic result;
and the determining subunit is configured to determine, according to the first logic result and the second logic result, whether charge sharing is required between data channels corresponding to sub-pixels in the next row of pixels, and determine a charge sharing mode to be used when charge sharing is required.
5. The display processing apparatus according to claim 4, wherein the determination subunit includes:
the first microcell is used for determining that charge sharing is not performed between data channels corresponding to sub-pixels in the next row of pixels under the condition that the first logic result and the second logic result are both 0;
the second microcell is used for determining that the charge sharing mode is homopolar charge sharing under the condition that the first logic result is 1 and the second logic result is 0;
and the third microcell is used for determining that the charge sharing mode is global charge sharing under the condition that the first logic result and the second logic result are both 1.
6. The display processing apparatus of claim 4, wherein the processing module comprises:
the first communication unit is used for communicating the data channels corresponding to the sub-pixels with the same polarity under the condition that the determined charge sharing mode is charge sharing with the same polarity;
and the second communication unit is used for communicating all the data channels with each other under the condition that the determined sharing mode is the global charge sharing.
7. A display panel comprising the display processing apparatus according to any one of claims 4 to 5.
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| CN202011472225.9A CN112669781B (en) | 2020-12-14 | 2020-12-14 | Display processing method, display processing device and display panel |
| PCT/CN2021/094569 WO2022127021A1 (en) | 2020-12-14 | 2021-05-19 | Display processing method, display processing apparatus and display panel |
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| CN202011472225.9A CN112669781B (en) | 2020-12-14 | 2020-12-14 | Display processing method, display processing device and display panel |
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| CN112669781B (en) * | 2020-12-14 | 2022-04-12 | 北京奕斯伟计算技术有限公司 | Display processing method, display processing device and display panel |
| CN114399979B (en) * | 2021-12-20 | 2023-03-24 | 北京奕斯伟计算技术股份有限公司 | Circuit structure and display driving chip |
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| WO2022127021A1 (en) | 2022-06-23 |
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