KR20120025657A - Source driver for reducing emi of a liquid crystal display - Google Patents

Abstract

PURPOSE: A source driver of a liquid display apparatus for reducing electromagnetic interference is provided to output data of each channel by dispersing the data with time differences using an RC delay device or an HV(High Voltage) inverter. CONSTITUTION: A first latch part(220A) successively latches data of each channel. An input driving signal output part(230) outputs an input driving signal. A plurality of delay devices(D_L11-D_L1m) successively delays the input driving signal. A second latch part(220B) successively latches the data of each channel with time differences. A digital-analog converter converts the data of each channel into an analog signal.

Description

SOURCE DRIVER FOR REDUCING EMI OF A LIQUID CRYSTAL DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for reducing electromagnetic interference in a liquid crystal display device. In particular, when a data driver outputs a data signal for driving a liquid crystal panel from a source driver, a liquid crystal display is used for reducing electromagnetic interference so that electromagnetic interference is reduced. The source driver for the device.

In general, a liquid crystal display device includes a liquid crystal display panel having a plurality of gate lines and data lines arranged in a direction perpendicular to each other, having a pixel region in a matrix form, a driving circuit unit supplying driving signals and data signals to the liquid crystal display panel; A backlight for providing a light source to the liquid crystal display panel is provided.

The driving circuit unit may include a source driver for supplying a data signal to each data line of the liquid crystal display panel, a gate driver for applying a gate driving pulse to each gate line of the liquid crystal display panel, and a driving system of the liquid crystal display panel. And a timing controller that receives the control data such as display data, vertical and horizontal synchronization signals, and a clock signal, and outputs them at a timing suitable for the source driver and the gate driver to reproduce the screen.

FIG. 1 is a block diagram of a source driver according to the prior art, and has a shift register section 110, a latch section 120, a D / A converter 130, and an output buffer 140, as shown therein.

The shift register unit 110 sequentially shifts the sampling start signal SS by using the clock signal CLK.

The latch unit 120 uses the sampling start signal output from the shift register unit 110 to output RGB image data (hereinafter, referred to as 'data') of each channel supplied from a timing controller (not shown). ) Sequentially.

The digital (D) / analog (A) converter 130 converts the digital data latched by the latch unit 120 into an analog data signal. The analog data signal has a positive value or a negative value with respect to the common voltage Vcom according to the polarity signal POL.

The output buffer 140 buffers the analog data signal converted by the D / A converter 130 and outputs the amplified data to the data lines D1 to Dn of the liquid crystal panel.

However, the latch unit 120 sequentially latches data of each channel and outputs the same. Accordingly, the data voltages of all the channels are simultaneously loaded from the output buffer 140 to each of the data lines DL1 to DLn.

As described above, in the source driver of the conventional LCD, power is concentrated by outputting data of all channels at the same time, and thus, there is a problem in that electromagnetic interference (EMI) is severe.

Accordingly, it is an object of the present invention to sequentially distribute output with a predetermined time difference when latching and outputting data of each channel in a latch of a source driver.

Another object of the present invention is to use an RC delay unit or an HV inverter as a delay element for distributedly outputting data of each channel with a predetermined time difference.

Still another object of the present invention is to provide a distributed output by sequentially delaying and outputting a time difference when outputting a data signal from an output buffer of a source driver.

The objects of the present invention are not limited to the above-mentioned objects. Other objects and advantages of the invention will be more clearly understood by the following description.

The present invention for achieving the above object,

A first latch unit sequentially latching data of each channel for driving the liquid crystal panel;

An input drive signal output unit configured to output an input drive signal;

A plurality of delayers serially connected to sequentially delay the input drive signal;

A second latch unit sequentially latching data of each channel latched in the first latch unit with a time difference by using input driving signals sequentially delayed through the plurality of delay units;

And a D / A converter for converting data of each channel output from the second latch unit into an analog signal and outputting the analog signal to an output buffer.

Another invention for achieving the above object,

A first latch unit sequentially latching data of each channel for driving the liquid crystal panel;

An input drive signal output unit configured to output an input drive signal to latch data latched to the first latch unit bit by bit;

A second latch unit sequentially latching data of each channel latched in the first latch unit bit by bit with a time difference by using the input drive signals output from the input drive signal output unit;

And a D / A converter for converting data of each channel output from the second latch unit into an analog signal and outputting the analog signal to an output buffer.

Another invention for achieving the above object,

A first latch unit sequentially latching data of each channel for driving the liquid crystal panel;

An input drive signal output unit configured to output an input drive signal;

A plurality of delayers each receiving the input driving signal and sequentially delaying the input driving signal;

A second latch unit configured to sequentially latch data of each channel latched in the first latch unit with a time delay corresponding to the delayed delay amount by using the input driving signals delayed and output through the plurality of delay units;

And a D / A converter for converting data of each channel output from the second latch unit into an analog signal and outputting the analog signal to an output buffer.

Another invention for achieving the above object,

A data output controller for outputting a switching control signal for outputting a data signal to each data channel of the liquid crystal panel at a desired timing;

A first delay unit and a second delay unit configured to sequentially delay and output the switching control signal output from the data output controller for a preset time;

A first output buffer unit having a plurality of multiplexers for selecting an analog data signal output from an amplifier and outputting the same to a corresponding channel by a switching control signal sequentially delayed by the first delay unit;

The second output buffer unit includes a plurality of multiplexers for selecting and outputting an analog data signal output from the amplifier according to the switching control signal sequentially delayed by the second delay unit.

According to the present invention, when latching and outputting data of each channel by a latch of a source driver of a liquid crystal display device, the interference is more reliably distributed by sequentially outputting a predetermined time difference or distributedly outputting bit by bit using an input drive signal. There is an effect that can be reduced easily.

In addition, by distributing and outputting the data signal output from the output buffer in a manner of sequentially delaying and outputting a predetermined time difference, the power of the high voltage is distributed accordingly to reduce the electromagnetic interference.

1 is a block diagram of a source driver of a liquid crystal display device according to the prior art.
2 is a block diagram of a source driver of a liquid crystal display device for reducing electromagnetic interference according to the present invention.
3A is a waveform diagram of a source out enable signal.
3B and 3E are waveform diagrams of input driving signals supplied in a delayed form to the second latch portion.
4 to 6 are partial detailed block diagrams of a source driver for reducing electromagnetic interference according to the present invention.
7 is a circuit diagram showing an embodiment of the RC delay applied to the present invention.
8 is a block diagram showing another embodiment of a source driver of a liquid crystal display device for reducing electromagnetic interference according to the present invention;
9 is a block diagram showing another embodiment of a source driver of a liquid crystal display device for reducing electromagnetic interference according to the present invention;
10A is a waveform diagram of a source out enable signal.
10 (b)-(e) are waveform diagrams of data signals showing delayed output sequentially by t.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a source driver of a liquid crystal display device for reducing electromagnetic interference according to the present invention. As shown therein, the shift register unit 210, the first latch unit 220A, and the second latch unit 220B are shown. ), An input drive signal output unit 230, a D / A converter 240, and an output buffer 250.

The shift register unit 210 sequentially shifts the sampling start signal SS by using the clock signal CLK.

The first latch unit 220A sequentially latches data DATA of each channel supplied from a timing controller (not shown) using the sampling start signal output from the shift register unit 210.

When the second latch unit 220B latches data of each channel latched by the first latch unit 220A, the second latch unit 220B does not latch the data simultaneously but instead outputs the input driving signal DRV output from the input driving signal output unit 230. Latch with a predetermined parallax using.

3 is a waveform diagram illustrating an input driving signal DRV supplied from the input driving signal output unit 230 to the second latch unit 220B. That is, the input drive signal output unit 230 outputs the input drive signal DRV in the state in which the source out enable signal SOE is "high" as shown in FIG. As shown in (e), the batteries are sequentially supplied with a predetermined time difference, and the second latch unit 220B latches data and outputs the data to the D / A converter 240 in response to the input driving signal DRV.

The D / A converter 240 converts the digital data latched in the second latch unit 220A into an analog data signal. The analog data signal has a positive value or a negative value with respect to the common voltage Vcom according to the polarity signal POL.

The output buffer 250 buffers the analog data signal converted by the D / A converter 240 and outputs the amplified data to the data lines D1 to Dn of the liquid crystal panel.

Hereinafter, with reference to the accompanying drawings, each embodiment of the distributed output of the data signal which is the technical configuration of the present invention will be described in detail.

First, referring to FIG. 4, a first embodiment in which data signals are distributed and output using a plurality of delay units connected in series is as follows.

As described above, the shift registers SR_L11 to SR_L1m and SR_R11 to SR_R1m of the shift register unit 210 sequentially shift the sampling start signal SS using the clock signal CLK.

The latches LA_L11 to LA_L1m and LA_R11 to LA_R1m of the first latch unit 220A sequentially latch data DATA1 and DATA2 using the sampling start signal output from the shift register 210.

The input drive signal DRV output from the input drive signal output unit 230 is sequentially delayed through the serially connected delay units D_L11 to D_L1m and D_R11 to D_R1m.

Each latch (LA_L21 to LA_L2m) and (LA_R21 to LA_R2m) of the second latch unit 220B includes the data of each channel in the latches (LA_L11 to LA_L1m) and (LA_R11 to LA_R1m) of the first latch unit 220A. After latching, the data of the corresponding channel is latched. The latches are sequentially latched with a predetermined time difference by using the corresponding input drive signal DRV delayed through the delayers D_L11 to D_L1m and D_R11 to D_R1m. .

For example, the first latch LA_L21 on the left side of the input drive signal output unit 230 is output from the input drive signal output unit 230 and then delayed once through one delay unit D_L11. The latched data is latched by the latch LA_L11 of the first latch unit 220A using the driving signal DRV.

In addition, the m-th latch LA_L2m is output from the input driving signal output unit 230 and the first latch unit using the input driving signal DRV delayed m times through m delayers D_L11 continuously. The latched data is latched in the latch LA_L1m of 220A.

Accordingly, the time difference corresponding to the accumulated delay amount of data of each channel output from the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m of the second latch unit 220B to the D / A converter 240 is adjusted. And distributed output.

The retarders D_L11 to D_L1m and D_R11 to D_R1m may be implemented in various ways. In FIG. 7, RC elements R1 and M1, R2 and M2 formed of resistors and capacitors, and inverter I1, An example of implementing the delay unit as (I2) is shown. Here, the MOS transistors M1 and M2 connect a gate to an input terminal, connect a drain and a source to each other, and then connect the connection point to the ground terminal to be used as a capacitor. The desired delay amount can be obtained by adding as many RC elements R1, M1, R2, M2, and inverters I1, I2 as necessary.

Meanwhile, referring to FIG. 5, a second embodiment of the present invention, in which distributed output is performed by dividing and latching data of each channel bit by bit, is described below.

The shift registers SR_L11 to SR_L1m and SR_R11 to SR_R1m of the shift register unit 210 sequentially shift the sampling start signal SS using the clock signal CLK as described above.

In addition, the latches LA_L11 to LA_L1m and LA_R11 to LA_R1m of the first latch portion 220A are also provided with the data DATA1 using the sampling start signal SS output from the shift register 210 as described above. ) And (DATA2) sequentially.

The input drive signal output unit 230 outputs an input drive signal so that the second latch unit 220B can latch the data latched by the first latch unit by a predetermined bit, and thus the input drive signal DRV is output. ) Is delayed through the delays D_L11 and D_R11, and then sequentially supplied to the bits of the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m of the second latch 220B. Therefore, data is distributed and output in a manner of sequentially outputting one bit or a predetermined bit at each latch LA_L21 to LA_L2m and LA_R21 to LA_R2m of the second latch unit 220B.

For example, after the input driving signal DRV output from the input driving signal output unit 230 is delayed through the delay units D_L11 and D_R11, the latches LA_L21 to the second latch unit 220B are delayed. It is supplied to the first bit of LA_L2m) and (LA_R21 to LA_R2m) to output data of the first bit of each channel. Subsequently, the input driving signal DRV is delayed through the delays D_L11 and D_R11, respectively, and then supplied to the second bit of each of the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m, and thus the second of each channel. Bit data is output. In this manner, the input drive signal DRV is supplied to the last bit of each of the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m to output the data of the first bit after the data of the last bit of each channel is output. do.

In the above description, the data is output one bit at each of the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m. However, the present invention is not limited thereto and the data is distributed in units of bits as necessary. Can be output.

Accordingly, data of each channel output to the D / A converter 240 may be distributed from the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m of the second latch unit 220B.

Meanwhile, with reference to FIG. 6, a third embodiment of the present invention outputs each input driving signal DRV simultaneously, and outputs data in such a manner that the delay amounts are supplied to the latches of the channels through the respective delayers. The explanation is as follows.

The shift registers SR_L11 to SR_L1m and SR_R11 to SR_R1m of the shift register unit 210 sequentially shift the sampling start signal SS using the clock signal CLK as described above.

In addition, the latches LA_L11 to LA_L1m and LA_R11 to LA_R1m of the first latch portion 220A are also provided with the data DATA1 using the sampling start signal SS output from the shift register 210 as described above. ) And (DATA2) sequentially.

The input drive signal DRV output from the input drive signal output unit 230 is delayed through the delay units D_L11 to D_L1m and D_R11 to D_R1m having different delay amounts, respectively, and then the second latch unit 220B of the second latch unit 220B. The latches are sequentially supplied to the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m. Accordingly, each of the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m of the second latch unit 220B have a time difference corresponding to the delay amount of the delay units D_L11 to D_L1m and D_R11 to D_R1m. To latch and output the data.

The delay amounts of the delay units D_L11 and D_R11 are the smallest, and the delay amount gradually increases, so that the delay amounts of the delay units D_L1m and D_R1m are described as an example.

In such a case, the latches LA_L21 and LA_R21 among the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m of the second latch 220B first latch data of the corresponding channel, and the next latch. (LA_L22 ~ LA_L2m-1) and (LA_R22 ~ LA_R2m-1) latch the data of the channel with the time difference by the corresponding delay amount, and finally latch (LA_L2m) and (LA_R2m) latch the data of the last channel. Done.

Therefore, the D / A converter 240 is separated from the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m of the second latch unit 220B with a time difference corresponding to the delay amount difference between the delay units D_L11 and D_R11. ), Data of each channel can be distributedly output.

Meanwhile, a fourth embodiment in which distributed data are output in a manner of sequentially delaying and outputting data signals output from an output buffer with a predetermined time difference will be described below with reference to FIGS. 8 to 10.

FIG. 8 is a block diagram of a fourth embodiment according to the present invention. As shown therein, the data output control unit 810, the first and second delay units 820 and 830, and the first and second output buffer units 840 are shown. ), 850 is configured.

The data output controller 810 outputs a switching control signal for controlling the switching operation of each of the multiplexers MUX provided in the first and second output buffer units 840 and 850.

The first delay unit 820 sequentially delays each of the switching control signals output from the data output control unit 810 by a unit delay time (“t” in FIG. 10), and each of the delayed switching control signals is delayed. The output is output to the multiplexer (MUX) of the output buffer unit 840. Similarly, the second delay unit 830 sequentially delays each switching control signal output from the data output control unit 810 by a unit delay time, and each of the delayed switching control signals is output to the second output buffer unit ( 850 is output to the corresponding multiplexer (MUX).

In the present embodiment, the delayed output switching control signal as described above is sequentially output to two outer (left and right) channel directions with respect to the center channel.

To this end, the first delay unit 820 delays the switching control signal output from the data output control unit 810 as described above and is provided in the first output buffer unit 840 on one side (for example, the left side). Sequentially output to the multiplexer (MUX) of, from the multiplexer (MUX) located in the center portion to the leftmost multiplexer (MUX) sequentially output.

Similarly, the second delay unit 830 delays each switching control signal output from the data output control unit 810 as described above and is provided in the second output buffer unit 840 on the other side (for example, the right side). The multiplexers are sequentially output to the multiplexers (MUX), but are sequentially output from the multiplexer (MUX) located at the center to the multiplexer (MUX) located at the rightmost side.

Accordingly, each of the multiplexers MUX included in the first output buffer unit 840 selects analog data signals output from a pair of amplifiers AMP as switching control signals sequentially delayed as described above. Since the data is output to the corresponding channel OUTPUT, the data signals of each channel are output in a delayed form as the switching control signal.

For example, the multiplexer MUX located at the center among the multiplexers MUX provided in the first output buffer unit 840 includes a switching control signal that is not delayed as shown in FIG. A switching control signal as shown in FIG. 10C is delayed by t compared to a non-switched switching control signal. Accordingly, the central multiplexer MUX first outputs the analog data signal without delaying the analog data signal and then delays the remaining analog data signal by t to output it to the second channel. The rest of the multiplexers (MUX) also sequentially delay the analog data signal by t and output it to the corresponding channel, and the analog data signal delayed by t further toward the leftmost channel direction is output.

10A is a waveform diagram of a source out enable signal SOE, and FIGS. 10B to 10E show data signals of respective channels through the multiplexers MUX as described above. This is a waveform diagram showing output delayed sequentially. That is, the waveform diagram shows that the source out enable signal SOE is sequentially delayed and output for t time as a whole.

To this end, the first delay unit 820 is provided with a plurality of delays, which can be easily implemented using a delay or a conventional delay as shown in FIG.

Since the second delay unit 830 and the second output buffer unit 850 operate with the first delay unit 820 and the first output buffer unit 840 with respect to the right channel with respect to the center channel. The data signals of the channels are also sequentially delayed by t as described above.

Meanwhile, FIG. 9 illustrates another embodiment, in which the data signals are sequentially delayed by t in the direction of the center channel from the outward channel to the center channel, and output.

That is, in the embodiment of FIG. 8, the first and second delay units 820 and 830 are disposed at the center portion of the channel, and the data signals are sequentially sequenced by t from the center channel to the leftmost and rightmost channel directions. Output with delay. On the other hand, in the embodiment of FIG. 9, the first and second delay units 920 and 930 are disposed on the left and right sides of the channel so that the data signals are sequentially sequentially by t from the leftmost and rightmost channels to the center channel direction. The difference is that the output is delayed.

Although the preferred embodiment of the present invention has been described in detail above, the scope of the present invention is not limited thereto, and may be implemented in various embodiments based on the basic concept of the present invention defined in the following claims. Such embodiments are also within the scope of the present invention.

210: shift register section
220A: First latch part
220B: second latch portion
230: input drive signal output unit
240: D / A converter
250: output buffer
810,910: data output control unit
820,920: First Delay Unit
830,930: Second delay
840,940: first output buffer unit
850,950: second output buffer unit

Claims (10)

A first latch unit sequentially latching data of each channel for driving the liquid crystal panel;
An input drive signal output unit configured to output an input drive signal;
A plurality of delayers serially connected to sequentially delay the input drive signal;
A second latch unit sequentially latching data of each channel latched in the first latch unit with a time difference by using input driving signals sequentially delayed through the plurality of delay units;
And a D / A converter converting data of each channel output from the second latch unit into an analog signal and outputting the analog signal to an output buffer.
A first latch unit sequentially latching data of each channel for driving the liquid crystal panel;
An input drive signal output unit configured to output an input drive signal to latch data latched to the first latch unit bit by bit;
A second latch unit sequentially latching data of each channel latched in the first latch unit bit by bit with a time difference by using the input drive signals output from the input drive signal output unit;
And a D / A converter converting data of each channel output from the second latch unit into an analog signal and outputting the analog signal to an output buffer.
3. The source driver of claim 2, further comprising a delay unit for delaying and outputting an output signal of the input driving signal output unit.
A first latch unit sequentially latching data of each channel for driving the liquid crystal panel;
An input drive signal output unit configured to output an input drive signal;
A plurality of delayers each receiving the input driving signal and sequentially delaying the input driving signal;
A second latch unit configured to sequentially latch data of each channel latched in the first latch unit with a time delay corresponding to the delayed delay amount by using the input driving signals delayed and output through the plurality of delay units;
And a D / A converter converting data of each channel output from the second latch unit into an analog signal and outputting the analog signal to an output buffer.
The liquid crystal display for reducing electromagnetic interference according to any one of claims 1, 2, and 4, wherein the first latch portion and the second latch portion are divided into two columns to operate simultaneously. Source driver.
The source driver of claim 1, 3, or 4, wherein the delay unit comprises an RC delay unit and an inverter.
7. The source driver of claim 6, wherein the capacitor, which is a component of the RC delay unit, is composed of a MOS transistor.
A data output controller for outputting a switching control signal for outputting a data signal to each data channel of the liquid crystal panel at a desired timing;
A first delay unit and a second delay unit configured to sequentially delay and output the switching control signal output from the data output controller for a preset time;
A first output buffer unit having a plurality of multiplexers for selecting an analog data signal output from an amplifier and outputting the same to a corresponding channel by a switching control signal sequentially delayed by the first delay unit;
And a second output buffer unit having a plurality of multiplexers for selecting an analog data signal output from the amplifier and outputting the analog data signal outputted from the amplifier according to the switching control signal sequentially delayed by the second delay unit. Source driver for liquid crystal display device for reducing electromagnetic interference.
The method of claim 8, wherein the first delay unit and the second delay unit output the switching control signals to the first output buffer and the second output buffer, respectively, in order from the center to the outer direction, or to the opposite direction. A source driver of a liquid crystal display device for reducing electromagnetic interference, characterized in that configured.
The liquid crystal display of claim 8, wherein the first output buffer and the second output buffer are configured to output data signals to the left and right channels based on one liquid crystal panel, respectively. Source driver.

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