CN112687223B - Source electrode driving circuit, source electrode driving method and display device - Google Patents
Source electrode driving circuit, source electrode driving method and display device Download PDFInfo
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- CN112687223B CN112687223B CN202011585343.0A CN202011585343A CN112687223B CN 112687223 B CN112687223 B CN 112687223B CN 202011585343 A CN202011585343 A CN 202011585343A CN 112687223 B CN112687223 B CN 112687223B
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Abstract
The invention provides a source electrode driving circuit, a source electrode driving method and a display device. The source driving circuit includes a delay controller for controlling values of n-th to m-th bits of second data to be inputted to the level shifter after a delay time elapses after values of 0-th to m-1-th bits of the second data are inputted to the level shifter; enabling the level shift circuit to firstly boost the first part of the second data to serve as a high-voltage data signal, and firstly driving the panel to reach the intermediate voltage of the gamma voltage corresponding to the second data by the output end according to the high-voltage data signal; after the delay time, boosting the rest part of the second data to synthesize a new high-voltage data signal, and driving the panel to the gamma voltage corresponding to the second data by the output end according to the new high-voltage data signal; the time-sharing conversion of high-voltage data is realized, voltage drop and noise of a level shift circuit are reduced, the output end drives the voltage in a segmented mode, the peak current of a source electrode driving circuit is reduced, the electromagnetic interference performance of the circuit is improved, and the noise level of a power supply is effectively reduced.
Description
Technical Field
The present invention relates to the field of display driving, and in particular, to a source driving circuit, a source driving method, and a display device.
Background
With the continuous development and progress of display technology, the demand of people for display is higher and higher. The high-end display market is now pursuing larger and larger display sizes, as well as higher and higher resolutions and faster response times, which demands the interface circuit of the display driver chip to have the capability of handling high data rates. However, large panel loads also require large driving capability of the output stage driving circuit, which may cause large power supply noise. In addition, when the level shifter converts the low-voltage data signal into the high-voltage data signal, and the output buffer drives the panel load, a voltage drop is generated on the high-voltage, so that the electromagnetic interference performance and the noise performance of the circuit are reduced.
Disclosure of Invention
The invention provides a source electrode driving circuit, a source electrode driving method and a display device, which can reduce the peak current of the source electrode driving circuit, thereby improving the electromagnetic interference performance of the circuit and effectively reducing the noise level of a power supply.
In order to achieve the purpose, the invention adopts the following scheme:
in one aspect, an embodiment of the present invention provides a source driving circuit, including a first latch, a second latch, a level shift circuit, and a digital-to-analog converter, where the first latch is configured to receive a data signal, store first data according to a first latch enable signal, and output the first data to the second latch, and the second latch is configured to store and output second data according to a second latch enable signal; the level shift circuit is used for boosting the second data and inputting a high-voltage data signal obtained by boosting into the digital-to-analog converter; the digital-to-analog converter is used for selecting and outputting corresponding gamma voltage according to the high-voltage data signal; the level shift circuit includes:
a level shifter and a delay controller;
the delay controller is used for controlling the values of the n th bit to the m th bit of the second data to be input into the level shifter after a delay time elapses after the values of the 0 th bit to the m-1 th bit of the second data are input into the level shifter, wherein m is less than or equal to n;
the level shifter is used for boosting the values of the 0 th bit to the m-1 th bit of the second data and outputting the values of the 0 th bit to the m-1 th bit of the boosted second data to the digital-to-analog converter;
the level shifter is further configured to boost the value of the nth to m bits of the second data after a delay time elapses, and output the boosted value of the nth to m bits of the second data to the digital-to-analog converter.
Optionally, a plurality of data lines corresponding to each bit of the second data are disposed between the second latch and the level shifter, and the delay controllers are respectively disposed on data lines corresponding to n-th to m-th bits of the second data.
Optionally, the source driving circuit further includes an operational amplifier and a multiplexer;
the operational amplifier is used for receiving the gamma voltage signal output by the digital-to-analog converter and outputting the gamma voltage signal to the multiplexer;
the multiplexer is used for receiving an output enable signal and driving a panel load to the corresponding gamma voltage according to the output of the operational amplifier;
the delay time is such that values of the nth bit to the mth bit of the second data are updated between the output enable signal rising edge and the first latch enable signal rising edge.
Optionally, the m is equal to n, and n is the most significant bit of the second data.
Optionally, m is equal to n-1, and n is the most significant bit of the second data.
In one aspect, an embodiment of the present invention provides a method applied to the source driver circuit provided in the embodiment of the present invention, including:
receiving a data signal through a first latch, storing first data according to a first latch enabling signal and outputting the first data to a second latch;
storing second data according to the second latch enable signal and outputting the second data to the level shifter; inputting the values of the n-th to m-th bits of the second data into the level shifter after a delay time elapses after the values of the 0-th to m-1-th bits of the second data are input into the level shifter by a delay controller, wherein m is less than or equal to n;
receiving the 0 th to m-1 th bit values of the second data through the level shifter, boosting the values to obtain first boosted data, and outputting the 0 th to m-1 th bit values of the boosted second data to a digital-to-analog converter;
and after the delay time, receiving and boosting the values of the n th bit to the m th bit of the second data through the level shifter, and outputting the boosted values of the n th bit to the m th bit of the second data to the digital-to-analog converter.
Optionally, the method further includes:
selecting the gamma voltage corresponding to the high-voltage data signal through the digital-to-analog converter and outputting the gamma voltage to an operational amplifier;
outputting the gamma voltage signal output by the analog-to-digital converter to a multiplexer through the operational amplifier;
inputting an output enable signal to the multiplexer to drive a panel load to the corresponding gamma voltage according to the gamma voltage signal through the multiplexer;
the delay time is such that the values of the nth through mth bits of the second data are updated between the rising edge of the output enable signal and the rising edge of the first latch signal.
Optionally, the source driving method includes that m is n, and n is a most significant bit of the second data.
Optionally, the source driving method includes that m is n-1, and n is a most significant bit of the second data.
In one aspect, an embodiment of the present invention provides a source driving apparatus, including:
the first processing module is used for receiving the data signal through the first latch, storing first data according to the first latch enabling signal and outputting the first data to the second latch;
the second processing module is used for storing second data according to the second latch enabling signal and outputting the second data to the level shifter;
a third processing module, configured to enable the value of the 0 th bit to the m-1 th bit of the second data to be input to the level shifter through a delay time after the value of the 0 th bit to the m-1 th bit of the second data is input to the level shifter through the delay controller, where m is less than or equal to n;
the fourth processing module is used for receiving the values of the 0 th bit to the m-1 th bit of the second data through the level shifter, boosting the values and outputting the boosted values of the 0 th bit to the m-1 th bit of the second data to the digital-to-analog converter;
and the fifth processing module is used for receiving and boosting the values of the n th bit to the m th bit of the second data through the level shifter after the delay time elapses, and outputting the boosted values of the n th bit to the m th bit of the second data to the digital-to-analog converter.
In one aspect, an embodiment of the present invention provides a source driving chip, including any one of the source driving circuits provided in the embodiments of the present invention.
In one aspect, an embodiment of the present invention provides a display device, including the source driver chip provided in the embodiment of the present invention.
The technical scheme provided by the embodiment of the invention has the beneficial effects that at least: according to the source driving circuit provided by the invention, the delay controller is added between the second latch of the source driving circuit and the level shifter, so that the values of the n th bit to the m th bit of the second data are controlled to be input into the level shifter after the value of the 0 th bit to the m-1 th bit of the second data is input into the level shifter for delay time; the level shift circuit converts part of the second data into high-voltage data signals, and the output end drives the high-voltage data signals to the intermediate voltage of the gamma voltage corresponding to the second data; after the delay time, the rest part of the second data is converted, and the output end is driven to the gamma voltage corresponding to the second data according to the refreshed high-voltage data signal; the voltage drop and the noise generated by the level shift circuit and the output end are reduced, and the peak current of the source electrode driving circuit can be reduced, so that the electromagnetic interference performance of the circuit can be improved, and the noise level of the power supply is effectively reduced.
Drawings
Fig. 1 is a schematic diagram of a source driving circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a source driving circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a source driver circuit according to an embodiment of the present invention;
FIG. 4 is a timing diagram of a source driver circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a source driving circuit according to an embodiment of the present invention;
FIG. 6 is a timing diagram of a source driver circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a source driving circuit according to an embodiment of the present invention;
FIG. 8 is a timing diagram of a source driver circuit according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a source driving circuit according to an embodiment of the present invention;
FIG. 10 is a flowchart of a method for providing a source driver circuit according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a source driving device according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a source driving device according to an embodiment of the present invention;
fig. 13 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
description of reference numerals:
101-first latch, 102-second latch, 103-level shift circuit, 1031-level shifter, 1032-delay controller, 104-digital-to-analog converter, 105-operational amplifier, 106-multiplexer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without making any creative effort, fall within the scope of protection of the invention.
The terms first, second and the like in the description and in the claims of the present invention are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the invention may be practiced other than those illustrated or described herein, and that the objects identified as "first," "second," etc. are generally a class of objects and do not limit the number of objects, e.g., a first object may be one or more. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
Furthermore, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a schematic diagram of a source driver circuit provided by an embodiment of the present invention is shown, where the source driver circuit includes a first latch 101, a second latch 102, a level shift circuit 103, and a digital-to-analog converter 104, the first latch 101 is configured to receive a data signal, store first data according to a first latch enable signal, and output the first data to the second latch 102, and the second latch 102 is configured to store and output second data according to a second latch enable signal; the level shift circuit 103 is configured to boost the second data, and input a high-voltage data signal obtained by boosting the second data to the digital-to-analog converter 104; the digital-to-analog converter 104 is configured to select and output a corresponding gamma voltage according to the high-voltage data signal; the level shift circuit 103 includes:
a level shifter 1031 and a delay controller 1032;
the delay controller 1032 is configured to control the n-th to m-th bit values of the second data to be input to the level shifter 1031 after a delay time elapses after the 0-th to m-1-th bit values of the second data are input to the level shifter 1031, where m is less than or equal to n;
the level shifter 1031 is configured to boost the values of the 0 th bit to the m-1 th bit of the second data, and output the boosted values of the 0 th bit to the m-1 th bit of the second data to the digital-to-analog converter 104;
the level shifter 1031 is further configured to boost the values of the n-th to m-th bits of the second data after the delay time elapses, and output the boosted values of the n-th to m-th bits of the second data to the digital-to-analog converter 104.
Specifically, in fig. 1, LAT1EN is a first latch enable signal, LAT2EN is a second latch enable signal, the second latch 102 is connected to the digital-to-analog converter 104 through a level shift circuit 103, the second data is boosted through the level shift circuit, and the level shift circuit 103 includes a level shifter 1031 and a delay controller 1032.
Specifically, referring to FIG. 1, the input DATA DATA0[ n:0] is a binary DATA signal, the binary number is usually calculated from the zeroth bit, so DATA0[ n:0] has 0, 1, 2, … …, n bits, such as DATA0[5:0], representing the values of the 0 th bit to the 5 th bit of the 6-bit binary DATA of the input DATA, DATA1[ 7:0] representing the 0 th bit to the 7 th bit of the 8-bit binary DATA of the first DATA, and DATA2[ 7] representing the 7 th bit of the second DATA. The 'bus' and the corresponding number on each module circuit connection line in fig. 1 indicate the number of DATA channels between two modules, e.g., the 0 th bit to the n th bit of the input DATA [ n:0] transferred between the first latch 101 and the second latch 102 are n +1 DATA channels.
The delay controller 1032 controls the time for inputting the nth to mth bit values of the second data into the 1031 of the level shifter, so that the nth to mth bit values of the second data are input into the 1031 of the level shifter after being delayed, thereby realizing that the level shifter boosts the 0 th to m-1 bit values of the second data and outputs the boosted values to the digital-to-analog converter 104, and after the delay time, the level shifter boosts the nth to mth bit values of the second data and outputs the boosted values to the digital-to-analog converter 104; therefore, the level shifter can boost partial data of the second data first and then boost the rest data of the second data, thereby reducing the voltage drop and the noise generated by the level shift circuit.
Therefore, the gamma voltage selected by the dac 104 through the high voltage data signal before the delay time corresponds to bits 0 to m-1 of the second data, and after the delay time, according to the refreshed high voltage data signal, the gamma voltage selected by the dac 104 corresponds to bits 0 to n of the second data, that is, before the delay time, the dac 104 selects the gamma voltage corresponding to the intermediate value of the second data, and after the delay time, the dac 104 selects the gamma voltage corresponding to the second data, and since the dac 104 is connected to the output terminal, the output point is driven to the intermediate value of the gamma voltage corresponding to the second data first, and then driven to the gamma voltage corresponding to the second data after the delay time.
For example: referring to fig. 2, when m is 5 and n is 5, if the X-th row input DATA0[5:0] is 000000 (gray scale value 0), and the X + 1-th row input DATA0[5:0] is 110001 (gray scale value 49), DATA1[5:0] is 110001 (gray scale value 49), and DATA2[5:0] is 010001 (gray scale value 17) at the time of the OEN rising edge, the level shifter 1031 converts DATA2[5:0] < 010001 into the first boosted voltage DATA as the high voltage DATA signal DHV [5:0] < 010001, and the dac 104 receives the high voltage DATA signal and selects the gray scale voltage corresponding to DATA2[5:0] < 010001 (gray scale value 17) and outputs the selected gray scale voltage to the output terminal, and the output terminal drives the panel to the gamma voltage corresponding to the gray scale value 17; after the delay time, the level shifter 1031 receives DATA2[5] in the X +1 th row and converts it into the second boosted DATA, before which DATA2[5] holds the 0 value in the X-th row, the delayed high-voltage DATA signal DHV [5:0] is updated to 110001, and the dac 104 receives the new high-voltage DATA signal and selects a gray-scale voltage corresponding to DATA2[5:0] being 110001 (gray-scale value 49) and outputs it to the output terminal.
If the DATA to be delayed changes in the front row and the rear row (in the circuit shown in fig. 2, DATA1[5] in the X-th row and the X + 1-th row are different), the voltage drop of the level shifter 103 will be reduced, and the source driving circuit provided by the present invention achieves the technical effect of the segment driving; if the DATA to be delayed does not change in the preceding and following rows (for example, DATA1[5] in the X-th row and X + 1-th row are both 1), it is equivalent to that the input DATA in the preceding and following rows have little change and no obvious voltage change because the DATA to be delayed does not change, and this time, it is equivalent to that the output end is directly driven to the target voltage.
Thus, it is achieved that the output first drives the panel to an intermediate voltage of DATA2[5:0 ]. After the delay time, the DATA is driven to the gamma voltage corresponding to DATA2[5:0], which can reduce the voltage drop and noise generated by the level shift circuit and reduce the voltage drop and noise generated by the output circuit, specifically referring to the timing diagram shown in fig. 3, S1 is the change of the output voltage and the change of the VDDA high voltage power terminal, arrow 36 indicates the voltage drop caused by the level shift circuit, arrow 37 indicates that the voltage drop of the VDDA high voltage power terminal is smaller when the output terminal is driven to the intermediate voltage first and then driven to the target voltage, compared with the voltage drop of the VDDA high voltage power terminal directly driven to the target voltage (e.g., gamma voltage 49 corresponding to the second DATA), referring to fig. 4, the timing diagram when no delay controller is added between the second latch 102 and the level shifter 1031, and the voltage drop of the VDDA high voltage power terminal is larger when the VDDA high voltage power terminal is driven, as indicated by arrow 37.
Optionally, a plurality of data lines corresponding to each bit of the second data are disposed between the second latch 102 and the level shifter 1031, and the delay controllers 1032 are respectively disposed on the data lines corresponding to the n-th to m-th bits of the second data.
Specifically, referring to fig. 2, when m is 5, n is 5, and the input DATA0[5:0] is 110001 (gray scale value 49), 6 DATA lines are provided between the second latch 102 and the level shifter 1031, respectively corresponding to bits 0, 1, 2, 3, 4, and 5 of the second DATA, and when m is 5, the 5 th bit of the second DATA is delayed, so that the delay controller 1032 is provided on the DATA line (channel) where the 5 th bit of the second DATA is located, and if m is 4, it is necessary to delay the 4 th to 5 th bits of the second DATA, the delay controller is provided on the DATA line where the 4 th to 5 th bits of the second DATA are located.
The delay controller can determine a specific delay time value according to the presetting, so that the level shifter can realize step-by-step boosting of high-voltage data, voltage drop and noise influence caused by the level shift circuit during boosting are reduced, sectional driving of the output end is realized, the voltage drop and noise influence caused by the output end during driving of panel load voltage are reduced, peak current of the source electrode driving circuit can be reduced, and performance and temperature during operation are more stable.
Optionally, the source driving circuit further includes an operational amplifier 105 and a multiplexer 106;
the operational amplifier 105 is configured to receive the gamma voltage signal output by the digital-to-analog converter 104 and output the gamma voltage signal to the multiplexer 106;
the multiplexer 106 is configured to receive an output enable signal and drive a panel load to the corresponding gamma voltage according to the output of the operational amplifier 105;
the delay time is such that values of the nth bit to the mth bit of the second data are updated between the output enable signal rising edge and the first latch enable signal rising edge.
Specifically, the output port of the source driving circuit is usually provided with an operational amplifier for output buffering, the gamma voltage signal corresponding to the gray-scale value of the high-voltage data signal DHV output by the digital-to-analog converter is input to the multiplexer through the operational amplifier, and finally, the voltage is output by the multiplexer to drive the panel voltage to the corresponding gamma voltage.
Referring to fig. 2, an arrow 31 indicates a rising edge of the second latch enable signal LAT2EN, an arrow 32 indicates a rising edge of the output enable signal OEN, an arrow 33 indicates that the 5 th bit of the second data enters the level shifter after a delay time, an arrow 38 indicates a rising edge of the first latch enable signal LAT1EN, 34 indicates an input signal of the first latch 101 of the X +1 th row of the channel, and 35 indicates an input signal of the first latch 101 of the X +2 th row of the channel. The delay time needs to be such that the data (the nth bit to the mth bit of the second data) that needs to be delayed is updated between the rising edge of the OEN signal and the rising edge of the LAT1 EN.
Optionally, the m is equal to n, and n is the most significant bit of the second data.
Specifically, when n is 7 and m is 7, the input DATA0[ 7:0] is an 8-bit binary number, and thus DATA2[7:0] is also an 8-bit binary number, having 0, 1, 2, 3, 4, 5, 6, and 7 bits in total, and the values of the n-th to m-th bits of the second DATA are DATA2[ 7], which is the highest bit of the second DATA; similarly, when n is 5 and m is 5, the second DATA is a 6-bit binary number DATA2[5:0], and the values of the n-th to m-th bits of the second DATA are DATA2[5], which are the most significant bits of the second DATA.
Optionally, the m is n-1, and the delay data is the most significant bit and the second most significant bit of the second data.
Specifically, when n is 7 and m is 6, the values of the n-th to m-th bits of the second DATA are DATA2[7: 6], that is, the 7-th to 6-th bits of the second DATA are the most significant bit and the next highest bit of the second DATA, and the values of the 0-th to m-1-th bits of the second DATA are DATA2[5:0] of the 0-th to 5-th bits.
The operation of the source driving circuit provided by the present invention is further explained with reference to fig. 2 and fig. 3:
when the column sync signal TP is active high, the output enable signal OEN is turned to low, the output multiplexer 106 is turned off, and the source driver outputs S1 and keeps floating or performs charge sharing according to other control signals.
In a high period of the row sync signal TP, the second latch enable signal LAT2EN is asserted, latching the output DATA1[5:0] of the first latch of the X-th row into the second latch as the output DATA2[5:0] of the second latch of the X-th row.
The level shift circuit boosts the output DATA2[4:0] of the second latch of the X-th row to convert into a high-voltage DATA signal DHV [4:0] of the X-th row.
The high voltage data signals DHV [4:0] of column X and DHV [5] of column X-1 select an intermediate gamma gray scale voltage as the intermediate input voltage signal of the output operational amplifier according to the data value. The intermediate voltage is an intermediate value between the gamma voltage corresponding to the input data of row X-1 and the gamma voltage corresponding to the input data of row X, and the value of the high voltage data signal DHV [5:0] is between the two.
When the row sync signal TP is at a low level, the output multiplexer control signal OEN is turned to a high level and turns on the output multiplexer, and the output of the output buffer drives the panel load to an intermediate voltage.
After a certain delay, the DATA2[5] of the X-th row is converted into a high-voltage DATA signal DHV [5] of the X-th row through a level shifter and combined with the high-voltage DATA signal DHV [4:0] of the X-th row to form a new DHV [5:0] of the X-th row, a target gamma gray scale voltage is selected according to the DATA value of the DHV [5:0] of the X-th row, and the panel load is driven to the target voltage corresponding to the input DATA of the X-th row.
After a period of time, the enable signal LAT1EN of the first stage latch will latch the input DATA signals DATA0[5:0] of row X +1 into the first stage latch.
The above process is repeated.
It should be noted that the schematic diagram provided in fig. 2 is only one input data, and referring to fig. 9, in practical use, parallel multi-path data driving circuits are provided according to the resolutions of different display devices.
The beneficial effects brought by the source electrode driving circuit at least comprise: controlling the values of the n-th to m-th bits of the second data to be input to the level shifter after a delay time elapses after the values of the 0-th to m-1-th bits of the second data are input to the level shifter by adding a delay controller between a second latch of a source driving circuit and the level shifter; the level shift circuit boosts a part of the second data to be used as a high-voltage data signal, and meanwhile, the output end drives the panel to reach the middle voltage of gamma voltage corresponding to the second data according to the high-voltage data signal; after the delay time, boosting the rest part of the second data, refreshing the high-voltage data signal, and driving the panel to the gamma voltage corresponding to the second data by the output end according to the new high-voltage data signal; by adding the delay controller, high-voltage data are converted in a time-sharing mode, voltage drop and noise generated by the level shift circuit and the output end are reduced, the output end is driven in a segmented mode, peak current of the source electrode driving circuit can be reduced, electromagnetic interference performance of the circuit can be improved, and power supply noise level is effectively reduced.
For example, referring to fig. 5, a source driving circuit according to an embodiment of the present invention is provided, where n is 5, m is 4, and the delay DATA is the fifth bit and the fourth bit DATA2[5:4] of the second DATA, and the source driving circuit according to an embodiment of the present invention is further described with reference to fig. 5:
assuming that DATA0[5:0] of the X-1 th row is 000000, the first latch 101 receives the DATA0[5:0] of the X-1 th row to 111001, stores the first DATA1[5:0] according to the first latch enable signal LAT1EN, and outputs the same to the second latch 102, and the second latch 102 stores and outputs the same to the level shifter 1031 according to the second latch signal.
The second latch signal includes a second latch enable signal LAT2EN, and the second latch 102 stores bits 0 to 5 of the received first DATA1[5:0] as a value DATA2[5:0] ═ 111001 of bits 0 to 5 of the second DATA according to the second latch enable signal LAT2EN, where DATA2[ 3:0] ═ 1001 and DATA2[5:4] of the X-1 th row constitute DATA2[5:0] ═ 001001001 to enter the level shifter 1031 first, and a delay controller 1032 is provided on a DATA line of the DATA2[5:4], and it is necessary that DATA2[5:4] of the X-th row enters the level shifter 1031 after a delay time elapses.
The level shifter 1031 boosts DATA2[ 3:0] to obtain first boosted DATA, outputs DHV [5:0] ═ 001001 as a high-voltage DATA signal, and forms DHV [5:0] ═ 001001 with the highest-order upper bit of the previous row (X-1 th row), the dac 104 selects a gamma voltage corresponding to a gray-scale value 9 to output to the operational amplifier 105 according to the high-voltage DATA signal DHV [5:0] ═ 001001 (gray-scale value 9), the multiplexer receives an output enable signal and outputs a driving voltage, and the display panel is driven to a gamma voltage corresponding to the gray-scale value 9.
After the delay time, the level shifter 1031 further boosts the DATA2[5:4] to obtain second boosted DATA, the refreshed high-voltage DATA signal DHV [5:0] is 111001 (gray scale value 57) and is output to the digital-to-analog converter 104, the digital-to-analog converter 104 selects the gamma voltage corresponding to the gray scale value 57 according to the high-voltage DATA signal and outputs the gamma voltage to the operational amplifier 105, the multiplexer receives the output enable signal and outputs the driving voltage, and the display panel is driven to the gamma voltage corresponding to the gray scale value 57 first, so that the source driving circuit shown in fig. 5 drives the panel voltage to the gamma voltage corresponding to the gray scale 9 first and drives the gamma voltage corresponding to the gray scale value 57 after the delay time elapses with respect to the input DATA0[5:0] 111001, and fig. 6 shows a timing diagram of the source driving circuit shown in fig. 5.
Exemplarily, referring to fig. 7, the source driving circuit according to the embodiment of the present invention, where n is 5, m is 4, and the delay DATA is the fifth and fourth bits DATA2[5:4] of the second DATA, is different from the source driving circuit shown in fig. 5 in that the fifth and fourth bits of the second DATA of the circuit shown in fig. 7 are not synchronously delayed, but the delay controller 1032 delays the fourth bit DATA2[4] of the second DATA first and then delays the fifth bit DATA2[5] of the second DATA, for example: when the input DATA0[5:0] ═ 111001, DATA2[ 3:0] ═ 1001, DATA2[4] ═ 1, DATA2[5] ═ 1, the level shifter 1031 boosts DATA2[ 3:0] ═ 1001 to obtain first boosted DATA, when the high-voltage DATA signal DHV [5:0] ═ 001001, after a first delay time, raises DATA2[4] ═ 1 to obtain second boosted DATA, the refreshed high-voltage DATA signal DHV [5:0] 011001, after a second delay time, raises DATA2[5] = 1 to obtain third boosted DATA, when the refreshed high-voltage DATA signal DHV [5:0] ═ 111001, fig. 8 shows the gray scale of the source driver circuit shown in fig. 7, the output terminal is driven to the gray scale corresponding to the gamma voltage of DHV [5:0] ═ 111001 (DHV 001001), and the output terminal is driven to the gamma voltage corresponding to the gamma voltage [5:0] = (DHV [5: 0) which is equal to 9), the second delay time is followed by driving to a gamma voltage of DHV [5:0] ═ 111001 (corresponding to gray level 57).
In one aspect, referring to fig. 10, an embodiment of the present invention provides a source driving method, which is applied to the source driving circuit according to the embodiment of the present invention, and the method includes:
1001, receiving a data signal through a first latch, storing first data according to a first latch enable signal, and outputting the first data to a second latch;
Optionally, the method further includes:
selecting the gamma voltage corresponding to the high-voltage data signal through the digital-to-analog converter and outputting the gamma voltage to an operational amplifier;
outputting the gamma voltage signal output by the analog-to-digital converter to a multiplexer through the operational amplifier;
inputting an output enable signal to the multiplexer to drive a panel load to the corresponding gamma voltage according to the gamma voltage signal through the multiplexer;
the delay time is between a rising edge of the output enable signal and a rising edge of the first latch signal.
Through the step 1003, the level shifter can boost partial data of the second data, and boost the rest data of the second data after the delay time, so that the voltage drop and the noise influence caused by the boost of the level shifter are reduced.
Through steps 1004 and 1005, the dac can receive a part of the high voltage data signals of the target voltage (the gamma voltage corresponding to the second data) first to select the middle voltage of the gamma voltage corresponding to the second data, and then select the gamma voltage corresponding to the second data after a delay time, so that the output end can drive the display panel to the middle value of the target voltage first and then to the target voltage, thereby avoiding the excessive voltage drop and noise caused by driving to the target voltage at one time, and improving the circuit performance.
Optionally, the source driving method includes that m is n, and n is a most significant bit of the second data.
Optionally, the source driving method includes that m is n-1, and n is a most significant bit of the second data.
Particularly, if the change of the most significant bit MSB indicates a large change amount of the output, which causes a large voltage drop, in order to stably operate the source driving circuit, the method provided by the present invention has an excellent technical effect, and if the MSB does not change, it indicates that the output change is reduced, and the voltage drop caused by the MSB is also small.
The values of m and n are already described in the embodiments of the source driver circuit portion, and are not described herein again.
In one aspect, referring to fig. 11, an embodiment of the invention provides a source driving device 110, including:
the first processing module 1101 is configured to receive a data signal through a first latch, store first data according to a first latch enable signal, and output the first data to a second latch;
the second processing module 1102 is configured to store second data according to the second latch enable signal and output the second data to the level shifter;
a third processing module 1103, configured to enable, after a delay time elapses after the values of the 0 th to m-1 th bits of the second data are input to the level shifter, the values of the n th to m th bits of the second data are input to the level shifter by using a delay controller, where m is less than or equal to n; a fourth processing module 1104, configured to receive and boost the 0 th to m-1 th bit values of the second data through the level shifter, and output the boosted 0 th to m-1 th bit values of the second data to a digital-to-analog converter;
a fifth processing module 1105, configured to receive and boost the n-th to m-th bit values of the second data through the level shifter after a delay time elapses, and output the boosted n-th to m-th bit values of the second data to the digital-to-analog converter.
Optionally, referring to fig. 12, the source driving device 110 further includes:
a sixth processing module 1106, configured to select, through the digital-to-analog converter, a gamma voltage corresponding to the high-voltage data signal and output the gamma voltage to an operational amplifier;
a seventh processing module 1107, configured to output the gamma voltage signal output by the analog-to-digital converter to a multiplexer through the operational amplifier;
an eighth processing module 1108, configured to input an output enable signal to the multiplexer, so as to drive a panel load to the corresponding gamma voltage according to the gamma voltage signal through the multiplexer;
the delay time is between a rising edge of the output enable signal and a rising edge of the first latch signal.
The source driving device provided by the invention can realize each process of the embodiment of the source driving method, can achieve the same technical effect, and is not repeated herein for avoiding repetition.
On one hand, the embodiment of the invention also provides a source driving chip, which comprises any one of the source driving circuits provided by the embodiment of the invention.
On one hand, the embodiment of the invention also provides a display device, which comprises the source driving chip provided by the embodiment of the invention.
Referring to fig. 13, an electronic device 1300 according to an embodiment of the present invention includes a processor 1301, a memory 1302, and a computer program stored in the memory 1302 and capable of running on the processor 1301, where the computer program is executed by the processor 1301 to implement the processes of the embodiment of the source driving method, and can achieve the same technical effects, and therefore, the descriptions thereof are omitted here to avoid repetition.
An embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements each process of the embodiment of the source driving method, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here. The computer-readable storage medium may be a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (12)
1. A source driving circuit comprises a first latch, a second latch, a level shift circuit and a digital-to-analog converter, wherein the first latch is used for receiving a data signal, storing first data according to a first latch enabling signal and outputting the first data to the second latch, and the second latch is used for storing and outputting second data according to a second latch enabling signal; the level shift circuit is used for boosting the second data and inputting a high-voltage data signal obtained by boosting into the digital-to-analog converter; the digital-to-analog converter is used for selecting and outputting corresponding gamma voltage according to the high-voltage data signal; wherein the level shift circuit comprises:
a level shifter and a delay controller;
the delay controller is used for controlling the values of the n-th to m-th bits of the second data to be input into the level shifter after a delay time elapses after the values of the 0-th to m-1-th bits of the second data are input into the level shifter, wherein m is less than or equal to n;
the level shifter is used for boosting the values of the 0 th bit to the m-1 th bit of the second data and outputting the values of the 0 th bit to the m-1 th bit of the boosted second data to the digital-to-analog converter;
the level shifter is further configured to boost the value of the nth to m bits of the second data after a delay time elapses, and output the boosted value of the nth to m bits of the second data to the digital-to-analog converter.
2. The source driver circuit as claimed in claim 1, wherein a plurality of data lines are provided between the second latch and the level shifter corresponding to each bit of the second data, and the delay controllers are respectively provided on the data lines corresponding to the n-th to m-th bits of the second data.
3. The source driver circuit of claim 1, further comprising an operational amplifier and a multiplexer;
the operational amplifier is used for receiving the gamma voltage signal output by the digital-to-analog converter and outputting the gamma voltage signal to the multiplexer;
the multiplexer is used for receiving an output enable signal and driving a panel load to the corresponding gamma voltage according to the output of the operational amplifier;
the delay time is such that values of nth through mth bits of the second data are updated between a rising edge of the output enable signal and a rising edge of the first latch enable signal.
4. The source driver circuit of claim 1, wherein m = n, and n is a most significant bit of the second data.
5. The source driver circuit of claim 1, wherein m = n-1, and n is a most significant bit of the second data.
6. A source driving method applied to the source driving circuit according to any one of claims 1 to 5, comprising:
receiving a data signal through a first latch, storing first data according to a first latch enabling signal and outputting the first data to a second latch;
storing second data through the second latch according to a second latch enabling signal and outputting the second data to the level shifter;
after the values of the 0 th bit to the m-1 th bit of the second data are input into the level shifter through a delay controller, enabling the values of the n th bit to the m th bit of the second data to be input into the level shifter after a delay time, wherein m is smaller than or equal to n;
receiving and boosting the 0 th to m-1 th bit values of the second data through the level shifter, and outputting the boosted 0 th to m-1 th bit values of the second data to the digital-to-analog converter;
and after the delay time, receiving and boosting the values of the n th bit to the m th bit of the second data through the level shifter, and outputting the boosted values of the n th bit to the m th bit of the second data to the digital-to-analog converter.
7. The source driving method of claim 6, further comprising:
selecting the gamma voltage corresponding to the high-voltage data signal through the digital-to-analog converter and outputting the gamma voltage to an operational amplifier;
outputting the gamma voltage signal output by the analog-to-digital converter to a multiplexer through the operational amplifier;
inputting an output enable signal to the multiplexer to drive a panel load to the corresponding gamma voltage according to the gamma voltage signal through the multiplexer;
the delay time is such that values of the nth bit to the mth bit of the second data are updated between the output enable signal rising edge and the first latch enable signal rising edge.
8. The source driving method of claim 6, wherein m = n, and n is the most significant bit of the second data.
9. The source driving method of claim 6, wherein m = n-1, and n is a most significant bit of the second data.
10. A source driving apparatus, comprising:
the first processing module is used for receiving the data signal through the first latch, storing first data according to the first latch enabling signal and outputting the first data to the second latch;
the second processing module is used for storing second data according to the second latch enabling signal and outputting the second data to the level shifter;
a third processing module, configured to enable a value of an nth bit to an m-th bit of the second data to be input to the level shifter after a delay time elapses after a value of a0 th bit to an m-1 th bit of the second data is input to the level shifter through the delay controller, where m is less than or equal to n;
the fourth processing module is used for receiving and boosting the values of the 0 th bit to the m-1 th bit of the second data through the level shifter and outputting the boosted values of the 0 th bit to the m-1 th bit of the second data to the digital-to-analog converter;
and the fifth processing module is used for receiving and boosting the values of the n th bit to the m th bit of the second data through the level shifter after the delay time elapses, and outputting the boosted values of the n th bit to the m th bit of the second data to the digital-to-analog converter.
11. A source driving chip, comprising the source driving circuit as claimed in any one of claims 1 to 5.
12. A display device comprising the source driver chip according to claim 11.
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