CN109410822B - Voltage level conversion circuit and display panel drive control method - Google Patents
Voltage level conversion circuit and display panel drive control method Download PDFInfo
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Abstract
The invention provides a voltage level conversion circuit and a display panel driving control method. The voltage level conversion circuit is coupled to a plurality of data lines in the display panel through a multiplexer. The voltage level conversion circuit comprises a voltage level conversion unit and a control unit. The voltage level conversion unit is coupled to the multiplexer and respectively receives a first voltage level, a second voltage level and a third voltage level, wherein the third voltage level is higher than the second voltage level and the second voltage level is higher than the first voltage level. The control unit is coupled to the voltage level conversion unit and used for selectively controlling the voltage level conversion unit to output a first voltage level or a second voltage level to the multiplexer according to the voltage level of the timing control signal.
Description
Technical Field
The present invention relates to a display device, and more particularly, to a voltage level converting circuit and a display panel driving control method.
Background
Generally, the source driver outputs of a display device can be coupled to a plurality of Data lines (Data lines) of a display panel through multiplexers, for example, as shown in fig. 1, two source driver outputs SO1 and SO2 can be coupled to four Data lines DL1 to DL4 through different multiplexers MUXA and MUXB, respectively.
As shown in fig. 2, at the moment when the multiplexer MUXA or MUXB is turned on (for example, at time t2 and t4), the data signal SDAT output by the source driver has a Voltage drop (Voltage drop) phenomenon, as shown by the dotted circle in fig. 2, which causes the problem of insufficient charging rate of the pixels (pixels) of the display panel.
As shown in fig. 3, at the moment when the multiplexer MUXA is turned on (for example, at time t2), the fan-out unit FO1 that has been fully charged by the source driver output SO1 is coupled to the data line DL1 that has no voltage at the rear end through the multiplexer MUXA, and due to a relatively large voltage difference between the two, a large current is instantaneously generated in the data line DL1, thereby causing the touch panel noise TPN to be instantaneously increased. Similarly, a similar situation occurs at the instant when the multiplexer MUXB is turned on (e.g., time t 4). At the moment when the mux MUXA or MUXB is turned off (e.g., at times t3 and t5), the touch panel noise TPN is also increased.
As shown in fig. 4, for example, in the source driver output SO1, the conventional operation timing is to start the source driver output SO1 to output the data signal SDAT1 to charge the fan-out unit FO1 at time t1 by the falling edge of the timing control signal XSTB, and then start the multiplexer MUXA at time t2, SO that the data signal SDAT output by the source driver output SO1 can start to charge the data line DL1 in the display panel through the multiplexer MUXA.
From the foregoing, it can be seen that: at the instant when the multiplexer MUXA is turned on (i.e., at time t2), the data signal SDAT has a voltage drop and the data line DL1 has a large instantaneous current, so that the pixel charging rate of the display panel may be insufficient and a large instantaneous touch panel noise TPN may be generated.
However, since most of the conventional touch pens in the market are active pens, the above-mentioned large touch panel noise TPN is likely to cause the touch pen to be unable to operate on the touch panel smoothly, and thus a solution is needed.
Disclosure of Invention
Therefore, the present invention provides a voltage level converting circuit and a driving control method of a display panel to solve the above-mentioned problems encountered in the prior art.
An embodiment of the present invention is a display panel driving control method. In this embodiment, the display panel driving control method is used for driving a plurality of data lines in the display panel through the multiplexer.
The display panel driving control method comprises the following steps: (a) starting to precharge the multiplexer through a time sequence control signal at a first time, wherein the multiplexer receives a first voltage level at the first time; (b) at a second time, the multiplexer receives a second voltage level, wherein the second time is later than the first time and the second voltage level is higher than the first voltage level; and (c) at a third time, the multiplexer receives a third voltage level, wherein the third time is later than the second time and the third voltage level is higher than the second voltage level. The speed of the multiplexer rising from the second voltage level at the second time to the third voltage level at the third time is greater than the speed of the multiplexer rising from the first voltage level at the first time to the second voltage level at the second time.
In one embodiment, the step (a) is to precharge the multiplexer according to the rising edge trigger of the timing control signal.
In one embodiment, the step (c) further comprises: when the multiplexer receives the third voltage level, the pre-charging of the multiplexer is stopped.
In one embodiment, the multiplexer is in an off state at a first time.
In one embodiment, the multiplexer is in a partially open state at the second time.
In one embodiment, the multiplexer is in a fully open state at a third time.
In an embodiment, the display panel driving control method further includes the following steps: (d) and at the first time, the plurality of data lines are simultaneously triggered to start to be charged according to the time sequence control signal.
In one embodiment, the step (d) starts to charge the data lines according to the rising edge trigger of the timing control signal.
In an embodiment, the display panel driving control method further includes the following steps: triggering the multiplexer to start pre-discharging at a fourth time, wherein the fourth time is later than the third time and the multiplexer receives a third voltage level at the fourth time; at a fifth time, the multiplexer receives a fourth voltage level, wherein the fifth time is later than the fourth time and the fourth voltage level is lower than the third voltage level; and receiving the first voltage level by the multiplexer at a sixth time, wherein the sixth time is later than the fifth time and the first voltage level is lower than the fourth voltage level.
In one embodiment, the speed of the multiplexer decreasing from the fourth voltage level at the fifth time to the first voltage level at the sixth time is greater than the speed of the multiplexer decreasing from the third voltage level at the fourth time to the fourth voltage level at the fifth time.
Another embodiment according to the present invention is a voltage level shifting circuit. In this embodiment, the voltage level converting circuit is coupled to a plurality of data lines in the display panel through a multiplexer. The voltage level conversion circuit comprises a voltage level conversion unit and a control unit. The voltage level conversion unit is coupled to the multiplexer and respectively receives a first voltage level, a second voltage level and a third voltage level, wherein the third voltage level is higher than the second voltage level and the second voltage level is higher than the first voltage level. The control unit is coupled to the voltage level conversion unit and used for selectively controlling the voltage level conversion unit to output a first voltage level or a second voltage level to the multiplexer according to the voltage level of the timing control signal.
Another embodiment according to the present invention is a voltage level shifting circuit. In this embodiment, the voltage level converting circuit is coupled to a plurality of data lines in the display panel through a multiplexer. The voltage level conversion circuit comprises a voltage division unit, a voltage level conversion unit and a control unit. The voltage division unit respectively receives a first voltage level, a second voltage level and a third voltage level to generate a plurality of candidate voltage levels, wherein the third voltage level is higher than the second voltage level and the second voltage level is higher than the first voltage level. The voltage level conversion unit is coupled to the multiplexer and the voltage division unit respectively for receiving the candidate voltage levels. The control unit is coupled to the voltage level conversion unit and used for selectively controlling the voltage level conversion unit to output the candidate voltage levels to the multiplexer according to the voltage level of the timing control signal.
Compared with the prior art, in the voltage level conversion circuit and the display panel driving control method of the invention, the rising edge of the timing control signal triggers the source driver to output the data signal to start charging the fan-out unit, and also triggers the multiplexer to be partially opened to start precharging the data lines of the display panel for a period of time by using the exponential precharge curve, and then completely opens the multiplexer to charge the data lines.
The invention can partially start the multiplexer to pre-charge the data lines of the display panel before the multiplexer is completely started to charge the data lines of the display panel, thereby not only prolonging the effective charging time of the data lines and enabling the charging of the data lines to be more linear, but also reducing the instantaneous current of the data lines when the multiplexer is completely started and avoiding the voltage drop phenomenon.
Therefore, the voltage level conversion circuit and the display panel driving control method can effectively improve the pixel charging rate of the display panel and greatly eliminate the noise of the touch panel, so that the touch pen can be smoothly operated on the touch panel.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
Fig. 1 is a schematic diagram illustrating a plurality of data lines coupled to a display panel by a multiplexer according to a conventional source driver.
Fig. 2 is a timing chart illustrating a voltage drop of a data signal outputted from a conventional source driver at the moment when a multiplexer is turned on.
Fig. 3 is a timing diagram illustrating a conventional touch panel noise increase due to a large instantaneous current flowing in a data line caused by a large voltage difference generated between a fan-out unit and the data line at the moment when a multiplexer is turned on.
Fig. 4 is a timing chart illustrating that the conventional driving method causes a voltage drop of a data signal and noise of a touch panel increases at the moment when the multiplexer is turned on.
FIG. 5 is a schematic diagram of a voltage level shifter circuit according to a preferred embodiment of the present invention.
FIG. 6 is a schematic diagram of a voltage level shifter circuit according to another preferred embodiment of the present invention.
FIG. 7 is a schematic diagram of a voltage level shifter circuit according to yet another preferred embodiment of the present invention.
Fig. 8 and 9 are timing diagrams illustrating the start of precharging the multiplexer triggered by the rising edge of the timing control signal in different embodiments, respectively.
Fig. 10 is a timing diagram illustrating the improvement of the data signal voltage drop and the touch panel noise at the instant when the multiplexer is fully turned on according to the present invention.
FIG. 11 is a flow chart showing a driving control method of a display panel according to another preferred embodiment of the present invention.
Wherein, the reference numbers:
SO 1-SO 2: source driver output
FO 1-FO 2: fan-out unit
MUXA to MUXB: multiplexer
DL 1-DL 4: data line
CLK: clock pulse signal
SDAT, SDAT 1: data signal
TPN: touch panel noise
t 1-t 7: time of day
XSTB: timing control signal
TCON: time sequence controller
LS: voltage level conversion circuit
MLS (MLS): voltage level conversion unit
CU: control unit
FB: feedback unit
EA 1: first error amplifier
EA 2: second error amplifier
+: positive input end
-: negative input terminal
SWA: a first timing control signal
SWB: second timing control signal
VGL: first voltage level
GND: second voltage level
VGH: third voltage level
VREF: reference voltage
MTP: memory cell
VDU: voltage dividing unit
MOP: multiplex amplification unit
R: voltage dividing resistor
And MUX: multiplexer
OP: operational amplifier
tx: at a specific time
Vx: specific voltage level
S10-S14: step (ii) of
Detailed Description
The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:
the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, without departing from the spirit or scope of the present invention.
In the drawings, portions of regions are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a region or substrate is referred to as being "on" or "connected (or coupled)" to another element or "electrically connected" to another element, it can be directly on or connected (or coupled) to the other element or electrically connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected (or referred to as coupled)" may refer to physical and/or electrical connections.
According to a preferred embodiment of the present invention, a voltage level shifting circuit is provided. In this embodiment, the voltage level converting circuit may be controlled by the timing controller and may be coupled to a plurality of data lines in the display panel through a multiplexer. Referring to fig. 5, fig. 5 is a schematic diagram of a voltage level converting circuit in this embodiment.
As shown in fig. 5, the voltage level converting circuit LS is respectively coupled to the timing controller TCON and the multiplexers MUXA through MUXB, and the multiplexers MUXA through MUXB may be coupled to a plurality of data lines (not shown) in the display panel, for example, the multiplexer MUXA may be coupled to two data lines in the display panel and the multiplexer MUXB may be coupled to another two data lines in the display panel, but not limited thereto.
In this embodiment, the voltage level converting circuit LS includes a voltage level converting unit MLS, a control unit CU and a feedback unit FB. The control unit CU is coupled to the timing controller TCON, the voltage level conversion unit MLS, and the feedback unit FB, respectively; the voltage level converting unit MLS is coupled to the control unit CU, the multiplexers MUXA to MUXB, and the feedback unit FB, respectively.
The feedback unit FB includes a first error amplifier EA1 and a second error amplifier EA 2. A positive input terminal + of the first error amplifier EA1 is coupled between the voltage level converting unit MLS and the multiplexer MUXA, and an output terminal of the error amplifier EA1 is coupled to the control unit CU; the positive input terminal + of the error amplifier EA2 is coupled between the voltage level converting unit MLS and the multiplexer MUXB, and the output terminal of the error amplifier EA2 is coupled to the control unit CU.
The voltage level converting unit MLS receives the first voltage level VGL, the second voltage level GND and the third voltage level VGH, respectively, wherein the third voltage level VGH is higher than the second voltage level GND and the second voltage level GND is higher than the first voltage level VGL, i.e. the third voltage level VGH > the second voltage level GND > the first voltage level VGL.
When the control unit CU receives the first timing control signal SWA and the second timing control signal SWB provided by the timing controller TCON, the control unit CU selectively controls the voltage level converting unit MLS to output the first voltage level VGL or the second voltage level GND to the multiplexers MUXA to MUXB according to the voltage levels of the first timing control signal SWA and the second timing control signal SWB.
For example, when the voltage level of the first timing control signal SWA is at a Low level (Low-level), the control unit CU controls the voltage level converting unit MLS to output the first voltage level VGL to the multiplexer MUXA according to the Low-level first timing control signal SWA, and the multiplexer MUXA is not precharged yet; when the voltage level of the first timing control signal SWA changes from low level to High level (High-level), the control unit CU controls the voltage level converting unit MLS to output the second voltage level GND to the multiplexer MUXA according to the High-level first timing control signal SWA to start precharging the multiplexer MUXA. That is, the control unit CU is triggered by a Rising edge (Rising edge) of the first timing control signal SWA to control the voltage level converting unit MLS to start precharging the multiplexer MUXA.
Similarly, when the voltage level of the second timing control signal SWB is a Low level (Low-level), the control unit CU controls the voltage level conversion unit MLS to output the first voltage level VGL to the multiplexer MUXB according to the Low-level second timing control signal SWB, and at this time, the multiplexer MUXB is not precharged yet; when the voltage level of the second timing control signal SWB changes from a low level to a High level (High-level), the control unit CU controls the voltage level conversion unit MLS to output the second voltage level GND to the multiplexer MUXB according to the High-level second timing control signal SWB to start precharging the multiplexer MUXB. That is, the control unit CU is triggered by the rising edge of the second timing control signal SWB to control the voltage level converting unit MLS to start precharging the multiplexer MUXB.
In order to determine whether the multiplexer MUXA to be precharged has reached the reference voltage VREF, the positive input terminal of the first error amplifier EA 1+ the receiving voltage level converting unit MLS in the feedback unit FB outputs the precharge voltage to the multiplexer MUXA and the negative input terminal of the first error amplifier EA 1-receives the reference voltage VREF, and compares the positive input terminal and the receiving voltage level converting unit MLS to determine whether the multiplexer MUXA to be precharged has reached the reference voltage VREF and then provides the determination result to the control unit CU.
If the determination result is yes, indicating that the multiplexer MUXA is precharged to the reference voltage VREF, the control unit CU controls the voltage level conversion unit MLS to output the third voltage level VGH to the multiplexer MUXA, so as to terminate the precharging of the multiplexer MUXA by the voltage level conversion unit MLS; if the result of the determination is negative, which indicates that the multiplexer MUXA has not been precharged to the reference voltage VREF, the voltage level converting unit MLS will continue to precharge the multiplexer MUXA.
Similarly, the positive input terminal + receiving voltage level converting unit MLS of the second error amplifier EA2 in the feedback unit FB outputs the precharge voltage to the multiplexer MUXB and the negative input terminal-receiving reference voltage VREF of the second error amplifier EA2, and compares the two to determine whether the multiplexer MUXB to be precharged has reached the reference voltage VREF and then provides the determination result to the control unit CU.
If the determination result is yes, indicating that the multiplexer MUXB has been precharged to the reference voltage VREF, the control unit CU controls the voltage level conversion unit MLS to output the third voltage level VGH to the multiplexer MUXB, so as to end the precharging of the voltage level conversion unit MLS to the multiplexer MUXB; if the result of the above determination is negative, indicating that the multiplexer MUXB has not been precharged to the reference voltage VREF, the voltage level conversion unit MLS will continue to precharge the multiplexer MUXB.
In another embodiment, referring to fig. 6, the voltage level converting circuit LS does not include the feedback unit FB, but includes the memory unit MTP coupled to the control unit CU. In practical applications, the memory cell MTP may be a Multi-Time Programming (MTP) circuit for storing predetermined information, but not limited thereto.
When the voltage level of the first timing control signal SWA provided by the timing controller TCON is low, the control unit CU outputs the first voltage level VGL to the multiplexer MUXA, and the multiplexer MUXA is not precharged yet; when the voltage level of the first timing control signal SWA provided by the timing controller TCON changes from the low level to the high level, the control unit CU controls the voltage level converting unit MLS to output the second voltage level GND to the multiplexer MUXA within a predetermined time according to the predetermined information stored in the storage unit MTP to start precharging the multiplexer MUXA. That is, the control unit CU is triggered by the rising edge of the first timing control signal SWA to control the voltage level converting unit MLS to start precharging the multiplexer MUXA. When the predetermined time is over, the control unit CU controls the voltage level converting unit MLS to output the third voltage level VGH to the multiplexer MUXA to end the pre-charging of the multiplexer MUXA.
Similarly, when the voltage level of the second timing control signal SWB provided by the timing controller TCON is a low level, the control unit CU outputs the first voltage level VGL to the multiplexer MUXB, and the multiplexer MUXB is not precharged yet; when the voltage level of the second timing control signal SWB provided by the timing controller TCON is changed from the low level to the high level, the control unit CU controls the voltage level converting unit MLS to output the second voltage level GND to the multiplexer MUXB within a predetermined time according to the predetermined information stored in the storage unit MTP to start precharging the multiplexer MUXB. That is, the control unit CU is triggered by the rising edge of the second timing control signal SWB to control the voltage level converting unit MLS to start precharging the multiplexer MUXB. When the predetermined time is over, the control unit CU controls the voltage level converting unit MLS to output the third voltage level VGH to the multiplexer MUXB, so as to end the pre-charging of the multiplexer MUXB.
In another embodiment, referring to fig. 7, the voltage level converting circuit LS may include a control unit CU, a voltage level converting unit MLS, a memory unit MTP, a voltage dividing unit VDU, and a multiplexing amplifying unit MOP. Wherein, the control unit CU is respectively coupled with the time sequence controller TCON, the voltage level conversion unit MLS, the multiplex amplification unit MOP and the storage unit MTP; the voltage level conversion unit MLS is respectively coupled with the control unit CU, the multiplex amplification unit MOP and the multiplexers MUXA-MUXB; the voltage division unit VDU is coupled with the multiplex amplification unit MOP; the multiplexing amplifying unit MOP is respectively coupled to the control unit CU and the voltage level converting unit MLS.
The voltage division unit VDU receives a first voltage level VGL, a second voltage level GND and a third voltage level VGH, respectively, wherein the third voltage level VGH is higher than the second voltage level GND and the second voltage level GND is higher than the first voltage level VGL. The voltage division unit VDU generates a plurality of candidate voltage levels according to the first voltage level VGL, the second voltage level GND and the third voltage level VGH, and provides the candidate voltage levels to the voltage level conversion unit MLS after being processed by the multiplexing amplification unit MOP.
When the control unit CU receives the first timing control signal SWA provided by the timing controller TCON, the control unit CU selectively controls the voltage level converting unit MLS to output the candidate voltage levels to the multiplexer MUXA according to the voltage level of the first timing control signal SWA.
For example, when the voltage level of the first timing control signal SWA is low, the control unit CU controls the voltage level converting unit MLS to output a lowest candidate voltage level (e.g., the first voltage level VGL) of the candidate voltage levels to the multiplexer MUXA according to the low first timing control signal SWA, where the multiplexer MUXA is not precharged; when the voltage level of the first timing control signal SWA changes from low level to high level, the control unit CU controls the voltage level conversion unit MLS to output the candidate voltage levels (including, but not limited to, the second voltage level GND) higher than the lowest candidate voltage level (e.g., the first voltage level VGL) and lower than the highest candidate voltage level (e.g., the third voltage level VGH) to precharge the multiplexer MUXA within a predetermined time according to the high-level first timing control signal SWA. That is, the control unit CU is triggered by the rising edge of the first timing control signal SWA to control the voltage level converting unit MLS to start precharging the multiplexer MUXA. When the predetermined time is over, the control unit CU controls the voltage level converting unit MLS to output the highest candidate voltage level (e.g., the third voltage level VGH) to the multiplexer MUXA to end the pre-charging of the multiplexer MUXA.
Similarly, when the control unit CU receives the second timing control signal SWB provided by the timing controller TCON, the control unit CU selectively controls the voltage level converting unit MLS to output the candidate voltage levels to the multiplexer MUXB according to the voltage level of the second timing control signal SWB.
For example, when the voltage level of the second timing control signal SWB is low, the control unit CU controls the voltage level conversion unit MLS to output a lowest candidate voltage level (e.g., the first voltage level VGL) of the candidate voltage levels to the multiplexer MUXB according to the low second timing control signal SWB, and the multiplexer MUXB is not precharged yet; when the voltage level of the second timing control signal SWB changes from the low level to the high level, the control unit CU controls the voltage level conversion unit MLS to output the candidate voltage levels (including the second voltage level GND, but not limited thereto) higher than the lowest candidate voltage level (e.g., the first voltage level VGL) and lower than the highest candidate voltage level (e.g., the third voltage level VGH) within a predetermined time according to the high level second timing control signal SWB to precharge the multiplexer MUXB. That is, the control unit CU is triggered by the rising edge of the second timing control signal SWB to control the voltage level converting unit MLS to start precharging the multiplexer MUXB. When the predetermined time is over, the control unit CU controls the voltage level converting unit MLS to output the highest candidate voltage level (e.g., the third voltage level VGH) to the multiplexer MUXB, so as to end the pre-charging of the multiplexer MUXB.
In one embodiment, the voltage level converting unit MLS may include a plurality of operational amplifiers (not shown). The control unit CU may output a push control signal to the voltage level converting unit MLS, so as to control the plurality of operational amplifiers to provide corresponding push forces to output the plurality of candidate voltage levels received by the voltage level converting unit MLS to the multiplexer MUXA or MUXB, so that the plurality of candidate voltage levels form an exponential precharge curve, but not limited thereto.
In practical applications, the voltage dividing unit VDU may include a plurality of voltage dividing resistors R, and the voltage dividing resistors R may be connected in series between the third voltage level VGH and the first voltage level VGL, and the second voltage level GND may be coupled between any two voltage dividing resistors R of the voltage dividing resistors R, but not limited thereto.
Referring to fig. 8 and 9, the timing control signal XSTB is a trigger signal output by the data signal SDAT, and the data signal SDAT is output only when the timing control signal XSTB is Falling (Falling). It should be noted that the first timing control signal SWA and the second timing control signal SWB are voltage amplification signals in phase with the multiplexers MUXA and MUXB, and therefore are not particularly shown in fig. 8 and 9. In practical applications, the time for the multiplexers MUXA and MUXB to transition from low level to high level is not limited to the time after the timing control signal XSTB falls, and the multiplexers MUXA and MUXB may also transition to the state before the timing control signal XSTB falls due to the pre-charge and exponential line charge.
As shown in fig. 8, it is assumed that the two multiplexers MUXA to MUXB adopt operation timings of MUXA, MUXB, and MUXA. At time t1, the rising edge of the first timing control signal SWA (SWA is the same phase voltage amplified signal of the multiplexer MUXA, so not shown) triggers the start of precharging the multiplexer MUXA until the multiplexer MUXA is fully on at time t 2. In addition, the falling edge of the timing control signal XSTB also starts charging the data lines in the display panel at the same time as the data signal SDAT is activated at time t 1. Similarly, at time t4, the rising edge of the second timing control signal SWB (SWB is the same-phase voltage amplified signal of the multiplexer MUXB and therefore not shown) triggers the start of precharging the multiplexer MUXB until the multiplexer MUXB is fully opened at time t 5.
As shown in fig. 9, it is assumed that the two multiplexers MUXA to MUXB adopt operation timings of MUXA, MUXB, MUXA, and MUXB. At time t1, the rising edge of the first timing control signal SWA (SWA is the same phase voltage amplified signal of the multiplexer MUXA, so not shown) triggers the start of precharging the multiplexer MUXA until the multiplexer MUXA is fully on at time t 2. In addition, the falling edge of the timing control signal XSTB also starts charging the data lines in the display panel at the same time as the data signal SDAT is activated at time t 1. Similarly, at time t4, the rising edge of the second timing control signal SWB (SWB is the same-phase voltage amplified signal of the multiplexer MUXB and therefore not shown) triggers the start of precharging the multiplexer MUXB until the multiplexer MUXB is fully opened at time t 5.
Referring to fig. 10, the present invention can improve the voltage drop of the data signal and the timing diagram of the touch panel noise at the instant when the multiplexer is fully turned on.
As shown in fig. 10, taking the multiplexer MUXA as an example, the rising edge of the first timing control signal SWA (SWA is an in-phase voltage amplified signal of the multiplexer MUXA and is not shown) triggers the start of precharging the multiplexer MUXA at time t1 and the multiplexer MUXA receives the first voltage level VGL at time t 1; then, the multiplexer MUXA receives the specific voltage level Vx higher than the first voltage level VGL at the specific time tx later than the time t 1; then, the multiplexer MUXA receives the third voltage level VGH higher than the specific voltage level Vx at time t2 later than the specific time tx. In practical applications, the specific time tx is between the times t1 and t 2; the specific voltage level Vx is between the first voltage level VGL and a third voltage level VGH, such as, but not limited to, the second voltage level GND.
It should be noted that the speed of the multiplexer MUXA rising from the specific voltage level Vx at the specific time tx to the third voltage level VGH at the time t2 is greater than the speed of the multiplexer MUXA rising from the first voltage level VGL at the time t1 to the specific voltage level Vx at the specific time tx.
That is, assuming that the time length from the time t1 to the specific time tx is equal to the time length from the specific time tx to the time t2, that is, the specific time tx is equal to (time t1+ time t2)/2, the voltage difference between the specific voltage level Vx and the third voltage level VGH is greater than the voltage difference between the first voltage level VGL and the specific voltage level Vx; assuming that the voltage difference between the specific voltage level Vx and the third voltage level VGH is equal to the voltage difference between the first voltage level and the specific voltage level Vx, that is, the specific voltage level Vx is equal to (the first voltage level VGL + the third voltage level VGH)/2, the time duration from the time t1 to the specific time tx is longer than the time duration from the specific time tx to the time t 2.
From the above, it can be seen that: during the period from time t1 to time t2 when the multiplexer MUXA is precharged, the voltage level received by the partially open multiplexer MUXA rises exponentially, so that the partially open multiplexer MUXA precharges the data lines of the display panel with an exponential precharge curve from time t1 until the multiplexer MUXA is fully open at time t 2.
In practical applications, the number of the specific time tx and the number of the specific voltage level Vx in the present invention may be one or more, and is not limited to a single time and a single voltage level in the above embodiments.
For example, the multiplexing amplifying unit MOP can be controlled by the memory unit MTP and the control unit CU in fig. 7 to output n specific voltage levels Vx1 to Vxn between the first voltage level VGL and the third voltage level VGH at n specific times tx1 to txn between time t1 and time t2, respectively, where n is a positive integer greater than 1, and the third voltage level VGH > Vxn > Vx (n-1) > Vx1 > the first voltage level VGL, so that the voltage level converting unit MLS can output an exponential precharge curve.
Taking the multiplexer MUXA as an example, the speed of the multiplexer MUXA rising from the specific voltage level Vxn at the specific time txn to the third voltage level VGH at the time t2 > the multiplexer MUXA rising from the specific voltage level Vx (n-1) at the time tx (n-1) to the specific voltage level Vxn at the specific time txn > the multiplexer MUXA rising from the first voltage level VGL at the time t1 to the specific voltage level Vx1 at the time tx 1.
That is, assuming that the length of time from the time t1 to the specific time tx1 is the length of time from the specific time tx1 to the specific time tx2 is the length of time from the specific time txn to the time t2, the voltage difference between the specific voltage level Vxn and the third voltage level VGH > the voltage difference between the specific voltage level Vx (n-1) and the specific voltage level Vxn > the voltage difference between the first voltage level VGL and the specific voltage level Vx 1; assuming that a voltage difference between the specific voltage level Vxn and the third voltage level VGH is a voltage difference between the specific voltage level Vx (n-1) and the specific voltage level Vxn, which is a voltage difference between the first voltage level VGL and the specific voltage level Vx1, a length of time from the time t1 to the specific time tx1 > a length of time from the specific time tx1 to the specific time tx2 > a length of time from the specific time tx n to the time t 2.
Similarly, the pre-charging of the multiplexer MUXB and the pre-discharging of the data lines of the display panel by the multiplexers MUXA to MUXB can be performed in the same way, and thus are not described herein.
Another preferred embodiment of the present invention is a display panel driving control method. In this embodiment, the display panel driving control method is used to control the source driver output to drive a plurality of data lines in the display panel through the multiplexer.
Referring to fig. 11, fig. 11 is a flowchart illustrating a driving control method of a display panel according to this embodiment. As shown in fig. 11, the display panel driving control method may include the following steps:
step S10: starting to precharge the multiplexer through a time sequence control signal at a first time, wherein the multiplexer receives a first voltage level at the first time;
step S12: at a second time, the multiplexer receives a second voltage level, wherein the second time is later than the first time and the second voltage level is higher than the first voltage level; and
step S14: and receiving a third voltage level by the multiplexer at a third time, wherein the third time is later than the second time and the third voltage level is higher than the second voltage level.
It should be noted that the speed of the multiplexer increasing from the second voltage level at the second time to the third voltage level at the third time is greater than the speed of the multiplexer increasing from the first voltage level at the first time to the second voltage level at the second time. That is, the multiplexer that is originally in the off state receives the first voltage level at the first time and is partially turned on, and the voltage level received by the multiplexer from the first time to the third time increases exponentially until the multiplexer receives the third voltage level at the third time and is completely turned on.
In practical applications, the rising edge of the timing control signal also triggers the plurality of data lines in the display panel to start charging at the first time. Since the voltage level received by the multiplexer from the first time to the third time is exponentially increased, the multiplexer precharges the data lines of the display panel by the exponential precharge curve from the first time, and the precharging of the data lines of the display panel is stopped until the multiplexer is in a fully-on state when receiving the third voltage level at the third time.
For example, as shown in fig. 10, the rising edge of the first timing control signal SWA (SWA is the same-phase voltage-amplified signal of the multiplexer MUXA, and therefore not shown) triggers the start of precharging the multiplexer MUXA at time t1 and the multiplexer MUXA receives the first voltage level VGL at time t 1; then, the multiplexer MUXA receives the second voltage level Vx at time tx, where time tx is later than the first time t1 and the second voltage level Vx is higher than the first voltage level VGL; then, the multiplexer MUXA receives the third voltage level VGH at time t2, where time t2 is later than time tx and the third voltage level VGH is higher than the second voltage level Vx. Since the speed of the multiplexer MUXA rising from the second voltage level Vx at the time tx to the third voltage level VGH at the time t2 is greater than the speed of the multiplexer MUXA rising from the first voltage level VGL at the time t1 to the second voltage level Vx at the time tx, that is, the voltage level received by the partially-opened multiplexer MUXA exhibits an exponential change during the precharge period from the time t1 to the time t2, the partially-opened multiplexer MUXA precharges the data lines of the display panel with an exponential precharge curve from the time t1 until the time t 2.
Similarly, the situation that the multiplexer pre-discharges the data lines of the display panel can be similar. In the above example, the display panel driving control method may further include the following steps:
triggering the multiplexer to start pre-discharging at a fourth time, wherein the fourth time is later than the third time and the multiplexer receives a third voltage level at the fourth time;
at a fifth time, the multiplexer receives a fourth voltage level, wherein the fifth time is later than the fourth time and the fourth voltage level is lower than the third voltage level; and
and receiving the first voltage level by the multiplexer at a sixth time, wherein the sixth time is later than the fifth time and the first voltage level is lower than the fourth voltage level.
Similarly, the speed of the multiplexer decreasing from the fourth voltage level at the fifth time to the first voltage level at the sixth time is greater than the speed of the multiplexer decreasing from the third voltage level at the fourth time to the fourth voltage level at the fifth time, i.e. the voltage levels received by the multiplexer from the fourth time to the sixth time are exponentially decreased.
Compared with the prior art, in the voltage level conversion circuit and the display panel driving control method of the invention, the rising edge of the timing control signal triggers the source driver to output the data signal to start charging the fan-out unit, and also triggers the multiplexer to be partially opened to start precharging the data lines of the display panel for a period of time by using the exponential precharge curve, and then completely opens the multiplexer to charge the data lines.
The invention can partially start the multiplexer to pre-charge the data lines of the display panel before the multiplexer is completely started to charge the data lines of the display panel, thereby not only prolonging the effective charging time of the data lines and enabling the charging of the data lines to be more linear, but also reducing the instantaneous current of the data lines when the multiplexer is completely started and avoiding the voltage drop phenomenon.
Therefore, the voltage level conversion circuit and the display panel driving control method can effectively improve the pixel charging rate of the display panel and greatly eliminate the noise of the touch panel, so that the touch pen can be smoothly operated on the touch panel.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A display panel driving control method is used for driving a plurality of data lines in a display panel through a multiplexer, and is characterized by comprising the following steps:
(a) starting to precharge the multiplexer by a time sequence control signal at a first time, wherein the multiplexer receives a first voltage level at the first time;
(b) receiving a second voltage level by the multiplexer at a second time, wherein the second time is later than the first time and the second voltage level is higher than the first voltage level; and
(c) at a third time, the multiplexer receives a third voltage level, wherein the third time is later than the second time and the third voltage level is higher than the second voltage level;
(d) at the first time, the plurality of data lines are simultaneously triggered to start to be charged according to the time sequence control signal;
the multiplexer increases from the second voltage level at the second time to the third voltage level at the third time at a speed greater than that of the multiplexer from the first voltage level at the first time to the second voltage level at the second time.
2. The method according to claim 1, wherein the step (a) is performed by precharging the multiplexer according to a Rising edge (Rising edge) of the timing control signal.
3. The display panel driving control method of claim 1, wherein the step (c) further comprises:
when the multiplexer receives the third voltage level, the pre-charging of the multiplexer is stopped.
4. The method as claimed in claim 1, wherein the multiplexer is turned off at the first time.
5. The method as claimed in claim 1, wherein the multiplexer is in a partially turned on state at the second time.
6. The method as claimed in claim 1, wherein the multiplexer is in a fully turned on state at the third time.
7. The method as claimed in claim 1, wherein step (d) initiates charging of the data lines according to the rising edge of the timing control signal.
8. The display panel driving control method according to claim 1, further comprising the steps of:
triggering the multiplexer to start pre-discharging at a fourth time, wherein the fourth time is later than the third time and the multiplexer receives the third voltage level at the fourth time;
at a fifth time, the multiplexer receives a fourth voltage level, wherein the fifth time is later than the fourth time and the fourth voltage level is lower than the third voltage level; and
at a sixth time, the multiplexer receives the first voltage level, wherein the sixth time is later than the fifth time and the first voltage level is lower than the fourth voltage level.
9. The method as claimed in claim 8, wherein the multiplexer decreases from the fourth voltage level at the fifth time to the first voltage level at the sixth time faster than the multiplexer decreases from the third voltage level at the fourth time to the fourth voltage level at the fifth time.
10. A voltage level shifting circuit coupled to a plurality of data lines of a display panel via a multiplexer, the voltage level shifting circuit comprising:
a voltage level conversion unit coupled to the multiplexer and respectively receiving a first voltage level, a second voltage level and a third voltage level, wherein the third voltage level is higher than the second voltage level and the second voltage level is higher than the first voltage level; and
a control unit coupled to the voltage level conversion unit for selectively controlling the voltage level conversion unit to output the first voltage level or the second voltage level to the multiplexer according to a voltage level of a timing control signal.
11. The circuit of claim 10, wherein the control unit controls the voltage level conversion unit to output the first voltage level to the multiplexer when the voltage level of the timing control signal is low.
12. The circuit of claim 10, wherein when the voltage level of the timing control signal is high, the control unit controls the voltage level converting unit to output the second voltage level to the multiplexer to precharge the multiplexer.
13. The voltage level shifting circuit of claim 12, further comprising:
a feedback unit, coupled to the multiplexer and the control unit, respectively, for determining whether the multiplexer performing the pre-charging reaches a reference voltage;
if the determination result is yes, the control unit controls the voltage level conversion unit to output the third voltage level to the multiplexer.
14. The voltage level shifting circuit of claim 10, further comprising:
a storage unit coupled to the control unit for storing a predetermined information;
when the voltage level of the timing control signal is at a high level, the control unit controls the voltage level conversion unit to output the second voltage level to the multiplexer within a preset time according to the preset information to pre-charge the multiplexer, and when the preset time is over, the control unit controls the voltage level conversion unit to output the third voltage level to the multiplexer.
15. The voltage level shifter of claim 14, wherein the memory cell is a Multi-Time Programming (MTP) circuit.
16. A voltage level shifting circuit coupled to a plurality of data lines of a display panel via a multiplexer, the voltage level shifting circuit comprising:
the voltage division unit is used for respectively receiving a first voltage level, a second voltage level and a third voltage level to generate a plurality of candidate voltage levels, wherein the third voltage level is higher than the second voltage level and the second voltage level is higher than the first voltage level;
a voltage level conversion unit coupled to the multiplexer and the voltage division unit, respectively, for receiving the candidate voltage levels; and
a control unit coupled to the voltage level conversion unit for selectively controlling the voltage level conversion unit to output the candidate voltage levels to the multiplexer according to a voltage level of a timing control signal.
17. The circuit of claim 16, wherein the voltage level conversion unit comprises a plurality of operational amplifiers, and the control unit further outputs a push control signal to the voltage level conversion unit to control the operational amplifiers to provide corresponding push outputs to the multiplexer, such that the candidate voltage levels form an exponential pre-charge curve.
18. The voltage level shifting circuit of claim 16, further comprising:
a storage unit coupled to the control unit for storing a predetermined information;
when the voltage level of the timing control signal is at a high level, the control unit controls the voltage level conversion unit to output the at least one candidate voltage level to the multiplexer respectively within at least one preset time according to the preset information to precharge the multiplexer, and when the at least one preset time is over, the control unit controls the voltage level conversion unit to output the third voltage level to the multiplexer.
19. The voltage level shifting circuit of claim 18, wherein the memory cell is a multiple time programmable circuit.
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| TW107136407 | 2018-10-16 | ||
| TW107136407A TWI680394B (en) | 2018-10-16 | 2018-10-16 | Voltage level shifter cirucit and display panel driving control method |
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| TWI758600B (en) | 2019-04-09 | 2022-03-21 | 友達光電股份有限公司 | Display panel and display panel driving method |
| CN110930923B (en) * | 2019-11-27 | 2022-09-27 | Tcl华星光电技术有限公司 | Display panel driving circuit |
| KR20210083637A (en) * | 2019-12-27 | 2021-07-07 | 엘지디스플레이 주식회사 | Display apparatus |
| TWI734553B (en) * | 2020-07-13 | 2021-07-21 | 友達光電股份有限公司 | Display panel |
| CN114446236A (en) * | 2020-11-06 | 2022-05-06 | 联咏科技股份有限公司 | Method for driving display screen and driving circuit thereof |
| WO2023044719A1 (en) * | 2021-09-24 | 2023-03-30 | 京东方科技集团股份有限公司 | Fingerprint recognition substrate, electronic device, and fingerprint recognition method |
| TWI800106B (en) * | 2021-11-22 | 2023-04-21 | 友達光電股份有限公司 | Multiplexer circuit, display panel and driving method using the same |
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| KR100607518B1 (en) * | 2004-02-20 | 2006-08-02 | 엘지전자 주식회사 | Electro-luminescensce dispaly panel and method for driving the same |
| CN100573635C (en) * | 2006-09-29 | 2009-12-23 | 胜华科技股份有限公司 | Active display and driving method thereof with de-multiplexer |
| KR102001047B1 (en) * | 2012-07-12 | 2019-07-18 | 삼성디스플레이 주식회사 | Method of driving a display panel and display panel driving apparatus for performing the method |
| KR102034061B1 (en) * | 2013-06-29 | 2019-11-08 | 엘지디스플레이 주식회사 | Liquid crystal display device |
| JP6231314B2 (en) * | 2013-07-16 | 2017-11-15 | シナプティクス・ジャパン合同会社 | Display drive device |
| TWI579823B (en) * | 2016-02-22 | 2017-04-21 | 友達光電股份有限公司 | Display device and driving circuit thereof |
| TWI576812B (en) * | 2016-04-15 | 2017-04-01 | 友達光電股份有限公司 | Pixel driving circuit |
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