TWI734553B - Display panel - Google Patents
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- TWI734553B TWI734553B TW109123512A TW109123512A TWI734553B TW I734553 B TWI734553 B TW I734553B TW 109123512 A TW109123512 A TW 109123512A TW 109123512 A TW109123512 A TW 109123512A TW I734553 B TWI734553 B TW I734553B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
Description
本發明是關於一種顯示面板,特別是關於一種藉由調整多工器電路區的臨界電壓,以改善像素充電率不足之顯示面板。 The present invention relates to a display panel, and more particularly to a display panel that improves the insufficient pixel charging rate by adjusting the threshold voltage of the multiplexer circuit area.
在製作多工器電路時,可使用互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor,CMOS)製程來製作對應之電晶體,其具有良好的切換阻抗以及充電性能。然而,CMOS製程包含互補式金屬氧化物半導體與N型金屬氧化物半導體(N-Type Metal-Oxide-Semiconductor,NMOS)製程以及P型金屬氧化物半導體(P-Type Metal-Oxide-Semiconductor,PMOS)製程,在實際製程上需要運用更多道光罩,製作步驟上較為複雜且成本較高。 When making a multiplexer circuit, a Complementary Metal-Oxide-Semiconductor (CMOS) process can be used to make the corresponding transistor, which has good switching impedance and charging performance. However, the CMOS process includes complementary metal oxide semiconductor and N-Type Metal-Oxide-Semiconductor (NMOS) processes and P-Type Metal-Oxide-Semiconductor (PMOS) processes. The manufacturing process requires more masks in the actual manufacturing process, and the manufacturing steps are more complicated and costly.
若是考慮單獨使用NMOS製程或PMOS製程來製作多工器電路區的電晶體,雖然能簡化製程,但在元件電性上的表現可能不如CMOS製程所製作的多工器電路。例如僅使用NMOS製程製作的多工器電路,像素充電率較差,尤其使用在高幀率(High frame rate,HFR)的環境中,更是有像素充電率嚴重不足之問題。 If one considers using the NMOS process or the PMOS process alone to fabricate the transistors in the multiplexer circuit area, although the process can be simplified, the electrical performance of the device may not be as good as the multiplexer circuit made by the CMOS process. For example, a multiplexer circuit made using only an NMOS process has a poor pixel charging rate. Especially when used in a high frame rate (HFR) environment, the pixel charging rate is seriously insufficient.
綜觀前所述,本發明之發明者思索並設計一種顯示面板,以期針對習知技術之缺失加以改善,進而增進產業上之實施利用。 In summary, the inventor of the present invention thought about and designed a display panel with a view to improving the lack of conventional technology, thereby enhancing the application and utilization in the industry.
有鑑於上述習知之問題,本發明的目的在於提供一種顯示面板,用以解決單獨使用NMOS製程或PMOS製程時,充電率不足之問題。 In view of the above-mentioned conventional problems, the purpose of the present invention is to provide a display panel to solve the problem of insufficient charging rate when the NMOS process or the PMOS process is used alone.
基於上述目的,本發明提供一種顯示面板,包含第一基板和第二基板,且其包含多工器電路區以及其他電路區。多工器電路區形成於第一基板上,包含複數個電晶體,分別電性耦接於顯示面板的複數個資料線,複數個電晶體包含第一臨界電壓。其他電路區形成於第一基板上,其他電路區包含複數個電晶體,複數個電晶體具有第二臨界電壓,第二臨界電壓與第一臨界電壓不同。 Based on the above objective, the present invention provides a display panel including a first substrate and a second substrate, and including a multiplexer circuit area and other circuit areas. The multiplexer circuit area is formed on the first substrate and includes a plurality of transistors electrically coupled to a plurality of data lines of the display panel, and the plurality of transistors include a first threshold voltage. The other circuit regions are formed on the first substrate, and the other circuit regions include a plurality of transistors, and the plurality of transistors have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage.
在本發明的實施例中,第一臨界電壓與第二臨界電壓可相差0.5V以上。 In the embodiment of the present invention, the first threshold voltage and the second threshold voltage may differ by more than 0.5V.
在本發明的實施例中,多工器電路區的複數個電晶體可包含N型電晶體,第二臨界電壓為正電壓而第一臨界電壓為負電壓。 In an embodiment of the present invention, the plurality of transistors in the multiplexer circuit region may include N-type transistors, the second threshold voltage is a positive voltage and the first threshold voltage is a negative voltage.
在本發明的實施例中,多工器電路區的複數個電晶體可包含P型電晶體,第二臨界電壓為負電壓而第一臨界電壓為正電壓。 In the embodiment of the present invention, the plurality of transistors in the multiplexer circuit region may include P-type transistors, the second threshold voltage is a negative voltage and the first threshold voltage is a positive voltage.
在本發明的實施例中,其他電路區可包含複數個像素區,複數個像素區分別包含第一像素、第二像素、第三像素、第四像素、第五像素及第六像素,各複數個像素區分別耦接於多工器電路區的複數個電晶體,當複數個電晶體導通時,由複數個資料線傳送資料訊號至複數個像素區。 In the embodiment of the present invention, other circuit regions may include a plurality of pixel regions, and the plurality of pixel regions respectively include a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel, each Each pixel area is respectively coupled to the plurality of transistors of the multiplexer circuit area. When the plurality of transistors are turned on, the data signals are transmitted to the plurality of pixel areas from the plurality of data lines.
在本發明的實施例中,多工器電路區可包含複數個第一電晶體、複數個第二電晶體、複數個第三電晶體、複數個第四電晶體、複數個第五電晶 體、以及複數個第六電晶體。複數個第一電晶體分別包含第一端、第二端及控制端,第一端連接第一像素、第二端連接正電壓源及控制端連接第一控制訊號線。複數個第二電晶體分別包含第一端、第二端及控制端,第一端連接第五像素、第二端連接正電壓源及控制端連接第二控制訊號線。複數個第三電晶體分別包含第一端、第二端及控制端,第一端連接第三像素、第二端連接正電壓源及控制端連接第三控制訊號線。複數個第四電晶體分別包含第一端、第二端及控制端,第一端連接第四像素、第二端連接負電壓源及控制端連接第一控制訊號線。複數個第五電晶體分別包含第一端、第二端及控制端,第一端連接第二像素、第二端連接負電壓源及控制端連接第二控制訊號線。複數個第六電晶體分別包含第一端、第二端及控制端,第一端連接第六像素、第二端連接負電壓源及控制端連接第三控制訊號線。 In the embodiment of the present invention, the multiplexer circuit area may include a plurality of first transistors, a plurality of second transistors, a plurality of third transistors, a plurality of fourth transistors, and a plurality of fifth transistors. Body, and a plurality of sixth transistors. The plurality of first transistors respectively include a first terminal, a second terminal and a control terminal. The first terminal is connected to the first pixel, the second terminal is connected to the positive voltage source, and the control terminal is connected to the first control signal line. The plurality of second transistors respectively include a first terminal, a second terminal and a control terminal. The first terminal is connected to the fifth pixel, the second terminal is connected to the positive voltage source, and the control terminal is connected to the second control signal line. The plurality of third transistors respectively include a first terminal, a second terminal and a control terminal. The first terminal is connected to the third pixel, the second terminal is connected to the positive voltage source, and the control terminal is connected to the third control signal line. The plurality of fourth transistors respectively include a first terminal, a second terminal and a control terminal. The first terminal is connected to the fourth pixel, the second terminal is connected to the negative voltage source, and the control terminal is connected to the first control signal line. The plurality of fifth transistors respectively include a first terminal, a second terminal and a control terminal. The first terminal is connected to the second pixel, the second terminal is connected to the negative voltage source, and the control terminal is connected to the second control signal line. The plurality of sixth transistors respectively include a first terminal, a second terminal and a control terminal. The first terminal is connected to the sixth pixel, the second terminal is connected to the negative voltage source, and the control terminal is connected to the third control signal line.
在本發明的實施例中,多工器電路區可包含複數個第一電晶體、複數個第二電晶體、複數個第三電晶體、複數個第四電晶體、複數個第五電晶體、以及複數個第六電晶體。複數個第一電晶體分別包含第一端、第二端及控制端,第一端連接第一像素、第二端連接正電壓源及控制端連接第一控制訊號線。複數個第二電晶體分別包含第一端、第二端及控制端,第一端連接第二像素、第二端連接負電壓源及控制端連接第二控制訊號線。複數個第三電晶體分別包含第一端、第二端及控制端,第一端連接第三像素、第二端連接正電壓源及控制端連接第三控制訊號線。複數個第四電晶體分別包含第一端、第二端及控制端,第一端連接第四像素、第二端連接負電壓源及控制端連接第一控制訊號線。複數個第五電晶體分別包含第一端、第二端及控制端,第一端連接第五像素、第二端連接正電壓源及控制端連接第二控制訊號線。複數個第六電晶體 分別包含第一端、第二端及控制端,第一端連接第六像素、第二端連接負電壓源及控制端連接第三控制訊號線。 In the embodiment of the present invention, the multiplexer circuit area may include a plurality of first transistors, a plurality of second transistors, a plurality of third transistors, a plurality of fourth transistors, a plurality of fifth transistors, And a plurality of sixth transistors. The plurality of first transistors respectively include a first terminal, a second terminal and a control terminal. The first terminal is connected to the first pixel, the second terminal is connected to the positive voltage source, and the control terminal is connected to the first control signal line. The plurality of second transistors respectively include a first terminal, a second terminal and a control terminal. The first terminal is connected to the second pixel, the second terminal is connected to the negative voltage source, and the control terminal is connected to the second control signal line. The plurality of third transistors respectively include a first terminal, a second terminal and a control terminal. The first terminal is connected to the third pixel, the second terminal is connected to the positive voltage source, and the control terminal is connected to the third control signal line. The plurality of fourth transistors respectively include a first terminal, a second terminal and a control terminal. The first terminal is connected to the fourth pixel, the second terminal is connected to the negative voltage source, and the control terminal is connected to the first control signal line. The plurality of fifth transistors respectively include a first terminal, a second terminal and a control terminal. The first terminal is connected to the fifth pixel, the second terminal is connected to the positive voltage source, and the control terminal is connected to the second control signal line. Multiple sixth transistors They respectively include a first end, a second end and a control end. The first end is connected to the sixth pixel, the second end is connected to a negative voltage source, and the control end is connected to a third control signal line.
在本發明的實施例中,第一像素及第四像素可為紅色像素,第二像素及第五像素可為綠色像素,第三像素及第六像素可為藍色像素。 In the embodiment of the present invention, the first pixel and the fourth pixel may be red pixels, the second pixel and the fifth pixel may be green pixels, and the third pixel and the sixth pixel may be blue pixels.
在本發明的實施例中,耦接於紅色像素的複數個電晶體包含紅色臨界電壓,耦接於綠色像素的複數個電晶體包含綠色臨界電壓及耦接於藍色像素的複數個電晶體包含藍色臨界電壓,藍色臨界電壓可大於綠色臨界電壓或紅色臨界電壓。 In an embodiment of the present invention, the plurality of transistors coupled to the red pixel includes a red threshold voltage, the plurality of transistors coupled to the green pixel includes a green threshold voltage, and the plurality of transistors coupled to the blue pixel includes The blue threshold voltage, the blue threshold voltage can be greater than the green threshold voltage or the red threshold voltage.
在本發明的實施例中,其他電路區可包含驅動晶片,耦接於複數個電晶體並提供操作電壓至複數個電晶體。 In an embodiment of the present invention, other circuit areas may include a driver chip, which is coupled to a plurality of transistors and provides an operating voltage to the plurality of transistors.
承上所述,本發明之顯示面板,藉由調整多工器電路區的第一臨界電壓,使像素充電率在高幀率的情況下獲得明顯改善。 As mentioned above, in the display panel of the present invention, by adjusting the first threshold voltage of the multiplexer circuit area, the pixel charging rate can be significantly improved at a high frame rate.
COF、COF1、COF2:覆晶式薄膜區 COF, COF1, COF2: flip-chip thin film area
DA、DA1、DA2:顯示區 DA, DA1, DA2: display area
DL11、DL21:第一資料線 DL11, DL21: the first data line
DL12、DL22:第二資料線 DL12, DL22: the second data line
DL13、DL23:第三資料線 DL13, DL23: the third data line
DL14、DL24:第四資料線 DL14, DL24: the fourth data line
DL15、DL25:第五資料線 DL15, DL25: the fifth data line
DL16、DL26:第六資料線 DL16, DL26: the sixth data line
DP:顯示面板 DP: display panel
MUX、MUX1、MUX1:多工器電路區 MUX, MUX1, MUX1: Multiplexer circuit area
MUX11、MUX21:第一控制訊號線 MUX11, MUX21: the first control signal line
MUX12、MUX22:第二控制訊號線 MUX12, MUX22: the second control signal line
MUX13、MUX23:第三控制訊號線 MUX13, MUX23: the third control signal line
NDA:非顯示區 NDA: Non-display area
NMUX:其他電路區 NMUX: other circuit area
P11、P21:第一像素 P11, P21: the first pixel
P12、P22:第二像素 P12, P22: second pixel
P13、P23:第三像素 P13, P23: third pixel
P14、P24:第四像素 P14, P24: fourth pixel
P15、P25:第五像素 P15, P25: fifth pixel
P16、P26:第六像素 P16, P26: sixth pixel
S1:第一基板 S1: First substrate
T11、T21:第一電晶體 T11, T21: the first transistor
T12、T22:第二電晶體 T12, T22: second transistor
T13、T23:第三電晶體 T13, T23: third transistor
T14、T24:第四電晶體 T14, T24: fourth transistor
T15、T25:第五電晶體 T15, T25: fifth transistor
T16、T26:第六電晶體 T16, T26: sixth transistor
t1、t2、t3:時間點 t1, t2, t3: time point
Vth1:第一臨界電壓 Vth1: the first threshold voltage
Vth2:第二臨界電壓 Vth2: second critical voltage
為使本發明之技術特徵、內容與優點及其所能達成之功效更為顯而易見,茲將本發明配合附圖,並以實施例之表達形式詳細說明如下:第1圖為本發明之顯示面板之示意圖。 In order to make the technical features, content and advantages of the present invention and the effects it can achieve more obvious, the present invention is combined with the accompanying drawings and described in detail in the form of embodiments as follows: Figure 1 is the display panel of the present invention The schematic diagram.
第2圖為本發明之顯示面板之多工器電路區的電流電壓曲線圖。 Figure 2 is a current-voltage curve diagram of the multiplexer circuit area of the display panel of the present invention.
第3圖為本發明實施例之多工器電路區的配置圖。 Figure 3 is a configuration diagram of a multiplexer circuit area according to an embodiment of the present invention.
第4圖為本發明另一實施例之多工器電路區的配置圖。 Figure 4 is a configuration diagram of a multiplexer circuit area according to another embodiment of the present invention.
第5圖為本發明實施例之顯示面板調整臨界電壓的測試圖。 FIG. 5 is a test diagram of adjusting the threshold voltage of the display panel according to the embodiment of the present invention.
第6圖為本發明另一實施例之顯示面板調整臨界電壓的測試圖。 FIG. 6 is a test diagram of adjusting the threshold voltage of a display panel according to another embodiment of the present invention.
為利瞭解本發明之技術特徵、內容與優點及其所能達成之功效,茲將本發明配合附圖,並以實施例之表達形式詳細說明如下,而其中所使用之圖式,其主旨僅為示意及輔助說明書之用,未必為本發明實施後之真實比例與精準配置,故不應就所附之圖式的比例與配置關係解讀、侷限本發明於實際實施上的權利範圍,合先敘明。 In order to understand the technical features, content and advantages of the present invention as well as the effects that can be achieved, the present invention is described in detail with the accompanying drawings and in the form of embodiment expressions as follows, and the figures used therein are only For the purpose of illustration and supplementary description, it is not necessarily the true scale and precise configuration after the implementation of the invention. Therefore, the scale and configuration relationship of the attached drawings should not be interpreted, and the scope of rights of the invention in actual implementation should not be interpreted. Narrate.
在附圖中,為了淸楚起見,放大了基板、面板、區域、線路等的厚度或寬度。在整個說明書中,相同的附圖標記表示相同的元件。應當理解,當諸如基板、面板、區域或線路的元件被稱為在另一元件「上」或「連接到」另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反地,當元件被稱為「直接在另一元件上」或「直接連接到」另一元件時,不存在中間元件。如本文所使用的「連接」,其可以指物理及/或電性的連接。再者,「電性連接」或「耦合」係可為二元件間存在其它元件。此外,應當理解,儘管術語「第一」、「第二」、「第三」在本文中可以用於描述各種元件、部件、區域、層及/或部分,其係用於將一個元件、部件、區域、層及/或部分與另一個元件、部件、區域、層及/或部分區分開。因此,僅用於描述目的,而不能將其理解為指示或暗示相對重要性或者其順序關係。 In the drawings, for the sake of clarity, the thickness or width of the substrate, panel, area, line, etc. are exaggerated. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a substrate, panel, area, or circuit is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connection" can refer to a physical and/or electrical connection. Furthermore, "electrical connection" or "coupling" can mean that there are other elements between the two elements. In addition, it should be understood that although the terms “first”, “second”, and “third” may be used herein to describe various elements, components, regions, layers and/or parts, they are used to refer to an element, component , Region, layer and/or part are distinguished from another element, component, region, layer and/or part. Therefore, it is only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or its sequence relationship.
除非另有定義,本文所使用的所有術語具有與本發明所屬技術領域的通常知識者通常理解的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的 含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地如此定義。 Unless otherwise defined, all terms used herein have the meanings commonly understood by those with ordinary knowledge in the technical field to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as they are in the context of related technologies and the present invention. The meaning is consistent with the meaning, and will not be interpreted as an idealized or excessively formal meaning unless it is clearly defined as such in this article.
請參閱第1圖,其為本發明之顯示面板之示意圖。如圖所示,本發明之顯示面板DP包含上基板及下基板,其中第一基板S1可為下基板或上基板,依據顯示面板DP類型來決定。第一基板S1當中包含不同設置區域,分別用來配置對應的結構及電路,其不同區域的設置方式於下列段落進一步說明。 Please refer to Figure 1, which is a schematic diagram of the display panel of the present invention. As shown in the figure, the display panel DP of the present invention includes an upper substrate and a lower substrate. The first substrate S1 can be a lower substrate or an upper substrate, depending on the type of the display panel DP. The first substrate S1 includes different setting areas for configuring corresponding structures and circuits. The setting methods of the different areas are further described in the following paragraphs.
第一基板S1上設置有多工器電路區MUX。多工器電路區MUX包含複數個電晶體,這些電晶體與顯示面板DP的複數個資料線彼此耦接。通過這些電晶體的開關與否,將驅動電路的驅動訊號傳送至各個資料線,控制資料線上所耦接的各個像素單元。這些電晶體於基板上製作時,依據半導體製程在基板上製作各層薄膜的差異,使得在第一基板S1上的複數個電晶體具有第一臨界電壓。 A multiplexer circuit area MUX is provided on the first substrate S1. The multiplexer circuit area MUX includes a plurality of transistors, and these transistors are coupled to a plurality of data lines of the display panel DP. Through the switching of these transistors, the driving signal of the driving circuit is transmitted to each data line, and each pixel unit coupled to the data line is controlled. When these transistors are fabricated on the substrate, the difference between the various layers of thin films fabricated on the substrate according to the semiconductor manufacturing process makes the plurality of transistors on the first substrate S1 have the first threshold voltage.
另外,第一基板S1上設置有其他電路區NMUX。其他電路區NMUX為不屬於多工器電路區MUX的其他所有區域,在本實施例當中,其他電路區NMUX包含顯示區DA、非顯示區NDA以及覆晶式薄膜(Chip on film)區COF等。顯示區DA中包含複數個像素,其形成像素矩陣以顯示畫面。非顯示區NDA為顯示區DA外圍的電路區域,並用來設置感測訊號或是掃描訊號等之驅動電路。如圖所示,顯示區DA下方包含覆晶式薄膜區COF,其通過覆晶封裝的方式設置驅動晶片,由驅動晶片來提供複數個接點來產生像素區域當中資料線的驅動訊號,通過多工器電路區MUX的設置,可使一個接點同時提供多條資料線所需的驅動訊號,進而簡化電路設計及其所需空間。顯示區DA、非顯示區NDA以及覆晶式薄膜區COF是設置於其他電路區NMUX上,由於多工器電路區MUX與 其他電路區NMUX在製作過程中,可利用製程改變兩者的摻雜濃度,因此兩個區域當中的電晶體可具有不同的臨界電壓。 In addition, other circuit areas NMUX are provided on the first substrate S1. The other circuit area NMUX is all other areas that do not belong to the multiplexer circuit area MUX. In this embodiment, the other circuit area NMUX includes the display area DA, the non-display area NDA, and the chip on film area COF, etc. . The display area DA includes a plurality of pixels, which form a pixel matrix to display a picture. The non-display area NDA is a circuit area peripheral to the display area DA, and is used to set up driving circuits for sensing signals or scanning signals. As shown in the figure, the display area DA includes a flip-chip thin film area COF, which uses a flip-chip package to install a driver chip. The driver chip provides a plurality of contacts to generate driving signals for the data lines in the pixel area. The setting of MUX in the circuit area of the worker can enable a contact to provide the driving signals required by multiple data lines at the same time, thereby simplifying the circuit design and the required space. The display area DA, the non-display area NDA, and the flip-chip film area COF are arranged on the other circuit areas NMUX, because the multiplexer circuit area MUX and During the manufacturing process of the other circuit area NMUX, the doping concentration of the two can be changed by the process, so the transistors in the two areas can have different threshold voltages.
在製造過程中摻雜不同含量的元素,可通過設計覆蓋多工器電路區MUX範圍或其他電路區NMUX範圍的光罩來改變製程中的摻雜量,進而改變在特定區域內設置電晶體元件的臨界電壓。亦即,藉由調整製程中摻雜的元素含量以改變電晶體的臨界電壓,使第一基板S1上的多工器電路區MUX的複數個電晶體具有第一臨界電壓,而其他電路區NMUX的複數個電晶體具有不同於第一臨界電壓的第二臨界電壓。在本實施例中,第一臨界電壓與第二臨界電壓相差超過0.5V,藉由調整製程電性的電壓值,提高像素充電率,尤其是在高幀率情況下改善充電率不足之問題。 In the manufacturing process, elements of different contents are doped, and the amount of doping in the process can be changed by designing a mask covering the MUX range of the multiplexer circuit area or the NMUX range of other circuit areas, thereby changing the placement of transistor elements in a specific area The critical voltage. That is, by adjusting the content of elements doped in the process to change the threshold voltage of the transistor, the plurality of transistors in the multiplexer circuit region MUX on the first substrate S1 have the first threshold voltage, while the other circuit regions NMUX The plurality of transistors have a second threshold voltage different from the first threshold voltage. In this embodiment, the difference between the first threshold voltage and the second threshold voltage exceeds 0.5V. By adjusting the voltage value of the process electrical properties, the pixel charging rate is improved, especially in the case of high frame rate, the problem of insufficient charging rate is improved.
請參閱第2圖,其為本發明之顯示面板之多工器電路區的電流電壓曲線圖。透過上述所提到的改變元素的摻雜量,可以在一定的範圍內調整多工器電路區MUX的第一臨界電壓Vth1。舉例而言,當多工器電路區MUX中所使用的電晶體為N型電晶體且未調整時,原本第一基板S1上電晶體的臨界電壓都相同,舉例而言,多工器電路區MUX中電晶體的第一臨界電壓Vth1與其他電路區NMUX中電晶體的第二臨界電壓Vth2均為+1.2975V。在本實施例中,改變多工器電路區MUX的摻雜量,使得多工器電路區MUX中的電晶體的第一臨界電壓Vth1的電流電壓曲線(I-V curve)朝向負電壓偏移(shift),例如從+1.2975調整至-1V、-2V或是-5V等,其調整幅度可在0.5V以上,以使充電電流提升來改善像素充電率。 Please refer to FIG. 2, which is a current-voltage curve diagram of the multiplexer circuit area of the display panel of the present invention. By changing the doping amount of the elements mentioned above, the first threshold voltage Vth1 of the multiplexer circuit region MUX can be adjusted within a certain range. For example, when the transistors used in the multiplexer circuit area MUX are N-type transistors and are not adjusted, the threshold voltages of the transistors on the first substrate S1 are all the same. For example, the multiplexer circuit area The first threshold voltage Vth1 of the transistor in the MUX and the second threshold voltage Vth2 of the transistor in the other circuit area NMUX are both +1.2975V. In this embodiment, the doping amount of the multiplexer circuit area MUX is changed so that the current-voltage curve (IV curve) of the first threshold voltage Vth1 of the transistor in the multiplexer circuit area MUX shifts toward a negative voltage. ), for example, adjust from +1.2975 to -1V, -2V or -5V, etc. The adjustment range can be above 0.5V to increase the charging current to improve the pixel charging rate.
在另一實施例當中,舉例而言,多工器電路區MUX的電晶體為P型電晶體且未調整時,第一臨界電壓Vth1與第二臨界電壓Vth2可均為-1.2975V。 當改變多工器電路區MUX中的電晶體的臨界電壓後,第一臨界電壓Vth1的電流電壓曲線(I-V curve)朝向正電壓偏移(shift),例如從-1.2975V調整至+1V、+2V或是+3V等,其調整幅度同樣可在0.5V以上,以使像素充電率獲得改善。 In another embodiment, for example, when the transistor of the multiplexer circuit region MUX is a P-type transistor and is not adjusted, the first threshold voltage Vth1 and the second threshold voltage Vth2 may both be -1.2975V. When the threshold voltage of the transistor in the multiplexer circuit area MUX is changed, the current-voltage curve (IV curve) of the first threshold voltage Vth1 is shifted toward a positive voltage, for example, adjusted from -1.2975V to +1V, + 2V or +3V, etc., the adjustment range can also be above 0.5V to improve the pixel charging rate.
通過上述對於多工器電路區MUX中的電晶體的臨界電壓調整,可使得其中的電晶體有較大的充電電流,提高像素的充電率,於此同時,製作多工器電路區MUX當中的電晶體電路,僅需使用到N型電晶體製程或是P型電晶體製程,能減少製程步驟及成本,降低製程的複雜度以提升生產效率。 Through the above adjustment of the threshold voltage of the transistors in the multiplexer circuit area MUX, the transistors in the multiplexer circuit area MUX can be made to have a larger charging current, and the charging rate of the pixels can be improved. At the same time, the multiplexer circuit area MUX is manufactured The transistor circuit only needs to use the N-type transistor process or the P-type transistor process, which can reduce process steps and costs, reduce the complexity of the process, and improve production efficiency.
請參閱第3圖,其為本發明實施例之多工器電路區的配置圖。如圖所示,多工器電路區MUX1為1對3的電路設置,其接收覆晶式薄膜區COF1當中驅動晶片所提供的資料訊號,傳送至顯示區DA1的各個像素。 Please refer to FIG. 3, which is a configuration diagram of a multiplexer circuit area according to an embodiment of the present invention. As shown in the figure, the multiplexer circuit area MUX1 is a 1-to-3 circuit arrangement, which receives data signals provided by the driving chip in the flip-chip film area COF1 and transmits them to each pixel in the display area DA1.
在本實施例中,顯示區DA1包含複數個像素所形成的像素陣列,其分別為第一像素P11、第二像素P12、第三像素P13、第四像素P14、第五像素P15及第六像素P16,分別耦接於提供資料訊號的第一資料線DL11、第二資料線DL12、第三資料線DL13、第四資料線DL14、第五資料線DL15及第六資料線DL16。在本實施例中,第一像素P11及第四像素P14為紅色像素,第二像素P12及第五像素P15為綠色像素,第三像素P13及第六像素P16為藍色像素。然而,本揭露不侷限於此,第一像素P11及第四像素P14也可以為藍色像素,第二像素P12及第五像素P15也可以為綠色像素,第三像素P13及第六像素P16也可以為紅色像素,各個像素的配置方式可依據顯示面板需求而調整。 In this embodiment, the display area DA1 includes a pixel array formed by a plurality of pixels, which are respectively a first pixel P11, a second pixel P12, a third pixel P13, a fourth pixel P14, a fifth pixel P15, and a sixth pixel. P16 is respectively coupled to the first data line DL11, the second data line DL12, the third data line DL13, the fourth data line DL14, the fifth data line DL15, and the sixth data line DL16 that provide data signals. In this embodiment, the first pixel P11 and the fourth pixel P14 are red pixels, the second pixel P12 and the fifth pixel P15 are green pixels, and the third pixel P13 and the sixth pixel P16 are blue pixels. However, the present disclosure is not limited to this. The first pixel P11 and the fourth pixel P14 may also be blue pixels, the second pixel P12 and the fifth pixel P15 may also be green pixels, and the third pixel P13 and the sixth pixel P16 may also be It can be a red pixel, and the configuration of each pixel can be adjusted according to the needs of the display panel.
覆晶式薄膜區COF1包含正電壓源接點N11以及負電壓源接點N12,由正電壓源N11通過多工器電路耦接第一資料線DL11、第三資料線DL13及第五資料線DL15,提供第一像素P11、第三像素P13及第五像素P15的資料訊 號,而負電壓源接點N12通過多工器電路耦接第二資料線DL12、第四資料線DL14及第六資料線DL16,提供第二像素P12、第四像素P14及第六像素P16的資料訊號。藉由一個接點即可提供三個像素區域資料線路所需的訊號,無須每個資料線路都設置訊號接點,有效降低覆晶式薄膜區COF1所需的電路設置區域。此外,通過正負電壓訊號的交錯設置,能使得顯示區DA1當中各個像素的顯示效果更為均勻。 The flip chip film region COF1 includes a positive voltage source contact N11 and a negative voltage source contact N12. The positive voltage source N11 is coupled to the first data line DL11, the third data line DL13, and the fifth data line DL15 through a multiplexer circuit. , Provide data information of the first pixel P11, the third pixel P13, and the fifth pixel P15 The negative voltage source contact N12 is coupled to the second data line DL12, the fourth data line DL14, and the sixth data line DL16 through the multiplexer circuit to provide the second pixel P12, the fourth pixel P14, and the sixth pixel P16. Data signal. A single contact can provide the signals required by the data circuits of the three pixel areas, and there is no need to set a signal contact for each data circuit, which effectively reduces the circuit setting area required for the flip-chip film area COF1. In addition, the staggered arrangement of the positive and negative voltage signals can make the display effect of each pixel in the display area DA1 more uniform.
為使正電壓源接點N11以及負電壓源接點N12能提供資料訊號至第一像素P11至第六像素P16,多工器電路區MUX1中設置了第一電晶體T11、第二電晶體T12、第三電晶體T13、第四電晶體T14個第五電晶體T15以及第六電晶體T16,以及控制上述電晶體的第一控制訊號線MUX11、第二控制訊號線MUX12以及第三控制訊號線MUX13。通過這些控制訊號線決定電晶體的開啟或關閉,決定將資料訊號傳送至對應的資料線。在本實施例中,是以N型電晶體製程為例來製作第一電晶體T11至第六電晶體T16,但本揭露不以此為限,在其他實施例中,也可以P型電晶體製程來製作上述的電晶體。由於通過P型電晶體製程來製作,原本顯示面板上的電晶體的臨界電壓(如前所述的第二臨界電壓Vth2)為負電壓,而通過對多工器電路區MUX1進行調整後,於其中形成的第一電晶體T11至第六電晶體T16,其臨界電壓(如前所述的第一臨界電壓Vth1)可調整為正電壓。與前述實施例類似地,由於多工器電路區MUX1當中的元件電性已進行調整,當第一電晶體T11至第六電晶體T16操作時能藉由較高的充電電流來避免充電不足的情況產生。另外,由於高幀率的運用使得每一條線路操作時間較短,即便產生部分漏電流,也並不會影響顯示效果。 In order to enable the positive voltage source contact N11 and the negative voltage source contact N12 to provide data signals to the first pixel P11 to the sixth pixel P16, a first transistor T11 and a second transistor T12 are provided in the multiplexer circuit area MUX1 , The third transistor T13, the fourth transistor T14, the fifth transistor T15 and the sixth transistor T16, and the first control signal line MUX11, the second control signal line MUX12, and the third control signal line that control the above-mentioned transistors MUX13. These control signal lines determine whether the transistor is turned on or off, and the data signal is determined to be sent to the corresponding data line. In this embodiment, the N-type transistor process is taken as an example to fabricate the first transistor T11 to the sixth transistor T16, but the disclosure is not limited to this. In other embodiments, P-type transistors may also be used. Process to make the above-mentioned transistor. Due to the P-type transistor manufacturing process, the threshold voltage of the transistor on the display panel (the second threshold voltage Vth2 as described above) is a negative voltage, and after adjusting the multiplexer circuit area MUX1, The threshold voltage of the first transistor T11 to the sixth transistor T16 formed therein (the first threshold voltage Vth1 as described above) can be adjusted to a positive voltage. Similar to the foregoing embodiment, since the electrical properties of the components in the multiplexer circuit area MUX1 have been adjusted, when the first transistor T11 to the sixth transistor T16 are operating, a higher charging current can be used to avoid insufficient charging. The situation arises. In addition, due to the use of high frame rate, the operation time of each line is shorter, even if a part of the leakage current occurs, it will not affect the display effect.
進一步說明多工器電路區MUX1的電路配置,第一電晶體T11包含第一端、第二端及控制端,第一端通過第一資料線DL11連接第一像素P11,第二端連接正電壓源接點N11,控制端連接第一控制訊號線MUX11。第二電晶體T12包含第一端、第二端及控制端,第一端通過第五資料線DL15連接第五像素P15,第二端連接正電壓源接點N11,控制端連接第二控制訊號線MUX12。第三電晶體T13包含第一端、第二端及控制端,第一端通過第三資料線DL13連接第三像素P13,第二端連接正電壓源接點N11,控制端連接第三控制訊號線MUX13。第四電晶體T14包含第一端、第二端及控制端,第一端通過第四資料線DL14連接第四像素P14,第二端連接負電壓源接點N12,控制端連接第一控制訊號線MUX11。第五電晶體T15包含第一端、第二端及控制端,第一端通過第二資料線DL12連接第二像素P12,第二端連接負電壓源接點N12,控制端連接第二控制訊號線MUX12。第六電晶體T16包含第一端、第二端及控制端,第一端通過第六資料線DL16連接第六像素P16,第二端連接負電壓源接點N12,控制端連接第三控制訊號線MUX13。 To further illustrate the circuit configuration of the multiplexer circuit area MUX1, the first transistor T11 includes a first terminal, a second terminal, and a control terminal. The first terminal is connected to the first pixel P11 through the first data line DL11, and the second terminal is connected to a positive voltage. The source contact N11, the control terminal is connected to the first control signal line MUX11. The second transistor T12 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the fifth pixel P15 through the fifth data line DL15, the second terminal is connected to the positive voltage source contact N11, and the control terminal is connected to the second control signal Line MUX12. The third transistor T13 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the third pixel P13 through the third data line DL13, the second terminal is connected to the positive voltage source contact N11, and the control terminal is connected to the third control signal Line MUX13. The fourth transistor T14 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the fourth pixel P14 through the fourth data line DL14, the second terminal is connected to the negative voltage source contact N12, and the control terminal is connected to the first control signal Line MUX11. The fifth transistor T15 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the second pixel P12 through the second data line DL12, the second terminal is connected to the negative voltage source contact N12, and the control terminal is connected to the second control signal Line MUX12. The sixth transistor T16 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the sixth pixel P16 through the sixth data line DL16, the second terminal is connected to the negative voltage source contact N12, and the control terminal is connected to the third control signal Line MUX13.
應當注意的是,為使像素能夠依照正電壓、負電壓交錯方式排列,因此,第二資料線DL12與第五資料線DL15於多工器電路區MUX1與顯示區DA1之間後方交叉,使得第二資料線DL12連接至第五電晶體T15,而第五資料線DL15連接第二電晶體T12。這種連接方式,使相鄰的兩個像素之間的電壓差較大,每個像素本身所使用之汲極-源極電壓(Drain to Source Voltage,Vds)較小,也就是說,在此架構下的相對漏電流量較小。在漏電流量不超過容許程度的情況下,可再進一步藉由調整摻雜的元素量將多工器電路區MUX1的電晶體的臨界電壓繼續往負電壓偏移,以提高像素充電率。此外,讓同一個電壓源接點單獨 負責正向電壓或負向電壓的傳遞,也可減少接點因電壓差所產生的功耗,提升裝置效能。 It should be noted that, in order to enable the pixels to be arranged in an alternating manner of positive and negative voltages, the second data line DL12 and the fifth data line DL15 intersect behind the multiplexer circuit area MUX1 and the display area DA1, so that the first The two data lines DL12 are connected to the fifth transistor T15, and the fifth data line DL15 is connected to the second transistor T12. This connection method makes the voltage difference between two adjacent pixels larger, and the drain to source voltage (Vds) used by each pixel itself is smaller, that is to say, here The relative leakage current under the architecture is small. When the amount of leakage current does not exceed the allowable level, the threshold voltage of the transistor of the multiplexer circuit region MUX1 can be further shifted to a negative voltage by adjusting the amount of doped elements to increase the pixel charging rate. In addition, let the same voltage source contact separately Responsible for the transmission of positive or negative voltage, it can also reduce the power consumption of the contact due to the voltage difference, and improve the performance of the device.
請參閱第4圖,其為本發明另一實施例之多工器電路區的配置圖。於本實施例中,與前述實施例相同之元件,其技術特徵不再重複描述。如圖所示,多工器電路區MUX2同為1對3的電路設置,其接收覆晶式薄膜區COF2所提供的資料訊號,傳送至顯示區DA2的各個像素。 Please refer to FIG. 4, which is a configuration diagram of a multiplexer circuit area according to another embodiment of the present invention. In this embodiment, the technical features of the same elements as those in the previous embodiment will not be described repeatedly. As shown in the figure, the multiplexer circuit area MUX2 is a one-to-three circuit arrangement, which receives the data signal provided by the flip-chip film area COF2 and transmits it to each pixel in the display area DA2.
顯示區DA2包含第一像素P21、第二像素P22、第三像素P23、第四像素P24、第五像素P25及第六像素P26,分別耦接於提供資料訊號的第一資料線DL21、第二資料線DL22、第三資料線DL23、第四資料線DL24、第五資料線DL25及第六資料線DL26。在本實施例中,第一像素P21及第四像素P24為紅色像素,第二像素P22及第五像素P25為綠色像素,第三像素P23及第六像素P26為藍色像素。 The display area DA2 includes a first pixel P21, a second pixel P22, a third pixel P23, a fourth pixel P24, a fifth pixel P25, and a sixth pixel P26, which are respectively coupled to the first data line DL21 and the second data line DL21, which provide data signals. The data line DL22, the third data line DL23, the fourth data line DL24, the fifth data line DL25, and the sixth data line DL26. In this embodiment, the first pixel P21 and the fourth pixel P24 are red pixels, the second pixel P22 and the fifth pixel P25 are green pixels, and the third pixel P23 and the sixth pixel P26 are blue pixels.
覆晶式薄膜區COF2具有正電壓源接點N21以及負電壓源接點N22,正電壓源N21通過多工器電路耦接第一資料線DL21、第三資料線DL23及第五資料線DL25,提供第一像素P21、第三像素P23及第五像素P25的資料訊號,而負電壓源接點N22通過多工器電路耦接第二資料線DL22、第四資料線DL24及第六資料線DL26,提供第二像素P22、第四像素P24及第六像素P26的資料訊號。 The flip chip film region COF2 has a positive voltage source contact N21 and a negative voltage source contact N22. The positive voltage source N21 is coupled to the first data line DL21, the third data line DL23, and the fifth data line DL25 through a multiplexer circuit. Provide data signals for the first pixel P21, the third pixel P23, and the fifth pixel P25, and the negative voltage source contact N22 is coupled to the second data line DL22, the fourth data line DL24, and the sixth data line DL26 through the multiplexer circuit , Provide data signals of the second pixel P22, the fourth pixel P24, and the sixth pixel P26.
多工器電路區MUX2中包含第一電晶體T21、第二電晶體T22、第三電晶體T23、第四電晶體T24、第五電晶體T25以及第六電晶體T26,以及控制上述電晶體的第一控制訊號線MUX21、第二控制訊號線MUX22以及第三控制訊號線MUX23。 The multiplexer circuit area MUX2 includes a first transistor T21, a second transistor T22, a third transistor T23, a fourth transistor T24, a fifth transistor T25, and a sixth transistor T26, as well as control the above-mentioned transistors The first control signal line MUX21, the second control signal line MUX22, and the third control signal line MUX23.
進一步說明多工器電路區MUX2的電路配置,第一電晶體T21包含第一端、第二端及控制端,第一端通過第一資料線DL21連接第一像素P21,第二端連接正電壓源接點N21,控制端連接第一控制訊號線MUX21。第二電晶體T22包含第一端、第二端及控制端,第一端通過第二資料線DL22連接第二像素P22,第二端連接負電壓源接點N22,控制端連接第二控制訊號線MUX22。第三電晶體T23包含第一端、第二端及控制端,第一端通過第三資料線DL23連接第三像素P23,第二端連接正電壓源接點N21,控制端連接第三控制訊號線MUX23。第四電晶體T24包含第一端、第二端及控制端,第一端通過第四資料線DL24連接第四像素P24,第二端連接負電壓源接點N22,控制端連接第一控制訊號線MUX21。第五電晶體T25包含第一端、第二端及控制端,第一端通過第五資料線DL25連接第五像素P25,第二端連接正電壓源接點N21,控制端連接第二控制訊號線MUX22。第六電晶體T26包含第一端、第二端及控制端,第一端通過第六資料線DL26連接第六像素P26,第二端連接負電壓源接點N22,控制端連接第三控制訊號線MUX23。 To further illustrate the circuit configuration of the multiplexer circuit area MUX2, the first transistor T21 includes a first terminal, a second terminal, and a control terminal. The first terminal is connected to the first pixel P21 through the first data line DL21, and the second terminal is connected to a positive voltage. The source contact N21, the control terminal is connected to the first control signal line MUX21. The second transistor T22 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the second pixel P22 through the second data line DL22, the second terminal is connected to the negative voltage source contact N22, and the control terminal is connected to the second control signal Line MUX22. The third transistor T23 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the third pixel P23 through the third data line DL23, the second terminal is connected to the positive voltage source contact N21, and the control terminal is connected to the third control signal Line MUX23. The fourth transistor T24 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the fourth pixel P24 through the fourth data line DL24, the second terminal is connected to the negative voltage source contact N22, and the control terminal is connected to the first control signal Line MUX21. The fifth transistor T25 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the fifth pixel P25 through the fifth data line DL25, the second terminal is connected to the positive voltage source contact N21, and the control terminal is connected to the second control signal Line MUX22. The sixth transistor T26 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the sixth pixel P26 through the sixth data line DL26, the second terminal is connected to the negative voltage source contact N22, and the control terminal is connected to the third control signal Line MUX23.
與前述實施例類似的是像素同樣依據正電壓、負電壓的交錯方式排列。但與前述實施例差異之處,是顯示區DA2與多工器電路區MUX2之間的資料線路並未交叉設置,反而是在覆晶式薄膜區COF2進行線路的交叉,即各個電晶體的第二端與接點之間,通過線路交叉使得第一電晶體T21、第三電晶體T23及第五電晶體T25連接正電壓源接點N21,第二電晶體T22、第四電晶體T24及第六電晶體T26連接負電壓源接點N22。 Similar to the foregoing embodiment, the pixels are also arranged in an interlaced manner of positive and negative voltages. However, the difference from the foregoing embodiment is that the data lines between the display area DA2 and the multiplexer circuit area MUX2 are not arranged crosswise. Instead, the lines are crossed in the flip-chip film area COF2, that is, the first part of each transistor Between the two ends and the contact point, the first transistor T21, the third transistor T23, and the fifth transistor T25 are connected to the positive voltage source contact N21 through the line crossing, and the second transistor T22, the fourth transistor T24, and the first transistor The six transistor T26 is connected to the negative voltage source contact N22.
以下藉由實例進一步說明本揭露的內容,當顯示面板在90Hz的幀率下調整第一臨界電壓Vth1的模擬測試結果如下表1所示,且其測試圖如第5圖所示。 The following examples are used to further illustrate the content of the disclosure. When the display panel adjusts the first threshold voltage Vth1 at a frame rate of 90 Hz, the simulation test results are shown in Table 1 below, and the test chart is shown in FIG. 5.
如表1所示,顯示面板原本電晶體的臨界電壓,即第二臨界電壓Vth2在60Hz的幀率下為1.2975V,像素的充電率大約為0.97,但隨著幀率提升至90Hz,各顏色的像素充電率下降至0.84~0.87,產生像素充電率嚴重不足的問題。因此,藉由本發明所揭露的控制摻雜元素以調整多工器電路區當中電晶體的臨界電壓,即第一臨界電壓Vth1,使第一臨界電壓Vth1朝向負電壓偏移,隨著第一臨界電壓Vth1的電流電壓曲線朝負電壓偏移,像素充電率逐漸提升。在本實例中,第一臨界電壓Vth1在調整至-1.0V時,像素充電率已明確地提升了10%,且仍隨著第一臨界電壓Vth1的偏移而繼續提升。因此,在不產生明顯的漏電流情況下,第一臨界電壓Vth1亦可以繼續朝向負電壓偏移。當調整至-2.0V時,其充電率可達到約0.97的效果。 As shown in Table 1, the threshold voltage of the original transistor of the display panel, that is, the second threshold voltage Vth2 is 1.2975V at a frame rate of 60Hz, and the charging rate of the pixel is about 0.97. However, as the frame rate increases to 90Hz, each color The pixel charging rate dropped to 0.84~0.87, resulting in a serious shortage of pixel charging rate. Therefore, by controlling the doping element disclosed in the present invention to adjust the threshold voltage of the transistor in the multiplexer circuit region, that is, the first threshold voltage Vth1, the first threshold voltage Vth1 is shifted toward the negative voltage, and as the first threshold The current-voltage curve of the voltage Vth1 shifts toward a negative voltage, and the pixel charging rate gradually increases. In this example, when the first threshold voltage Vth1 is adjusted to -1.0V, the pixel charging rate has clearly increased by 10%, and it continues to increase as the first threshold voltage Vth1 shifts. Therefore, without significant leakage current, the first threshold voltage Vth1 can also continue to shift toward a negative voltage. When adjusted to -2.0V, the charging rate can reach about 0.97.
在本實施例中,依據製程可調整多工器電路區的電晶體的整體臨界電壓,但本揭露不侷限於此,在另一實施例中,多工器電路區也可依據各個像素區域設置不同光罩,使得不同像素區域當中電晶體的臨界電壓有所不同。 舉例來說,表1當中臨界電壓的充電率在紅色像素較高,藍色像素的充電率較低。請同時參閱第5圖,其為本發明實施例之顯示面板調整臨界電壓的實際測試圖。如圖所示,當臨界電壓調整至-2.0V時,在每一個幀數中,會有紅色像素、綠色像素以及藍色像素的訊號產生,像素充電的順序依序是紅色像素、綠色像素以及藍色像素,使得紅色像素可以從時間點t1就充電至充電時間結束(即下一次發光),而綠色像素則從時間點t2開始充電至充電時間結束,亦即,藍色像素在充電時間上會相較綠色像素以及紅色像素較為不足(僅能從時間點t3開始充電),因此,藍色像素相較於綠色像素以及紅色像素需要更高的充電電流。對此,可進一步調正藍色像素區域的臨界電壓,使得其充電率進一步提升,即使得藍色像素區域中電晶體的臨界電壓大於綠色像素區域或紅色像素區域當中電晶體的臨界電壓。 In this embodiment, the overall threshold voltage of the transistor in the multiplexer circuit area can be adjusted according to the manufacturing process, but the disclosure is not limited to this. In another embodiment, the multiplexer circuit area can also be set according to each pixel area Different photomasks cause different threshold voltages of transistors in different pixel regions. For example, the charging rate of the threshold voltage in Table 1 is higher for the red pixels and lower for the blue pixels. Please also refer to FIG. 5, which is an actual test diagram for adjusting the threshold voltage of the display panel according to the embodiment of the present invention. As shown in the figure, when the threshold voltage is adjusted to -2.0V, in each frame number, signals of red pixels, green pixels, and blue pixels will be generated. The order of pixel charging is red pixels, green pixels, and The blue pixel allows the red pixel to be charged from time t1 to the end of the charging time (ie the next light emission), while the green pixel starts to be charged from time t2 to the end of the charging time, that is, the blue pixel is in the charging time Compared with the green pixels and the red pixels, it is insufficient (only charging can start from the time point t3). Therefore, the blue pixels require a higher charging current than the green pixels and the red pixels. In this regard, the threshold voltage of the blue pixel region can be further adjusted to further increase its charging rate, that is, the threshold voltage of the transistor in the blue pixel region is greater than the threshold voltage of the transistor in the green pixel region or the red pixel region.
請參閱第6圖,其為本發明另一實施例之顯示面板調整臨界電壓的測試圖。如圖所示,在每一個幀數中,會有紅色像素、綠色像素以及藍色像素的訊號產生(如中間圖所示),由最下方的各色像素的時間與電壓關係圖可以看出,紅色像素的電壓是最先下降,因此在這個時間內,電晶體導通使紅色像素獲得充電電流開始充電,接著是綠色像素的電壓下降開始充電,最後是藍色像素的電壓下降並開始充電。與前述實施例不同的是,當第一臨界電壓Vth1調整為-3.5V時,其像素電壓的圖形出現傾斜,產生漏電流的情況,相較於前一實施例調整至-2.0V可能影響顯示品質,因此調整的幅度應視顯示面板的幀率及其規格來決定。 Please refer to FIG. 6, which is a test chart of adjusting the threshold voltage of the display panel according to another embodiment of the present invention. As shown in the figure, in each frame number, signals of red pixels, green pixels and blue pixels are generated (as shown in the middle figure). It can be seen from the time and voltage relationship diagram of each color pixel at the bottom. The voltage of the red pixel drops first, so during this time, the transistor turns on to make the red pixel get a charging current to start charging, then the voltage of the green pixel drops to start charging, and finally the voltage of the blue pixel drops and starts charging. The difference from the previous embodiment is that when the first threshold voltage Vth1 is adjusted to -3.5V, the pixel voltage pattern is tilted, causing leakage current. Compared with the previous embodiment, adjusting to -2.0V may affect the display Therefore, the adjustment range should depend on the frame rate of the display panel and its specifications.
以下藉由另一實例進一步說明,當顯示面板的幀率由60Hz轉變成120Hz時,調整第一臨界電壓Vth1的模擬測試結果如表2所示。 Hereinafter, another example is used to further illustrate that when the frame rate of the display panel is changed from 60 Hz to 120 Hz, the simulation test result of adjusting the first threshold voltage Vth1 is shown in Table 2.
如表2所示,顯示面板原本電晶體的臨界電壓,即第二臨界電壓Vth2在60Hz的幀率下為1.2975V,像素的充電率大約為0.97,但隨著幀率提升至120Hz,各顏色的像素充電率下降至0.74~0.76,產生像素充電率嚴重不足的問題。當多工器電路區當中電晶體的臨界電壓進行調整,即第一臨界電壓Vth1朝向負電壓偏移,可使像素充電率得到改善,在本實例中,調整至-1.0V時,像素充電率已明確地提升了14%,當調整至-2.0V時,則充電率則可提升至約0.9。 As shown in Table 2, the threshold voltage of the original transistor of the display panel, that is, the second threshold voltage Vth2 is 1.2975V at a frame rate of 60Hz, and the charging rate of the pixel is about 0.97. However, as the frame rate increases to 120Hz, each color The pixel charging rate dropped to 0.74~0.76, resulting in a serious shortage of pixel charging rate. When the threshold voltage of the transistor in the multiplexer circuit area is adjusted, that is, the first threshold voltage Vth1 is shifted toward a negative voltage, the pixel charging rate can be improved. In this example, when adjusted to -1.0V, the pixel charging rate It has clearly increased by 14%, and when adjusted to -2.0V, the charging rate can be increased to about 0.9.
以上所述僅為舉例性,而非為限制性者。任何未脫離本發明之精神與範疇,而對其進行之等效修改或變更,均應包含於後附之申請專利範圍中。 The above descriptions are merely illustrative and not restrictive. Any equivalent modifications or alterations that do not depart from the spirit and scope of the present invention should be included in the scope of the appended patent application.
COF:覆晶式薄膜區 COF: Flip-chip thin film area
DA:顯示區 DA: display area
DP:顯示面板 DP: display panel
MUX:多工器電路區 MUX: Multiplexer circuit area
NDA:非顯示區 NDA: Non-display area
NMUX:其他電路區 NMUX: other circuit area
S1:第一基板 S1: First substrate
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Publication number | Priority date | Publication date | Assignee | Title |
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TW200809741A (en) * | 2006-04-28 | 2008-02-16 | Thales Sa | Organic light-emitting display screen |
TW200828206A (en) * | 2006-12-18 | 2008-07-01 | Wintek Corp | Multiplexing circuit for display |
KR20140115454A (en) * | 2013-03-19 | 2014-10-01 | 엘지디스플레이 주식회사 | Organic light emitting diode display device and driving method the same |
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KR20140115454A (en) * | 2013-03-19 | 2014-10-01 | 엘지디스플레이 주식회사 | Organic light emitting diode display device and driving method the same |
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