TWM578909U - Voltage level shifter capable of adjusting threshold voltage for integrated circuit - Google Patents

Abstract

The voltage level shifter is composed of a bias control circuit, two first transistors and two second transistors. The bias control circuit is electrically connected to the bases of the two first transistors and can generate a bias voltage. a voltage, and the drains of the two first transistors are electrically connected to the gate of one of the second transistors and the drain of the other second transistor, wherein the source and the substrate of the two second transistors are electrically connected Connected to one of a low potential input voltage and a high potential input voltage, and the sources of the two first transistors are electrically connected to the other of the low potential input voltage and the high potential input voltage, whereby the present voltage is The level shifter uses a bias control circuit to adjust the threshold voltage of the first transistor, thereby adjusting the low voltage value or the high voltage value of the input voltage signal.

Description

Voltage level shifter for integrated circuit adjustable threshold voltage value

The present invention relates to a voltage level shifter for an integrated circuit, and more particularly to a voltage level shifter mounted with a bias controller, such that the present voltage level shifter can be biased via a bias controller Adjusting the threshold voltage of the transistor, and further indirectly adjusting the low voltage of the input voltage signal or the operating range of the high voltage of the input voltage signal.

With the rapid development of technology, Thin-Film Transistor Liquid Crystal Display (TFT LCD) has been widely used in electronic products such as personal computer monitors, televisions, mobile phones and digital cameras. The clock signal is controlled to scan the thin film transistor array to sequentially display pixels. Since the clock signal requires a higher voltage level, the clock signal must first pass the voltage level shifter to convert the voltage level. The high voltage clock signal of the converted voltage level is supplied to the thin film transistor, and, thanks to the booming of semiconductor technology, the voltage level shifter is implemented in the form of an integrated circuit.

Please refer to FIG. 1 , which is a conventional voltage level shifter 1 currently used for a thin film transistor liquid crystal display. As shown, the conventional voltage level shifter 1 has a first voltage level shift. The unit 10 and a second voltage level shifting unit 11, the first voltage level shifting unit 10 has two first PMOS transistors 101 and two first NMOS transistors 102, and the second voltage level shift The unit 11 has two second PMOS transistors 111 and two second NMOS transistors 112.

As shown, the source of each of the first PMOS transistors 101 is electrically connected to an operating voltage (VDD), and the source of each of the first PMOS transistors 101 is electrically connected to the substrate. Then, the drains of each of the first PMOS transistors 101 are electrically connected to the gates of one of the first NMOS transistors 102 and the gate of the other first NMOS transistor 102 to form a first contact 12 and a second contact 13 and a source of each of the first NMOS transistors 102 are electrically connected to the substrate, wherein the source of each of the first NMOS transistors 102 is electrically connected to the reverse charge pump ( VGL).

In addition, the source of each of the second POMS transistors is electrically connected to the substrate, and the source of each of the second POMS transistors is electrically connected to a boosted charge pump (VGH), wherein each of the second NMOSs The source of the transistor 112 is electrically connected to the substrate, and the source of each of the second NMOS transistors 112 is electrically connected to the reverse charge pump (VGL), and the drain of each of the second NMOS transistors 112 is The gate of one of the second PMOS transistors 111 is electrically connected to the gate of the other second PMOS transistor 111, and the gate of one of the second NMOS transistors 112 is electrically connected to the first contact. 12, and the gate of the other second NMOS transistor 112 is electrically connected to the second contact 13.

In order to supply the high voltage pulse signal of the converted voltage level to the thin film transistor in a specific application, the transistor used in the conventional voltage level shifter 1 must be able to withstand a high voltage (greater than 30 volts). Moreover, it is known that the threshold voltage value of the transistor used in the voltage level shifter 1 is greater than the threshold voltage value of a common transistor, and the two first PMOS transistors 101 must be specially designed to be downgraded. a threshold voltage value (Vth) of a PMOS transistor 101, whereby when the gates of the two first PMOS transistors 101 receive an input voltage signal having a voltage level between GND and VDD, the first voltage level The quasi-shift unit 10 steps down the voltage level of the input voltage signal, thereby lowering the low voltage value of the voltage level, so that the low voltage value of the voltage level of the input voltage signal is changed from GND to VGL, thereby The voltage level of the input voltage signal is converted from GND~VDD to VGL~VDD.

Then, when the input voltage signal with the voltage level between VGL and VDD is transmitted to the two second NMOS transistors 112 of the second voltage level shifting unit 11 via the first contact 12 and the second contact 13 The second voltage level shifting unit 11 boosts the voltage level of the input voltage signal, so that the high voltage value of the voltage level is changed from VDD to VGH, thereby converting the voltage level from VGL~VDD to VGL. ~VGH, where GND is the voltage reference point, and VDD is the operating voltage, then VGL is the reverse charge pump, and VGH is the boost charge pump.

It can be seen from the foregoing description that when the voltage level shifter 1 of the conventional voltage level shifts or steps the voltage level of the input voltage signal, the conventional voltage level shifter 1 needs to use two specially designed two firsts. The PMOS transistor 101 can step down or boost the input voltage signal, so that the voltage level shifter 1 increases the material cost by using the specially designed two first PMOS transistors 101.

The main purpose of this creation is to use a specially designed transistor to adjust the high and low voltage values of the working voltage. The bias control circuit and a common transistor are used to adjust the critical value of the transistor, thereby further adjusting the operating voltage. The high and low voltage values enable the high and low voltage values of the operating voltage to be adjusted, and the material cost is reduced because no specially designed transistors are used.

In order to achieve the foregoing objective, the voltage level shifter for the integrated circuit adjustable threshold voltage is composed of two first transistors, two second transistors, and a bias control circuit, and the two first transistors are The threshold voltage of the first transistor is used to receive an input voltage signal, and the voltage level criterion of the input voltage signal is between a low voltage value and a high voltage value. And the drain of the first transistor is electrically connected to the gate of one of the second transistors and the drain of the other of the second transistors to form an output contact.

The source and the source and the substrate of the two second transistors are electrically connected to one of a low potential input voltage and a high potential input voltage, and the sources of the two first transistors are electrically connected to the above The other of the low potential input voltage and the high potential input voltage, wherein the bias voltage control The circuit is electrically connected to the bases of the two first transistors, and provides a bias voltage to the two first transistors to lower the threshold voltage of the first transistor to adjust the low voltage value and the high voltage value. One of them further converts the input voltage signal into an output voltage signal that is transmitted to the output contact, and the low voltage value or the high voltage value of the output voltage signal voltage level is different from the input voltage signal.

In a preferred embodiment, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor, and the high voltage value of the input voltage signal can be reduced by the bias voltage.

In another preferred embodiment, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor, and the low voltage value of the input voltage signal can be increased via the bias voltage.

In the foregoing two embodiments, the high-potential input voltage is set as an operating voltage (VDD) or a boosted charge pump (VGH), and the low-potential input voltage is set as a reverse charge pump (VGL), wherein the above The voltage of the reverse charge pump (VGL) is between -15 and -5 volts, and the voltage of the boosted charge pump (VGH) is between 10 and 50 volts. In addition, the bias control circuit is composed of two poles. One of the ways of stacking, stacking a reference voltage circuit or a diode stacking resistor produces a bias voltage.

The present invention is characterized in that only the bias control circuit, the two first transistors and the two second transistors are formed, so that the bias control circuit lowers the threshold voltage of the first transistor, thereby lowering the input voltage signal. The voltage value or the high voltage value can be adjusted. Therefore, the present invention uses four transistors and a bias control circuit to cause the bias control circuit to lower the threshold voltage of the transistor, thereby adjusting the high and low voltage values of the output input voltage signal. This can also reduce material costs by reducing the use of specially designed transistors.

1‧‧‧Preferred voltage level shifter

10‧‧‧First voltage level shifting unit

101‧‧‧First PMOS transistor

102‧‧‧First NMOS transistor

11‧‧‧Second voltage level shifting unit

111‧‧‧Second PMOS transistor

112‧‧‧Second NMOS transistor

12‧‧‧ first joint

13‧‧‧second junction

2‧‧‧Voltage level shifter for integrated circuit adjustable threshold voltage

20‧‧‧First transistor

21‧‧‧Second transistor

22‧‧‧ bias control circuit

23‧‧‧Output contacts

3‧‧‧Boost voltage level shifter

4‧‧‧Step-down voltage level shifter

1 is a schematic diagram of a conventional voltage level shifter for an integrated circuit; FIG. 2 is a schematic diagram of a voltage level shifter for creating an adjustable threshold voltage of an integrated circuit in a first preferred embodiment; 3 is a schematic diagram of a specific application of a voltage level shifter for creating an adjustable threshold voltage of an integrated circuit in a first preferred embodiment; FIG. 4 is a voltage level for creating an adjustable threshold voltage of an integrated circuit. A schematic diagram of a quasi-shifter in a second preferred embodiment; FIG. 5 is a schematic diagram of a specific application of a voltage level shifter for an integrated circuit adjustable threshold voltage value in a second preferred embodiment; and FIG. This is a schematic diagram of a third preferred embodiment of a voltage level shifter for creating an adjustable threshold voltage value for an integrated circuit.

In order to further understand the structure, use and characteristics of this creation, there is a deeper and clearer understanding and understanding. The preferred embodiment is described in detail with reference to the following figures: Please refer to Figure 2 for the first In a preferred embodiment, the voltage level shifter 2 for an integrated circuit adjustable threshold voltage is mounted on an integrated circuit and controlled by two first transistors 20, two second transistors 21, and a bias voltage. The circuit 22 is configured. The two first transistor 20 and the two second transistors 21 have a source, a drain, a substrate and a gate, and both of the first transistors 20 have a threshold indicating a voltage level. The voltage value is that the two first transistors 20 are respectively set as PMOS transistors, and the two second transistors 21 are set as NMOS transistors.

As shown, the source of each of the first transistors 20 is electrically connected to an operating voltage (VDD) as a high-potential input voltage, and the substrate of each of the first transistors 20 is electrically connected to the bias control circuit. 22, wherein the drain of one of the second transistors 21 and the gate of the other of the second transistors 21 are electrically connected to the drain of the same first transistor 20 to form an output contact 23, and each The source of a second transistor 21 is electrically connected to a reverse charge pump (VGL) electrically connected to a low potential input voltage, and the voltage of the reverse charge pump (VGL) is less than the above operating voltage. The voltage value of (VDD), in addition, the base and the source of each of the second transistors 21 are electrically connected to each other. In this embodiment, the voltage of the reverse charge pump (VGL) is between -15 and - 5 volts to constitute the above low potential input voltage.

Referring to FIG. 3, the voltage level shifter 2 for an integrated circuit adjustable threshold voltage value is used for the integrated circuit to adjust the threshold voltage value of the voltage level shifter 2 for reducing the input. The threshold value of the voltage signal, and the output contact 23 is electrically connected to a boost voltage level shifter 3, and the boost voltage level shifter 3 is used to increase the voltage value of the input voltage signal, as shown in the figure. The gates of the two first transistors 20 receive an input voltage signal, and the voltage level of the input voltage signal is between a low voltage value and a high voltage value, as shown in the figure, the low voltage of the input voltage signal The value is set to GND higher than the low potential input voltage, and the high voltage value of the input voltage signal is set to VDD which is the same as the high potential input voltage, and further, the bias control circuit 22 generates a bias voltage (VP1). And transmitting the bias voltage (VP1) to the base of each of the first transistors 20. In this embodiment, the bias voltage (VP1) lowers the threshold voltage of the first transistor 20, and further inputs the input. The high voltage value of the voltage signal is VDD The lower voltage value GND of the input voltage signal is reduced by the assembly between the two first transistors 20 and the two second transistors 21, whereby the input voltage signal passes through the bias voltage ( VP1) lowering the threshold voltage value of the first transistor 20 and the two first transistors 20 and The assembly mode between the two second transistors 21 reduces the high voltage value of the input voltage signal and the low voltage value of the input voltage signal, thereby converting the voltage level of the input voltage signal from GND to VDD to VGL~VDD forms an output voltage signal, and the output voltage signal is transmitted to the output contact 23, wherein GND is a voltage reference point (for example, ground), and the voltage of the bias voltage (VP1) is smaller than the working voltage. (VDD), in this embodiment, the bias control circuit is biased by one of a diode stacking method, a differential reference voltage circuit, or a diode stacked resistor.

In addition, the bias voltage (VP1) is adjusted to lower the threshold voltage of the first transistor 20 by a body effect, wherein the body effect can be expressed as:

Where |V _th0 | is |V _th | at V _sb =0V, and γ is the body effect coefficient, It is the Fermi potential, and therefore, the threshold voltage |V _th | becomes smaller as V _sb increases.

Then, when the output voltage signal is transmitted to the boost voltage level shifter 3 via the output contact 23, the output voltage signal is boosted by the boost voltage level shifter 3 to increase the input voltage signal. The high voltage value VDD converts the high voltage value VDD of the output voltage signal to VGH, and the voltage level of the output voltage signal is converted from VGL~VDD to VGL~VGH.

Referring to FIG. 4, in the second preferred embodiment, the difference from the first preferred embodiment is that the first transistor 20 and the second transistor 21 are the same as the first bias control circuit 22. The embodiment, and thus the description will not be repeated in this embodiment.

In this embodiment, the two first transistors 20 are both NMOS transistors, and the two second transistors 21 are all PMOS transistors. As shown, the source electrical properties of each of the first transistors 20 are shown. connection The reverse charge pump (VGL) is used as a low potential input voltage, and the source of each of the second transistors 21 is electrically connected to a boosted charge pump (VGH) as a high potential input voltage.

Referring to FIG. 5, a voltage level shifter 2 for an integrated circuit adjustable threshold voltage value is used in an application to increase the input of a voltage level shifter 2 for an integrated circuit adjustable threshold voltage value. The voltage value of the voltage signal is used in conjunction with a step-down voltage level shifter 4, and the step-down voltage level shifter 4 is used to reduce the voltage value of the input voltage signal, as shown in the figure, the step-down voltage level The quasi-shifter 4 receives an input voltage signal, and the voltage level of the input voltage signal is between a low voltage value and a high voltage value as in the first preferred embodiment. As shown in the figure, the input voltage signal is The low voltage value is set to be higher than the GND of the low potential input voltage, and the high voltage value of the input voltage signal is set to be the same as the VDD of the high potential input voltage, and the step voltage level shifter 4 sets the voltage level. The input voltage signal between GND and VDD is converted to an input voltage signal with a voltage level between VGL and VDD.

Subsequently, the step-down voltage level shifter 4 transfers the input voltage signal having a voltage level between VGL and VDD to each of the voltage level shifters 2 for the integrated circuit adjustable threshold voltage value. a gate of the transistor 20, and the bias control circuit 22 generates a bias voltage (VP2) and transmits the bias voltage (VP2) to the substrate of each of the first transistors 20, in the embodiment described above The bias voltage (VP2) lowers the threshold voltage of the first transistor 20, thereby increasing the low voltage value of the input voltage signal, and the high voltage value VDD of the input voltage signal passes through the two first transistors 20 and The assembly mode of the two second transistors 21 is increased, so that the voltage level of the input voltage signal is converted from VGL~VDD to VGL~VGH to form an output voltage signal transmitted to the output contact 23, resulting in an output voltage signal. The high and low voltage values of the output voltage signal are different from the high and low voltage values of the input voltage signal. Therefore, the voltage level shifter 2 for the integrated circuit adjustable threshold voltage is only required to be four. Electricity The crystal matching bias control circuit 22 can adjust the threshold value of the input voltage signal. In this embodiment, the voltage of the reverse charge pump (VGL) is between -15 and -5 volts to form a low voltage, and the voltage is boosted. The charge pump (VGH) voltage value is between 10 and 50 volts to form a high voltage, wherein the voltage value of the bias voltage (VP2) is greater than the voltage value of the reverse charge pump (VGL).

Referring to FIG. 6, in the third preferred embodiment, the difference from the first preferred embodiment is that the voltage level shifter 2 for the integrated circuit adjustable threshold voltage value is connected to the other as the second. The voltage level shifter 2 for an integrated circuit adjustable threshold voltage value of the preferred embodiment, and one of the voltage level shifters 2 for the integrated circuit adjustable threshold voltage to apply the voltage of the input voltage signal The level is converted from GND~VDD to VGL~VDD, which converts the input voltage signal into an output voltage signal that is transmitted to the output contact 23, and the other is a voltage level shifter that can adjust the threshold voltage of the integrated circuit. 2 Convert the voltage level of the above output voltage signal from VGL~VDD to VGL~VGH.

The above embodiments are not intended to limit the scope of the present invention. It is included in the scope of the following patent application.

Claims (6)

A voltage level shifter for an integrated circuit adjustable threshold voltage value, comprising two first transistors, two second transistors and a bias control circuit, wherein the two first transistors have a voltage level a threshold voltage value, and the gates of the two first transistors are used to receive an input voltage signal, and the voltage level criterion of the input voltage signal is between a low voltage value and a high voltage value, and the first The drain of the transistor is electrically connected to the gate of one of the second transistors and the drain of the other of the second transistors to form an output contact; both the source and the substrate of the second transistor are electrically Connected to one of a low potential input voltage and a high potential input voltage, and the sources of the two first transistors are electrically connected to the other of the low potential input voltage and the high potential input voltage; The bias control circuit is electrically connected to the bases of the two first transistors, and provides a bias voltage to the two first transistors to lower the threshold voltage of the first transistor to adjust One of a low voltage value and a high voltage value, thereby converting the input voltage signal into an output voltage signal transmitted to the output contact, and the low voltage value or high voltage value of the output voltage signal voltage level is different from the above Input voltage signal. The voltage level shifter for an integrated circuit adjustable threshold voltage value according to claim 1, wherein the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. The high voltage value of the input voltage signal can be lowered by the bias voltage. The voltage level shifter for an integrated circuit adjustable threshold voltage value according to claim 1, wherein the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor. The low voltage value of the input voltage signal can be increased by the bias voltage. The voltage level shifter for an integrated circuit adjustable threshold voltage value according to Item 1, wherein the high potential input voltage is set to an operating voltage (VDD) or a boosted charge pump (VGH). The low potential input voltage is set to the reverse charge pump (VGL). The voltage level shifter for an integrated circuit adjustable threshold voltage value according to claim 4, wherein the reverse charge pump (VGL) has a voltage value between -15 and -5 volts, and the above The boost charge pump (VGH) voltage is between 10 and 50 volts. The voltage level shifter for an integrated circuit adjustable threshold voltage value according to Item 1, wherein the bias control circuit is a diode stacking method, a differential reference voltage circuit or a diode One of the ways in which the body stack resistors generate a bias voltage.