JP3221221U - Adjustable critical voltage level shifter for integrated circuits - Google Patents

Abstract

An adjustable voltage level shifter of critical voltage values for an integrated circuit is provided. The two first transistors have critical voltage values that indicate voltage levels, and the gates of the two first transistors are formed of two first transistors, two second transistors, and a bias control circuit. Used to receive an input voltage signal, the voltage level of the input voltage signal is between the low voltage value and the high voltage value, and the drain of the first transistor is the gate of one of the second transistors and the other of the other At the same time, it is electrically connected to the drain of the transistor to form the output contact 23. The present invention is specially designed because the bias control circuit lowers the critical voltage value of the transistor and adjusts the high and low voltage values of the output input voltage signal using four transistors and one bias control circuit. By not using a transistor, the cost of the material can be reduced. [Selected figure] Figure 2

Description

  The present invention relates to voltage level shifters for integrated circuits, and in particular, since a bias controller is attached, the bias controller adjusts the critical voltage value of the transistor and further indirectly controls the low voltage or high voltage operation range of the input voltage signal. The present invention relates to a voltage level shifter that can be adjusted.

  As science and technology progress, thin-film transistor liquid crystal displays (TFT LCDs) have become very universally applicable to electronic products such as personal computer displays, televisions, cell phones and digital cameras. Become. The thin film transistor may be controlled to scan the thin film transistor array by a frequency signal in order to display image elements sequentially when operating. Since the frequency signal requires a high voltage level, the voltage level is converted by the voltage level shifter, and then the converted high voltage frequency signal of the voltage level must be supplied to the thin film transistor. Also, with the active development of semiconductor technology, voltage level shifters are achieved in the form of integrated circuits.

  See FIG. FIG. 1 shows a known voltage level shifter 1 used in a conventional thin film transistor liquid crystal display. As shown in the drawings, the known voltage level shifter 1 comprises a first voltage level shifting unit 10 and a second voltage level shifting unit 11. The first voltage level shift unit 10 includes two first PMOS transistors 101 and two first NMOS transistors 102. The second voltage level shift unit 11 includes two second PMOS transistors 111 and two second NMOS transistors 112.

  As shown in the drawing, when each of the first PMOS transistors 101 is electrically connected to the working voltage (VDD) at its source and electrically connected to the base, the drains thereof are respectively connected to one of the first NMOS transistors. The first contact 12 and the second contact 13 are formed simultaneously and electrically connected to the drain of the second transistor 102 and the gate of the other first NMOS transistor 102. Also, each of the first NMOS transistors 102 is electrically connected to the base and any one of its sources, and is electrically connected to the reverse charge (VGL).

  Note that each of the second POMS transistors is electrically connected to the base and any of its sources, and is electrically connected to the boost charge charge (VGH). Each of the second NMOS transistors 112 has its source electrically connected to the base and is electrically connected to the reverse charge (VGL), and its drain is the drain of its one second PMOS transistor 111 and the other second PMOS The gate of the transistor 111 is simultaneously electrically connected, and the gate of one of the second NMOS transistors 112 is electrically connected to the first contact 12 and the gate of the other second NMOS transistor 112 is electrically connected to the second contact 13. Connected.

  When applied specifically, the transistors used in the known voltage level shifter 1 must withstand high voltages (greater than 30 v) in order to supply the thin film transistor with a converted high voltage frequency signal of voltage level, Furthermore, the critical voltage value of the transistor used in the known voltage level shifter 1 is larger than the critical voltage value of the generally observed transistor, and two threshold voltages (Vth) of the first PMOS transistor 101 are reduced. The first PMOS transistor 101 has to be specially designed. As a result, the gates of the two first PMOS transistors 101 receive input voltage signals at voltage levels GND to VDD, decompress the voltage level of the input voltage signal of the first voltage level shift unit 10, and The low voltage value is lowered to change the low voltage value of the voltage level of the input voltage signal from GND to VGL, and further, the voltage level of the input voltage signal is converted from GND to VDD to VGL to VDD.

  Thereafter, when an input voltage signal at a voltage level of VGL to VDD is transmitted to the two second NMOS transistors 112 of the second voltage level shift unit 11 through the first contact 12 and the second contact 13, the second voltage level shift is performed. The unit 11 boosts the voltage level of the input voltage signal to change the high voltage value of the voltage level from VDD to VGH, and further converts the voltage level from VGL to VDD to VGL to VGH. GND is a voltage reference point, VDD is a working voltage, VGL is reverse charge charging, and VGH is boost charge charging.

  As can be understood from the above description, the known voltage level shifter 1 is specially designed to decompress or boost the input voltage signal when the voltage level of the input voltage signal is decompressed or boosted. The first PMOS transistor 101 must be used. Furthermore, the known voltage level shifter 1 increases the cost of the material by using two specially designed first PMOS transistors 101.

  The main objective of the present invention is to adjust the high and low voltage values of the working voltage without using specially designed transistors. By adjusting the critical value of the transistor by the bias control circuit and the commonly found transistor, and further adjusting the high and low voltage value of the working voltage, not only can the high and low voltage value of the working voltage be adjusted, but also specially designed. The cost of the material is reduced because no transistors are used.

  In order to achieve the above object, the adjustable voltage level shifter of the critical voltage value for the integrated circuit of the present invention comprises two first transistors, two second transistors and a bias control circuit, and the two first transistors Has a critical voltage value indicative of a voltage level, the gates of the two first transistors being used to receive an input voltage signal, the voltage level of the input voltage signal being between a low voltage value and a high voltage value And the drain of the first transistor is simultaneously electrically connected to the gate of one of the second transistors and the drain of the other second transistor to form an output contact.

  The sources, sources, and bases of the two second transistors are all electrically connected to one of the low potential input voltage and the high potential input voltage, and the sources of the two first transistors are the low potential input voltage and the high potential. The first transistor is electrically connected to the other of the input voltages, the bias control circuit is electrically connected simultaneously to the bases of the two first transistors, and provides a bias voltage to the two first transistors. Lower one of the low voltage value and the high voltage value, and further convert the input voltage signal into the output voltage signal transmitted to the output contact point, and lower the output voltage signal voltage level. The voltage value or high voltage value is different from the input voltage signal.

  In a preferred embodiment, since the first transistor is provided as a PMOS transistor and the second transistor is provided as an NMOS transistor, the high voltage value of the input voltage signal can be reduced by the bias voltage.

  In another preferred embodiment, since the first transistor is provided as an NMOS transistor and the second transistor is provided as a PMOS transistor, the low voltage value of the input voltage signal can be improved by the bias voltage.

  In the two embodiments, the high potential voltage is provided as working voltage (VDD) or boosted charge (VGH), and the low potential voltage is provided as reverse charge (VGL), and the reverse charge (VGL) The voltage value of V is in the range of -15 to -5 v, and the voltage value of the boost charge charge (VGH) is in the range of 10 to 50 v. The bias control circuit generates a bias according to one of the overlap according to the diode overlap method and the band gap reference voltage circuit or the diode overlap resistance.

  The feature of the present invention consists only of a bias control circuit, two first transistors and two second transistors, and further reduces the critical voltage value of the first transistor by the bias control circuit and further reduces the low voltage value of the input voltage signal or Allow adjustment of high voltage value. Thus, the present invention is specially designed because it uses the four transistors and one bias control circuit to lower the critical voltage value of the transistors by the bias control circuit and further adjust the high and low voltage values of the output input voltage signal. The cost of the material can be reduced by not using the transistor.

FIG. 1 is a schematic diagram of a conventional adjustable threshold voltage value shifter for integrated circuits. FIG. 1 is a schematic view of a first embodiment of the adjustable threshold voltage level shifter for integrated circuits of the present invention. FIG. 2 is a schematic view of a concrete application according to a first preferred embodiment of the adjustable threshold voltage value level shifter for integrated circuits of the present invention; FIG. 5 is a schematic view according to a second preferred embodiment of the adjustable threshold voltage value level shifter for integrated circuits of the present invention; FIG. 5 is a schematic view of a concrete application according to a second preferred embodiment of the adjustable threshold voltage value level shifter for integrated circuits of the present invention; FIG. 5 is a schematic view according to a third preferred embodiment of the adjustable threshold voltage value level shifter for integrated circuits of the present invention;

  DETAILED DESCRIPTION In order to make the structure, uses and features of the present invention more clearly and in detail recognized and understood, preferred embodiments will be described, which will be described in detail in conjunction with the drawings as follows.

  See FIG. In the first preferred embodiment, the adjustable voltage level shifter 2 of the critical voltage value for the integrated circuit of the present invention is attached to the integrated circuit and comprises two first transistors 20, two second transistors 21 and a bias control circuit It consists of 22. Each of the two first transistors 20 and the four second transistors 21 has a source, a drain, a base, and a gate. Further, each of the two first transistors 20 has a critical voltage value indicating a voltage level. Each of the two first transistors 20 is provided as a PMOS transistor, and each of the two second transistors 21 is provided as an NMOS transistor.

  As shown in FIG. 2, each of the first transistors 20 is electrically connected to the working voltage (VDD) as its high potential input voltage, and each of its bases is electrically connected to the bias control circuit 22. Connected to The drain of the one second transistor 21 and the gate of the other second transistor 21 are simultaneously and electrically connected to the drain of the same first transistor 20 to form an output contact 23. Each of the second transistors 21 is electrically connected to a reverse charge (VGL) as a low potential input voltage at any of its sources. The voltage value of the reverse charge (VGL) is smaller than the voltage value of the working voltage (VDD). The bases of the second transistors 21 are electrically connected to the sources. In this embodiment, the voltage value of the reverse charge (VGL) is in the range of -15 to -5 v so as to constitute the low potential input voltage.

  See FIG. In particular application, the adjustable voltage level shifter 2 of the critical voltage value for integrated circuits is used to reduce the critical value of the input voltage signal. Output contact 23 is electrically connected to boosted voltage level shifter 3. The boosted voltage level shifter 3 is used to improve the voltage value of the input voltage signal. As shown, the gates of the two first transistors 20 receive an input voltage signal. The input voltage signal has a voltage level between a low voltage value and a high voltage value, and as shown in the drawing, the low voltage value is provided higher than the GND of the low potential input voltage, and the high voltage A value is provided equal to VDD of the high potential input voltage. The bias control circuit 22 generates a bias voltage (VP1) and transmits it to the bases of the first transistors 20. In this embodiment, the bias voltage (VP1) lowers the critical voltage value of the first transistor 20 and further lowers the high voltage value VDD of the input voltage signal. The low voltage value GND of the input voltage signal is lowered by the combination between four of the two first transistors 20 and the two second transistors 21. Thus, the critical voltage value of the bias voltage (VP1) for the first transistor 20 lowers the input voltage signal, and the combination between the two first transistors 20 and the two second transistors 21 causes the input voltage signal to be reduced. The output voltage signal is formed by reducing the high voltage value of the input voltage signal and the low voltage value of the input voltage signal, and further converting the voltage level of the input voltage signal from GND to VDD to VGL to VDD. The voltage signal is transmitted to the output contact 23. GND is a voltage reference point (for example, ground), and the voltage value of the bias voltage (VP1) is smaller than the work voltage (VDD). In this embodiment, the bias control circuit generates a bias by one of the following: diode overlap method, bandgap reference voltage circuit or diode overlap resistance.

Also, the bias voltage (VP1) reduces the critical voltage value of the first transistor 20 by the base effect. The base effect (body effect) may be shown as follows.

  Thereafter, when the output voltage signal is transmitted to the boosted voltage level shifter 3 through the output contact point 23, the boosted voltage level shifter 3 improves the high voltage value VDD of the input voltage signal to increase the output voltage signal. The voltage value VDD is changed to VGH, and the voltage level of the output voltage signal is further converted from VGL to VDD to VGL to VGH.

  See FIG. In the second preferred embodiment, the first transistor 20 and the second transistor 21 are different from the first preferred embodiment. The bias control circuit 22 is the same as in the first preferred embodiment, and will not be described repeatedly in this embodiment.

  In this embodiment, both of the two first transistors 20 are provided as NMOS transistors, and both of the two second transistors 21 are provided as PMOS transistors. As shown in FIG. 4, any one of the sources of each of the first transistors 20 is electrically connected to reverse charge (VGL) as a low potential input voltage, and each of the sources of each of the second transistors 21 is at a high potential. It is electrically connected to a boost charge charge (VGH) as an input voltage.

  See FIG. When applied specifically, the adjustable voltage level shifter 2 of the critical voltage value for the integrated circuit is used to improve the voltage value of the input voltage signal, and is used according to the reduced voltage level shifter 4. The reduced voltage level shifter 4 is used to reduce the voltage value of the input voltage signal. As shown in FIG. 5, the reduced voltage level shifter 4 receives an input voltage signal. The voltage level of the input voltage signal is between the low voltage value and the high voltage value so that it is the same as in the first preferred embodiment. As shown in FIG. 5, when the low voltage value of the input voltage signal is provided higher than the GND of the low potential input voltage, and the high voltage value of the input voltage signal is provided the same as the VDD of the high potential input voltage. The reduced voltage level shifter 4 converts an input voltage signal at a voltage level of GND to VDD into an input voltage signal at a voltage level of VGL to VDD.

  Thereafter, the reduced voltage level shifter 4 transmits the input voltage signal of the voltage level of VGL to VDD to the gate of each of the first transistors 20 of the adjustable voltage level shifter 2 of the critical voltage value for the integrated circuit. The bias control circuit 22 generates a bias voltage (VP2) and transmits it to the bases of the first transistors 20. In this embodiment, the bias voltage (VP2) reduces the critical voltage value of the first transistor 20 to further improve the low voltage value of the input voltage signal. The high voltage value VDD of the input voltage signal is improved by the combination form between the two first transistors 20 and the two second transistors 21 so that the voltage levels of the input voltage signals from VGL to VDD to VGL to VGH. To form an output voltage signal transmitted to the output contact 23 so that the high and low voltage values of the output voltage signal are different from the high and low voltage values of the input voltage signal. Thereby, the adjustable voltage level shifter 2 of the critical voltage value for the integrated circuit of the present invention can adjust the critical value of the input voltage signal according to the bias control circuit 22 with only four transistors. In this embodiment, the voltage value of the reverse charge (VGL) is in the range of -15 to -5v to form a low voltage, and the boosted charge (VGH) voltage value is in the range of 10 to 50v to form a high voltage. is there. The voltage value of the bias voltage (VP2) is larger than the voltage value of the reverse charge (VGL).

  See FIG. In the third preferred embodiment, the adjustable threshold voltage level shifter 2 for integrated circuits is connected to the adjustable threshold voltage level shifter 2 for integrated circuits as in the other second preferred embodiment. And the adjustable voltage level shifter 2 of the critical voltage value for one of the integrated circuits converts the voltage level of the input voltage signal from GND to VDD to VGL to VDD and transmits the input voltage signal to the output contact 23 And the adjustable voltage level shifter 2 of the critical voltage value for the other integrated circuit converts the voltage level of the output voltage signal from VGL to VDD to VGL to VGH. It differs from the one preferred embodiment.

  The examples given above are for the purpose of illustration only and not for the purpose of limitation. Without departing from the scope of the spirit of the present invention, those skilled in the art can use any of the various practical modifications and modifications described below based on the claims of the present invention and the description of the present invention. It should be included in the scope of the new registration request.

DESCRIPTION OF REFERENCE NUMERALS 1 conventional voltage level shifter 10 first voltage level shift unit 101 first PMOS transistor 102 first NMOS transistor 11 second voltage level shift unit 111 second PMOS transistor 112 second NMOS transistor 12 first contact point 13 second contact point 2 critical voltage for integrated circuit Value adjustable voltage level shifter 20 first transistor 21 second transistor 22 bias control circuit 23 output contact 3 boosted voltage level shifter 4 reduced voltage level shifter

  As shown in the drawing, when each of the first PMOS transistors 101 is electrically connected to the working voltage (VDD) at its source and electrically connected to the base, the drains thereof are respectively connected to one of the first NMOS transistors. The first contact 12 and the second contact 13 are formed simultaneously and electrically connected to the drain of the second transistor 102 and the gate of the other first NMOS transistor 102. Also, each of the first NMOS transistors 102 is electrically connected to the base and any of its sources, and is electrically connected to the reverse charge pump (VGL).

  Note that each of the second POMS transistors is electrically connected to the base and any of its sources, and is electrically connected to the boost charge pump (VGH). Each of the second NMOS transistors 112 has its source electrically connected to the base and is electrically connected to the reverse charge pump (VGL), and its drain is the drain of its one second PMOS transistor 111 and the other second PMOS The gate of the transistor 111 is simultaneously electrically connected, and the gate of one of the second NMOS transistors 112 is electrically connected to the first contact 12 and the gate of the other second NMOS transistor 112 is electrically connected to the second contact 13. Connected.

  Thereafter, when an input voltage signal at a voltage level of VGL to VDD is transmitted to the two second NMOS transistors 112 of the second voltage level shift unit 11 through the first contact 12 and the second contact 13, the second voltage level shift is performed. The unit 11 boosts the voltage level of the input voltage signal to change the high voltage value of the voltage level from VDD to VGH, and further converts the voltage level from VGL to VDD to VGL to VGH. GND is a voltage reference point, VDD is a working voltage, VGL is a reverse charge pump, and VGH is a boost charge pump.

  In the two embodiments, the high potential voltage is provided as a working voltage (VDD) or a boosted charge pump (VGH), and the low potential voltage is provided as a reverse charge pump (VGL), the reverse charge pump (VGL) The voltage value of V is between -15 and -5v, and the boosted charge pump (VGH) voltage value is between 10 and 50v. The bias control circuit generates the bias by one of the diode superposition, the band gap reference voltage circuit, and the diode and resistor superposition.

  As shown in FIG. 2, each of the first transistors 20 is electrically connected to the working voltage (VDD) as its high potential input voltage, and each of its bases is electrically connected to the bias control circuit 22. Connected to The drain of the one second transistor 21 and the gate of the other second transistor 21 are simultaneously and electrically connected to the drain of the same first transistor 20 to form an output contact 23. Each of the second transistors 21 is electrically connected to a reverse charge pump (VGL) as a low potential input voltage at any of its sources. The voltage value of the reverse charge pump (VGL) is smaller than the voltage value of the working voltage (VDD). The bases of the second transistors 21 are electrically connected to the sources. In this embodiment, the voltage value of the reverse charge pump (VGL) is in the range of -15 to -5 v so as to constitute the low potential input voltage.

  See FIG. In particular application, the adjustable voltage level shifter 2 of the critical voltage value for integrated circuits is used to reduce the critical value of the input voltage signal. Output contact 23 is electrically connected to boosted voltage level shifter 3. The boosted voltage level shifter 3 is used to improve the voltage value of the input voltage signal. As shown, the gates of the two first transistors 20 receive an input voltage signal. The input voltage signal has a voltage level between a low voltage value and a high voltage value, and as shown in the drawing, the low voltage value is provided higher than the GND of the low potential input voltage, and the high voltage A value is provided equal to VDD of the high potential input voltage. The bias control circuit 22 generates a bias voltage (VP1) and transmits it to the bases of the first transistors 20. In this embodiment, the bias voltage (VP1) lowers the critical voltage value of the first transistor 20 and further lowers the high voltage value VDD of the input voltage signal. The low voltage value GND of the input voltage signal is lowered by the combination between four of the two first transistors 20 and the two second transistors 21. Thus, the critical voltage value of the bias voltage (VP1) for the first transistor 20 lowers the input voltage signal, and the combination between the two first transistors 20 and the two second transistors 21 causes the input voltage signal to be reduced. The output voltage signal is formed by reducing the high voltage value of the input voltage signal and the low voltage value of the input voltage signal, and further converting the voltage level of the input voltage signal from GND to VDD to VGL to VDD. The voltage signal is transmitted to the output contact 23. GND is a voltage reference point (for example, ground), and the voltage value of the bias voltage (VP1) is smaller than the work voltage (VDD). In this embodiment, the bias control circuit generates the bias by one of the following methods: diode superposition, band gap reference voltage circuit, or diode and resistor superposition.

  In this embodiment, both of the two first transistors 20 are provided as NMOS transistors, and both of the two second transistors 21 are provided as PMOS transistors. As shown in FIG. 4, any one of the sources of each of the first transistors 20 is electrically connected to a reverse charge pump (VGL) as a low potential input voltage, and each of the sources of each of the second transistors 21 is at a high potential. It is electrically connected to a boost charge pump (VGH) as an input voltage.

  Thereafter, the reduced voltage level shifter 4 transmits the input voltage signal of the voltage level of VGL to VDD to the gate of each of the first transistors 20 of the adjustable voltage level shifter 2 of the critical voltage value for the integrated circuit. The bias control circuit 22 generates a bias voltage (VP2) and transmits it to the bases of the first transistors 20. In this embodiment, the bias voltage (VP2) reduces the critical voltage value of the first transistor 20 to further improve the low voltage value of the input voltage signal. The high voltage value VDD of the input voltage signal is improved by the combination form between the two first transistors 20 and the two second transistors 21 so that the voltage levels of the input voltage signals from VGL to VDD to VGL to VGH. To form an output voltage signal transmitted to the output contact 23 so that the high and low voltage values of the output voltage signal are different from the high and low voltage values of the input voltage signal. Thereby, the adjustable voltage level shifter 2 of the critical voltage value for the integrated circuit of the present invention can adjust the critical value of the input voltage signal according to the bias control circuit 22 with only four transistors. In this embodiment, the voltage value of the reverse charge pump (VGL) is in the range of -15 to -5 v to form a low voltage, and the boost charge pump (VGH) voltage value is in the range of 10 to 50 v to form a high voltage. is there. The voltage value of the bias voltage (VP2) is larger than the voltage value of the reverse charge pump (VGL).

Claims (6)

Two first transistors, two second transistors, and a bias control circuit, wherein the two first transistors have a critical voltage value indicating a voltage level, and the gates of the two first transistors receive an input voltage signal The voltage level of the input voltage signal is between a low voltage value and a high voltage value, and the drain of the first transistor is the gate of one of the second transistors and the other of the second transistors. Simultaneously electrically connected to the drain of the
The sources and bases of the two second transistors are simultaneously electrically connected to one of the low potential input voltage and the high potential input voltage, and the sources of the two first transistors are the low potential input voltage and the high potential input voltage. Electrically connected to the other, the bias control circuit is electrically connected simultaneously to the bases of the two first transistors, provides a bias voltage to the two first transistors, and the critical voltage of the first transistor The low voltage value is adjusted to adjust one of the low voltage value and the high voltage value, and the input voltage signal is converted to the output voltage signal transmitted to the output contact, and the low voltage value of the output voltage signal voltage level is The adjustment of the critical voltage value for integrated circuits which is different from the low voltage value of the input voltage signal or whose high voltage value of the output voltage signal voltage level is different from the high voltage value of the input voltage signal Possible voltage level shifter.   The critical voltage value for an integrated circuit according to claim 1, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor, so that a high voltage value of the input voltage signal is lowered by the bias voltage. Adjustable voltage level shifter.   The critical voltage value for an integrated circuit according to claim 1, wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor, so that the low voltage value of the input voltage signal is improved by the bias voltage. Adjustable voltage level shifter.   The threshold voltage adjustable voltage level shifter for integrated circuits according to claim 1, wherein the high potential input voltage is provided as a working voltage or boosted charge, and the low potential input voltage is provided as a reverse charge.   5. The adjustable threshold voltage level shifter of claim 4, wherein the voltage value of the reverse charge is between -15 and -5 volts and the boosted charge voltage value is between 10 and 50 volts.   The adjustable voltage of critical voltage value for an integrated circuit according to claim 1, wherein said bias control circuit generates a bias according to one form of overlap according to a diode overlap method, a band gap reference voltage circuit or a diode overlap resistor. Level shifter.