TW202203185A - Display panel - Google Patents

Abstract

A display panel is disclosed. The display panel includes a first substrate and a second substrate, and includes a multiplexer circuit area and other circuit areas. The multiplexer circuit area is formed on the first substrate and includes a plurality of transistors, which are electrically coupled to the plurality of data lines of the display panel respectively, and the plurality of transistors include a first threshold voltage. The other circuit area is formed on the first substrate. The other circuit area includes plurality of transistors, which include a second threshold voltage and the second threshold voltage is different from the first threshold voltage.

Description

display panel

The present invention relates to a display panel, in particular to a display panel with insufficient pixel charging rate improved by adjusting the threshold voltage of the multiplexer circuit region.

When fabricating the multiplexer circuit, a complementary metal-oxide-semiconductor (CMOS) process can be used to fabricate the corresponding transistor, which has good switching resistance and charging performance. However, the CMOS process includes complementary metal oxide semiconductor and N-type metal oxide semiconductor (N-Type Metal-Oxide-Semiconductor, NMOS) process and P-Type Metal-Oxide-Semiconductor (PMOS) process In the actual manufacturing process, more photomasks need to be used, and the manufacturing steps are more complicated and the cost is higher.

If we consider using NMOS process or PMOS process alone to fabricate transistors in the multiplexer circuit area, although the process can be simplified, the electrical performance of components may not be as good as the multiplexer circuit fabricated by CMOS process. For example, a multiplexer circuit fabricated only by an NMOS process has a poor pixel charging rate, especially when used in a high frame rate (HFR) environment, where the pixel charging rate is seriously insufficient.

In view of the foregoing, the inventors of the present invention have considered and designed a display panel, in order to improve the deficiencies of the prior art, thereby enhancing the implementation and utilization in the industry.

In view of the above-mentioned conventional problems, an object of the present invention is to provide a display panel for solving the problem of insufficient charging rate when the NMOS process or the PMOS process is used alone.

Based on the above objective, the present invention provides a display panel including a first substrate and a second substrate, and including a multiplexer circuit area and other circuit areas. The multiplexer circuit area is formed on the first substrate, and includes a plurality of transistors, which are respectively electrically coupled to a plurality of data lines of the display panel, and the plurality of transistors include a first threshold voltage. The other circuit regions are formed on the first substrate, and the other circuit regions include a plurality of transistors, and the plurality of transistors have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage.

In the embodiment of the present invention, the difference between the first threshold voltage and the second threshold voltage may be more than 0.5V.

In an embodiment of the present invention, the plurality of transistors in the multiplexer circuit region may include N-type transistors, the second threshold voltage is a positive voltage and the first threshold voltage is a negative voltage.

In an embodiment of the present invention, the plurality of transistors in the multiplexer circuit region may include P-type transistors, the second threshold voltage is a negative voltage and the first threshold voltage is a positive voltage.

In the embodiment of the present invention, other circuit regions may include a plurality of pixel regions, and the plurality of pixel regions respectively include a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel and a sixth pixel, each of which is a plurality of pixels. The pixel regions are respectively coupled to the plurality of transistors in the multiplexer circuit region. When the plurality of transistors are turned on, the plurality of data lines transmit data signals to the plurality of pixel regions.

In an embodiment of the present invention, the multiplexer circuit region may include a plurality of first transistors, a plurality of second transistors, a plurality of third transistors, a plurality of fourth transistors, a plurality of fifth transistors, and a plurality of sixth transistors. The plurality of first transistors respectively include a first terminal, a second terminal and a control terminal, the first terminal is connected to the first pixel, the second terminal is connected to the positive voltage source, and the control terminal is connected to the first control signal line. The plurality of second transistors respectively include a first end, a second end and a control end, the first end is connected to the fifth pixel, the second end is connected to the positive voltage source, and the control end is connected to the second control signal line. The plurality of third transistors respectively include a first end, a second end and a control end, the first end is connected to the third pixel, the second end is connected to the positive voltage source, and the control end is connected to the third control signal line. The plurality of fourth transistors respectively include a first end, a second end and a control end, the first end is connected to the fourth pixel, the second end is connected to the negative voltage source, and the control end is connected to the first control signal line. The plurality of fifth transistors respectively include a first end, a second end and a control end, the first end is connected to the second pixel, the second end is connected to the negative voltage source, and the control end is connected to the second control signal line. The plurality of sixth transistors respectively include a first end, a second end and a control end, the first end is connected to the sixth pixel, the second end is connected to the negative voltage source, and the control end is connected to the third control signal line.

In an embodiment of the present invention, the multiplexer circuit region may include a plurality of first transistors, a plurality of second transistors, a plurality of third transistors, a plurality of fourth transistors, a plurality of fifth transistors, and a plurality of sixth transistors. The plurality of first transistors respectively include a first terminal, a second terminal and a control terminal, the first terminal is connected to the first pixel, the second terminal is connected to the positive voltage source, and the control terminal is connected to the first control signal line. The plurality of second transistors respectively comprise a first terminal, a second terminal and a control terminal, the first terminal is connected to the second pixel, the second terminal is connected to the negative voltage source, and the control terminal is connected to the second control signal line. The plurality of third transistors respectively include a first end, a second end and a control end, the first end is connected to the third pixel, the second end is connected to the positive voltage source, and the control end is connected to the third control signal line. The plurality of fourth transistors respectively include a first end, a second end and a control end, the first end is connected to the fourth pixel, the second end is connected to the negative voltage source, and the control end is connected to the first control signal line. The plurality of fifth transistors respectively include a first end, a second end and a control end, the first end is connected to the fifth pixel, the second end is connected to the positive voltage source, and the control end is connected to the second control signal line. The plurality of sixth transistors respectively include a first end, a second end and a control end, the first end is connected to the sixth pixel, the second end is connected to the negative voltage source, and the control end is connected to the third control signal line.

In the embodiment of the present invention, the first pixel and the fourth pixel may be red pixels, the second pixel and the fifth pixel may be green pixels, and the third pixel and the sixth pixel may be blue pixels.

In an embodiment of the present invention, the plurality of transistors coupled to the red pixels include a red threshold voltage, the plurality of transistors coupled to the green pixels include a green threshold voltage, and the plurality of transistors coupled to the blue pixels include The blue threshold voltage, the blue threshold voltage may be greater than the green threshold voltage or the red threshold voltage.

In an embodiment of the present invention, other circuit regions may include a driving chip, which is coupled to a plurality of transistors and provides operating voltages to the plurality of transistors.

As mentioned above, in the display panel of the present invention, by adjusting the first threshold voltage of the multiplexer circuit region, the pixel charging rate can be significantly improved under the condition of high frame rate.

In order to facilitate the understanding of the technical features, content and advantages of the present invention and the effects that can be achieved, the present invention is hereby described in detail with the accompanying drawings, and in the form of embodiments as follows, and the drawings used therein are only for the purpose of For the purpose of illustrating and assisting the description, it is not necessarily the real proportion and precise configuration after the implementation of the present invention. Therefore, the proportion and configuration relationship of the attached drawings should not be interpreted or limited to the scope of rights of the present invention in actual implementation. Say Ming.

In the drawings, the thickness or width of substrates, panels, regions, lines, etc., are exaggerated for clarity. The same reference numerals refer to the same elements throughout the specification. It will be understood that when an element such as a substrate, panel, region or line is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements. Furthermore, it will be understood that, although the terms “first,” “second,” and “third” may be used herein to describe various elements, components, regions, layers and/or sections, they are , region, layer and/or section is distinguished from another element, component, region, layer and/or section. Therefore, it is for descriptive purposes only and should not be construed to indicate or imply relative importance or their sequential relationship.

Unless otherwise defined, all terms used herein have the meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning unless expressly so defined herein.

Please refer to FIG. 1 , which is a schematic diagram of the display panel of the present invention. As shown in the figure, the display panel DP of the present invention includes an upper substrate and a lower substrate, wherein the first substrate S1 can be a lower substrate or an upper substrate, which is determined according to the type of the display panel DP. The first substrate S1 includes different setting areas, which are respectively used to configure corresponding structures and circuits. The setting methods of the different areas are further described in the following paragraphs.

The multiplexer circuit area MUX is disposed on the first substrate S1. The multiplexer circuit region MUX includes a plurality of transistors, and the transistors are coupled to a plurality of data lines of the display panel DP. Through the switching of these transistors, the driving signal of the driving circuit is transmitted to each data line to control each pixel unit coupled to the data line. When these transistors are fabricated on the substrate, according to the difference of each layer of thin films fabricated on the substrate according to the semiconductor manufacturing process, the plurality of transistors on the first substrate S1 have a first threshold voltage.

In addition, other circuit regions NMUX are provided on the first substrate S1. The other circuit areas NMUX are all other areas that do not belong to the multiplexer circuit area MUX. In this embodiment, the other circuit areas NMUX include a display area DA, a non-display area NDA, and a chip on film area COF, etc. . The display area DA includes a plurality of pixels, which form a pixel matrix to display a picture. The non-display area NDA is a circuit area on the periphery of the display area DA, and is used for setting driving circuits such as sensing signals or scanning signals. As shown in the figure, the lower part of the display area DA includes a chip-on-film area COF, which is provided with a driving chip by means of flip-chip packaging. The driving chip provides a plurality of contacts to generate driving signals for the data lines in the pixel area. The arrangement of the MUX in the processor circuit area enables one contact to simultaneously provide the driving signals required by a plurality of data lines, thereby simplifying the circuit design and the required space. The display area DA, the non-display area NDA, and the chip-on-film area COF are disposed on the other circuit areas NMUX. Since the multiplexer circuit area MUX and the other circuit areas NMUX are in the manufacturing process, the doping of the two can be changed by the process. concentration, so the transistors in the two regions can have different threshold voltages.

Doping elements with different contents in the manufacturing process can change the doping amount in the process by designing a mask covering the MUX range of the multiplexer circuit area or the NMUX range of other circuit areas, thereby changing the placement of transistor elements in a specific area. the critical voltage. That is, by adjusting the content of elements doped in the process to change the threshold voltage of the transistors, a plurality of transistors in the multiplexer circuit region MUX on the first substrate S1 have the first threshold voltage, while the other circuit regions NMUX have the first threshold voltage. The plurality of transistors have a second threshold voltage different from the first threshold voltage. In this embodiment, the difference between the first threshold voltage and the second threshold voltage exceeds 0.5V. By adjusting the voltage value of the process electrical properties, the pixel charging rate is improved, especially the problem of insufficient charging rate at high frame rate.

Please refer to FIG. 2 , which is a current-voltage curve diagram of the multiplexer circuit region of the display panel of the present invention. By changing the doping amount of the elements mentioned above, the first threshold voltage Vth1 of the multiplexer circuit region MUX can be adjusted within a certain range. For example, when the transistors used in the multiplexer circuit area MUX are N-type transistors and are not adjusted, the threshold voltages of the transistors on the first substrate S1 are the same. For example, the multiplexer circuit area The first threshold voltage Vth1 of the transistor in the MUX and the second threshold voltage Vth2 of the transistor in the other circuit region NMUX are both +1.2975V. In this embodiment, the doping amount of the multiplexer circuit region MUX is changed, so that the current-voltage curve (IV curve) of the first threshold voltage Vth1 of the transistors in the multiplexer circuit region MUX is shifted toward the negative voltage. ), for example, from +1.2975 to -1V, -2V or -5V, etc., the adjustment range can be more than 0.5V to increase the charging current to improve the pixel charging rate.

In another embodiment, for example, when the transistors in the multiplexer circuit region MUX are P-type transistors and are not adjusted, the first threshold voltage Vth1 and the second threshold voltage Vth2 may both be -1.2975V. After changing the threshold voltage of the transistor in the multiplexer circuit region MUX, the current-voltage curve (IV curve) of the first threshold voltage Vth1 is shifted toward the positive voltage, for example, adjusted from -1.2975V to +1V, + 2V or +3V, etc., the adjustment range can also be above 0.5V to improve the pixel charging rate.

By adjusting the threshold voltage of the transistors in the multiplexer circuit area MUX, the transistors in the multiplexer circuit area MUX can have a larger charging current, and the charging rate of the pixels can be improved. The transistor circuit only needs to use the N-type transistor process or the P-type transistor process, which can reduce the process steps and costs, reduce the complexity of the process and improve the production efficiency.

Please refer to FIG. 3 , which is a configuration diagram of a circuit area of a multiplexer according to an embodiment of the present invention. As shown in the figure, the multiplexer circuit area MUX1 is a 1-to-3 circuit arrangement, which receives the data signal provided by the driving chip in the chip-on-film area COF1 and transmits it to each pixel in the display area DA1.

In this embodiment, the display area DA1 includes a pixel array formed by a plurality of pixels, which are the first pixel P11 , the second pixel P12 , the third pixel P13 , the fourth pixel P14 , the fifth pixel P15 and the sixth pixel respectively. P16, respectively coupled to the first data line DL11, the second data line DL12, the third data line DL13, the fourth data line DL14, the fifth data line DL15 and the sixth data line DL16 for providing data signals. In this embodiment, the first pixel P11 and the fourth pixel P14 are red pixels, the second pixel P12 and the fifth pixel P15 are green pixels, and the third pixel P13 and the sixth pixel P16 are blue pixels. However, the present disclosure is not limited thereto, the first pixel P11 and the fourth pixel P14 may also be blue pixels, the second pixel P12 and the fifth pixel P15 may also be green pixels, and the third pixel P13 and the sixth pixel P16 may also be It can be a red pixel, and the configuration of each pixel can be adjusted according to the needs of the display panel.

The chip-on-film region COF1 includes a positive voltage source contact N11 and a negative voltage source contact N12. The positive voltage source N11 is coupled to the first data line DL11, the third data line DL13 and the fifth data line DL15 through a multiplexer circuit , the data signals of the first pixel P11, the third pixel P13 and the fifth pixel P15 are provided, and the negative voltage source contact N12 is coupled to the second data line DL12, the fourth data line DL14 and the sixth data line through the multiplexer circuit The DL16 provides data signals of the second pixel P12, the fourth pixel P14 and the sixth pixel P16. The signals required by the data lines in the three pixel regions can be provided by one contact, and there is no need to set signal contacts for each data line, thereby effectively reducing the circuit setting area required for the chip-on-film region COF1. In addition, by interleaving the positive and negative voltage signals, the display effect of each pixel in the display area DA1 can be made more uniform.

In order to enable the positive voltage source contact N11 and the negative voltage source contact N12 to provide data signals to the first pixel P11 to the sixth pixel P16, a first transistor T11 and a second transistor T12 are arranged in the multiplexer circuit region MUX1 , the third transistor T13, the fourth transistor T14, the fifth transistor T15 and the sixth transistor T16, and the first control signal line MUX11, the second control signal line MUX12 and the third control signal line for controlling the above transistors MUX13. The transistors are turned on or off through these control signal lines, and the data signals are sent to the corresponding data lines. In this embodiment, the N-type transistor process is used as an example to manufacture the first transistor T11 to the sixth transistor T16, but the present disclosure is not limited to this. In other embodiments, P-type transistors may also be used. process to fabricate the above-mentioned transistors. Due to the P-type transistor process, the original threshold voltage of the transistor on the display panel (the aforementioned second threshold voltage Vth2) is a negative voltage, and after adjusting the multiplexer circuit region MUX1, the The threshold voltages of the first transistor T11 to the sixth transistor T16 formed therein (the aforementioned first threshold voltage Vth1 ) can be adjusted to a positive voltage. Similar to the previous embodiment, since the electrical properties of the elements in the multiplexer circuit region MUX1 have been adjusted, when the first transistor T11 to the sixth transistor T16 are operating, a higher charging current can be used to avoid insufficient charging. situation arises. In addition, due to the use of high frame rate, the operation time of each line is short, even if some leakage current occurs, it will not affect the display effect.

The circuit configuration of the multiplexer circuit area MUX1 is further described. The first transistor T11 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the first pixel P11 through the first data line DL11, and the second terminal is connected to a positive voltage. The source contact N11, the control terminal is connected to the first control signal line MUX11. The second transistor T12 includes a first terminal, a second terminal and a control terminal, the first terminal is connected to the fifth pixel P15 through the fifth data line DL15, the second terminal is connected to the positive voltage source contact N11, and the control terminal is connected to the second control signal Line MUX12. The third transistor T13 includes a first terminal, a second terminal and a control terminal, the first terminal is connected to the third pixel P13 through the third data line DL13, the second terminal is connected to the positive voltage source contact N11, and the control terminal is connected to the third control signal Line MUX13. The fourth transistor T14 includes a first end, a second end and a control end, the first end is connected to the fourth pixel P14 through the fourth data line DL14, the second end is connected to the negative voltage source contact N12, and the control end is connected to the first control signal Line MUX11. The fifth transistor T15 includes a first end, a second end and a control end, the first end is connected to the second pixel P12 through the second data line DL12, the second end is connected to the negative voltage source contact N12, and the control end is connected to the second control signal Line MUX12. The sixth transistor T16 includes a first end, a second end and a control end, the first end is connected to the sixth pixel P16 through the sixth data line DL16, the second end is connected to the negative voltage source contact N12, and the control end is connected to the third control signal Line MUX13.

It should be noted that, in order to enable the pixels to be arranged in a staggered manner of positive voltage and negative voltage, therefore, the second data line DL12 and the fifth data line DL15 cross between the multiplexer circuit area MUX1 and the display area DA1, so that the The two data lines DL12 are connected to the fifth transistor T15, and the fifth data line DL15 is connected to the second transistor T12. This connection method makes the voltage difference between two adjacent pixels larger, and the Drain to Source Voltage (Vds) used by each pixel itself is smaller, that is to say, here The relative leakage current under the architecture is small. Under the condition that the leakage current does not exceed the allowable level, the threshold voltage of the transistor in the multiplexer circuit region MUX1 can be further shifted to a negative voltage by adjusting the amount of doping elements, so as to improve the pixel charging rate. In addition, allowing the same voltage source contact to be solely responsible for the transmission of the positive voltage or the negative voltage can also reduce the power consumption of the contact due to the voltage difference and improve the performance of the device.

Please refer to FIG. 4 , which is a configuration diagram of a multiplexer circuit area according to another embodiment of the present invention. In this embodiment, the technical features of the same elements as those in the previous embodiments will not be repeated. As shown in the figure, the multiplexer circuit area MUX2 is a 1-to-3 circuit arrangement, which receives the data signal provided by the chip-on-film area COF2 and transmits it to each pixel in the display area DA2.

The display area DA2 includes a first pixel P21, a second pixel P22, a third pixel P23, a fourth pixel P24, a fifth pixel P25 and a sixth pixel P26, which are respectively coupled to the first data line DL21, the second pixel P21 and the second pixel P26 for providing data signals. Data line DL22, third data line DL23, fourth data line DL24, fifth data line DL25, and sixth data line DL26. In this embodiment, the first pixel P21 and the fourth pixel P24 are red pixels, the second pixel P22 and the fifth pixel P25 are green pixels, and the third pixel P23 and the sixth pixel P26 are blue pixels.

The chip-on-film region COF2 has a positive voltage source contact N21 and a negative voltage source contact N22. The positive voltage source N21 is coupled to the first data line DL21, the third data line DL23 and the fifth data line DL25 through a multiplexer circuit. The data signals of the first pixel P21, the third pixel P23 and the fifth pixel P25 are provided, and the negative voltage source contact N22 is coupled to the second data line DL22, the fourth data line DL24 and the sixth data line DL26 through a multiplexer circuit , providing data signals of the second pixel P22, the fourth pixel P24 and the sixth pixel P26.

The multiplexer circuit area MUX2 includes a first transistor T21, a second transistor T22, a third transistor T23, a fourth transistor T24, a fifth transistor T25, and a sixth transistor T26, and controls the above transistors. The first control signal line MUX21, the second control signal line MUX22 and the third control signal line MUX23.

The circuit configuration of the multiplexer circuit region MUX2 is further described. The first transistor T21 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the first pixel P21 through the first data line DL21, and the second terminal is connected to a positive voltage. The source contact N21, the control terminal is connected to the first control signal line MUX21. The second transistor T22 includes a first terminal, a second terminal and a control terminal. The first terminal is connected to the second pixel P22 through the second data line DL22, the second terminal is connected to the negative voltage source contact N22, and the control terminal is connected to the second control signal Line MUX22. The third transistor T23 includes a first end, a second end and a control end, the first end is connected to the third pixel P23 through the third data line DL23, the second end is connected to the positive voltage source contact N21, and the control end is connected to the third control signal Line MUX23. The fourth transistor T24 includes a first end, a second end and a control end, the first end is connected to the fourth pixel P24 through the fourth data line DL24, the second end is connected to the negative voltage source contact N22, and the control end is connected to the first control signal Line MUX21. The fifth transistor T25 includes a first end, a second end and a control end, the first end is connected to the fifth pixel P25 through the fifth data line DL25, the second end is connected to the positive voltage source contact N21, and the control end is connected to the second control signal Line MUX22. The sixth transistor T26 includes a first end, a second end and a control end, the first end is connected to the sixth pixel P26 through the sixth data line DL26, the second end is connected to the negative voltage source contact N22, and the control end is connected to the third control signal Line MUX23.

Similar to the previous embodiment, the pixels are also arranged in a staggered manner of positive voltage and negative voltage. However, the difference from the above-mentioned embodiment is that the data lines between the display area DA2 and the multiplexer circuit area MUX2 are not arranged to cross, instead, the lines are crossed in the chip-on-film area COF2, that is, the first line of each transistor. Between the two terminals and the contacts, the first transistor T21, the third transistor T23 and the fifth transistor T25 are connected to the positive voltage source contact N21, the second transistor T22, the fourth transistor T24 and the third The six transistors T26 are connected to the negative voltage source contact N22.

The content of the present disclosure is further described below with examples. The simulation test results of adjusting the first threshold voltage Vth1 of the display panel at a frame rate of 90 Hz are shown in Table 1 below, and the test chart is shown in FIG. 5 . Table 1: frame rate 60Hz 90Hz transistor type NMOS NMOS NMOS NMOS NMOS NMOS NMOS NMOS NMOS first threshold voltage 1.2975V 1.2975V 1.0V 0.5V 0.0V -0.5V -1.0V -1.5V -2.0V Charge Rate - Pixels [Red] 0.9771 0.8696 0.8933 0.9236 0.9445 0.9549 0.9646 0.9716 0.9759 Charge Rate - Pixels [Green] 0.9786 0.8707 0.8936 0.9235 0.9443 0.9542 0.9645 0.971 0.9758 Charge Rate - Pixels [Blue] 0.9723 0.8404 0.8597 0.885 0.9034 0.9155 0.926 0.9335 0.9398

As shown in Table 1, the original threshold voltage of the transistor of the display panel, that is, the second threshold voltage Vth2 is 1.2975 V at the frame rate of 60 Hz, and the charging rate of the pixel is about 0.97, but as the frame rate increases to 90 Hz, the color of each color The pixel charging rate dropped to 0.84~0.87, resulting in a serious problem of insufficient pixel charging rate. Therefore, by controlling the doping elements disclosed in the present invention, the threshold voltage of the transistor in the multiplexer circuit region, that is, the first threshold voltage Vth1, is adjusted, so that the first threshold voltage Vth1 is shifted toward the negative voltage. The current-voltage curve of the voltage Vth1 shifts toward the negative voltage, and the pixel charging rate gradually increases. In this example, when the first threshold voltage Vth1 is adjusted to -1.0V, the pixel charging rate has been clearly increased by 10%, and continues to increase with the shift of the first threshold voltage Vth1. Therefore, the first threshold voltage Vth1 can continue to shift toward the negative voltage without generating significant leakage current. When adjusted to -2.0V, its charging rate can reach the effect of about 0.97.

In this embodiment, the overall threshold voltage of the transistors in the multiplexer circuit area can be adjusted according to the manufacturing process, but the present disclosure is not limited to this. In another embodiment, the multiplexer circuit area can also be set according to each pixel area Different masks have different threshold voltages of transistors in different pixel regions. For example, in Table 1, the charging rate of the threshold voltage is higher for the red pixel, and the charging rate for the blue pixel is lower. Please also refer to FIG. 5 , which is an actual test chart for adjusting the threshold voltage of the display panel according to the embodiment of the present invention. As shown in the figure, when the threshold voltage is adjusted to -2.0V, in each frame, there will be red pixel, green pixel and blue pixel signal generated, and the pixel charging sequence is red pixel, green pixel and For blue pixels, the red pixels can be charged from the time point t1 to the end of the charging time (ie, the next time to emit light), while the green pixels are charged from the time point t2 to the end of the charging time, that is, the blue pixels are in the charging time. Compared with the green pixels and the red pixels, it will be insufficient (it can only be charged from the time point t3), so the blue pixels require a higher charging current than the green pixels and the red pixels. In this regard, the threshold voltage of the blue pixel region can be further adjusted to further increase the charging rate, that is, the threshold voltage of the transistor in the blue pixel region is greater than the threshold voltage of the transistor in the green pixel region or the red pixel region.

Please refer to FIG. 6 , which is a test chart for adjusting the threshold voltage of the display panel according to another embodiment of the present invention. As shown in the figure, in each frame, there will be red pixel, green pixel and blue pixel signal generated (as shown in the middle figure). The voltage of the red pixel is the first to drop, so during this time, the transistor is turned on so that the red pixel gets the charging current and starts to charge, then the voltage of the green pixel drops and starts to charge, and finally the voltage of the blue pixel drops and starts to charge. Different from the previous embodiment, when the first threshold voltage Vth1 is adjusted to -3.5V, the graph of the pixel voltage is inclined, resulting in leakage current. Compared with the previous embodiment, adjusting to -2.0V may affect the display. Therefore, the adjustment range should be determined according to the frame rate of the display panel and its specifications.

Hereinafter, another example will be used to further illustrate, when the frame rate of the display panel is changed from 60 Hz to 120 Hz, the simulation test results of adjusting the first threshold voltage Vth1 are shown in Table 2. Table 2: frame rate 60Hz 120Hz transistor type NMOS NMOS NMOS NMOS NMOS NMOS NMOS NMOS NMOS first threshold voltage 1.2975V 1.2975V 1.0V 0.5V 0.0V -0.5V -1.0V -1.5V -2.0V Charge Rate - Pixels [Red] 0.9771 0.7602 0.791 0.8348 0.8695 0.8964 0.9132 0.9254 0.9375 Charge Rate - Pixels [Green] 0.9786 0.7689 0.8 0.8437 0.8766 0.8999 0.9201 0.9353 0.9467 Charge Rate - Pixels [Blue] 0.9723 0.7433 0.7693 0.8061 0.8338 0.8544 0.8715 0.8848 0.8954

As shown in Table 2, the original threshold voltage of the transistor of the display panel, that is, the second threshold voltage Vth2 is 1.2975 V at the frame rate of 60Hz, and the charging rate of the pixel is about 0.97, but as the frame rate increases to 120Hz, the color of each color The pixel charging rate dropped to 0.74~0.76, resulting in a serious problem of insufficient pixel charging rate. When the threshold voltage of the transistor in the multiplexer circuit area is adjusted, that is, the first threshold voltage Vth1 is shifted to a negative voltage, the pixel charging rate can be improved. In this example, when the pixel charging rate is adjusted to -1.0V, the pixel charging rate A definite increase of 14% has been achieved, and when adjusted to -2.0V, the charge rate can be increased to about 0.9.

The above description is exemplary only, not limiting. Any equivalent modifications or changes that do not depart from the spirit and scope of the present invention shall be included in the appended patent application scope.

COF, COF1, COF2: chip-on-film area DA, DA1, DA2: Display area DL11, DL21: The first data line DL12, DL22: the second data line DL13, DL23: The third data line DL14, DL24: the fourth data line DL15, DL25: Fifth data line DL16, DL26: sixth data line DP: Display Panel MUX, MUX1, MUX1: Multiplexer circuit area MUX11, MUX21: The first control signal line MUX12, MUX22: The second control signal line MUX13, MUX23: The third control signal line NDA: non-display area NMUX: Other circuit area P11, P21: the first pixel P12, P22: the second pixel P13, P23: the third pixel P14, P24: the fourth pixel P15, P25: the fifth pixel P16, P26: sixth pixel S1: the first substrate T11, T21: the first transistor T12, T22: the second transistor T13, T23: the third transistor T14, T24: the fourth transistor T15, T25: the fifth transistor T16, T26: sixth transistor t1, t2, t3: time points Vth1: the first threshold voltage Vth2: the second threshold voltage

In order to make the technical features, content and advantages of the present invention and the effects that can be achieved more obvious, the present invention is hereby described in detail as follows in the form of embodiments in conjunction with the accompanying drawings: FIG. 1 is a schematic diagram of a display panel of the present invention. FIG. 2 is a current-voltage curve diagram of the multiplexer circuit region of the display panel of the present invention. FIG. 3 is a configuration diagram of a circuit area of a multiplexer according to an embodiment of the present invention. FIG. 4 is a configuration diagram of a circuit area of a multiplexer according to another embodiment of the present invention. FIG. 5 is a test chart for adjusting the threshold voltage of the display panel according to the embodiment of the present invention. FIG. 6 is a test chart for adjusting the threshold voltage of the display panel according to another embodiment of the present invention.

COF: chip on film area

DA: display area

DP: Display Panel

MUX: Multiplexer circuit area

NDA: non-display area

NMUX: Other circuit area

S1: the first substrate

Claims (10)

A display panel, comprising a first substrate and a second substrate, comprising: a multiplexer circuit region, formed on the first substrate, including a plurality of transistors, respectively electrically coupled to a plurality of data lines of the display panel, the plurality of transistors including a first threshold voltage; An other circuit region is formed on the first substrate, the other circuit region includes a plurality of transistors, the plurality of transistors have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage. The display panel of claim 1, wherein the difference between the first threshold voltage and the second threshold voltage is more than 0.5V. The display panel of claim 1, wherein the plurality of transistors in the multiplexer circuit region comprise N-type transistors, the second threshold voltage is a positive voltage and the first threshold voltage is a negative voltage. The display panel of claim 1, wherein the plurality of transistors in the multiplexer circuit region comprise P-type transistors, the second threshold voltage is a negative voltage and the first threshold voltage is a positive voltage. The display panel of claim 1, wherein the other circuit area includes a plurality of pixel areas, and the plurality of pixel areas respectively include a first pixel, a second pixel, a third pixel, a fourth pixel, a first pixel Five pixels and a sixth pixel, the plurality of pixel regions are respectively coupled to the plurality of transistors in the multiplexer circuit region, when the plurality of transistors are turned on, the plurality of data lines transmit data signals to the plurality of transistors a plurality of pixel regions. The display panel of claim 5, wherein the multiplexer circuit region comprises: A plurality of first transistors respectively include a first end, a second end and a control end, the first end is connected to the first pixel, the second end is connected to a positive voltage source, and the control end is connected to a first control signal line; A plurality of second transistors respectively include a first end, a second end and a control end, the first end is connected to the fifth pixel, the second end is connected to the positive voltage source, and the control end is connected to a second control signal line; A plurality of third transistors respectively include a first end, a second end and a control end, the first end is connected to the third pixel, the second end is connected to the positive voltage source, and the control end is connected to a third control signal line; A plurality of fourth transistors respectively include a first end, a second end and a control end, the first end is connected to the fourth pixel, the second end is connected to a negative voltage source, and the control end is connected to the first control signal line; A plurality of fifth transistors respectively include a first end, a second end and a control end, the first end is connected to the second pixel, the second end is connected to the negative voltage source, and the control end is connected to the second control signal lines; and A plurality of sixth transistors respectively include a first end, a second end and a control end, the first end is connected to the sixth pixel, the second end is connected to the negative voltage source, and the control end is connected to the third Control signal lines. The display panel of claim 5, wherein the multiplexer circuit area includes: A plurality of first transistors respectively include a first end, a second end and a control end, the first end is connected to the first pixel, the second end is connected to a positive voltage source, and the control end is connected to a first control signal line; A plurality of second transistors respectively include a first end, a second end and a control end, the first end is connected to the second pixel, the second end is connected to a negative voltage source, and the control end is connected to a second control signal line; A plurality of third transistors respectively include a first end, a second end and a control end, the first end is connected to the third pixel, the second end is connected to the positive voltage source, and the control end is connected to a third control signal line; A plurality of fourth transistors respectively include a first end, a second end and a control end, the first end is connected to the fourth pixel, the second end is connected to the negative voltage source, and the control end is connected to the first control signal line; A plurality of fifth transistors respectively include a first end, a second end and a control end, the first end is connected to the fifth pixel, the second end is connected to the positive voltage source, and the control end is connected to the second control signal lines; and A plurality of sixth transistors respectively include a first end, a second end and a control end, the first end is connected to the sixth pixel, the second end is connected to the negative voltage source, and the control end is connected to the third Control signal line. The display panel of claim 5, wherein the first pixel and the fourth pixel are red pixels, the second pixel and the fifth pixel are a green pixel, and the third pixel and the sixth pixel are a blue pixel color pixels. The display panel of claim 8, wherein the plurality of transistors coupled to the red pixel include a red threshold voltage, the plurality of transistors coupled to the green pixel include a green threshold voltage and are coupled to The plurality of transistors of the blue pixel include a blue threshold voltage, and the blue threshold voltage is greater than the green threshold voltage or the red threshold voltage. The display panel of claim 1, wherein the other circuit area includes a driving chip, which is coupled to the plurality of transistors and provides an operating voltage to the plurality of transistors.

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