CN214279558U

CN214279558U - Slew rate enhancement circuit, source driving chip and display device

Info

Publication number: CN214279558U
Application number: CN202023016481.5U
Authority: CN
Inventors: 朴相敏; 南帐镇
Original assignee: Beijing Eswin Computing Technology Co Ltd; Hefei Eswin IC Technology Co Ltd
Current assignee: Hefei Yisiwei Computing Technology Co ltd; Beijing Eswin Computing Technology Co Ltd
Priority date: 2020-12-14
Filing date: 2020-12-14
Publication date: 2021-09-24
Anticipated expiration: 2030-12-14

Abstract

The utility model provides a slew rate reinforcing circuit, source driver chip and display device belongs to and shows drive technical field. The slew rate enhancement circuit comprises a first latch, a second latch, a first level shifter, a slew rate enhancement module and an amplifier; the first latch is used for storing the received first data; the second latch is used for storing the received second data, and the second data is the latter data of the first data; the slew rate enhancement module is used for adjusting the slew rate of the output stage of the amplifier according to the value of the designated digit of the first data, the value of the designated digit of the second data and the current input data. The utility model discloses can realize output voltage's quick conversion under the condition that does not increase amplifier quiescent current, guarantee the stability of IC temperature simultaneously.

Description

Slew rate enhancement circuit, source driving chip and display device

Technical Field

The utility model relates to a show the drive field, especially relate to a slew rate reinforcing circuit, source driver chip and display device.

Background

A Source Driver IC (Source Driver IC) of the display panel drives pixels of the panel by recombining input Digital signals into Analog signals through a Digital-to-Analog Converter ("DAC"). The higher the resolution of the display screen, the more the number of pixels, so that the number of pixels to be driven in the same time is increased, resulting in a shorter time for each pixel to be driven; and the larger the picture is, the larger the capacitance of the screen is, and the time for driving the pixels is increased; this may slow down the slew rate (i.e., slew rate) of the voltage output from the source driver IC of the display panel, resulting in abnormal image quality and increased temperature of the IC.

In a DAC circuit of a general display source driver IC, a method of increasing a quiescent current of an amplifier to increase a slew rate is generally used, and if a display screen has a resolution of 8k or more, an effect of increasing only a current to increase the slew rate is limited, and increasing the current in such a manner may cause a temperature rise of the IC, which is more remarkable in a high-definition, large-sized display screen device of 8k or more.

SUMMERY OF THE UTILITY MODEL

The utility model provides a slew rate reinforcing circuit, source driver chip and display device can realize output voltage's quick conversion under the condition that does not increase amplifier quiescent current, guarantees the stability of IC temperature simultaneously.

In order to achieve the above purpose, the utility model adopts the following scheme:

on the one hand, the embodiment of the utility model provides a slew rate reinforcing circuit, include:

the circuit comprises a first latch, a second latch, a first level shifter, a slew rate enhancement module and an amplifier;

the first latch is used for storing the received first data;

the second latch is configured to store received second data, where the second data is a data subsequent to the first data;

the first level shifter is used for boosting the first data and taking a high-voltage data signal obtained by boosting as the current input data of the slew rate enhancement module;

the slew rate enhancement module is connected with the amplifier, the first level shifter, the first latch and the second latch, and is used for adjusting the voltage of the output stage of the amplifier according to the value of the specified bit of the first data, the value of the specified bit of the second data and the current input data, so as to enhance the slew rate of the output stage of the amplifier. Optionally, the slew rate enhancement module includes:

the mode detection module is connected with the first latch and the second latch and used for judging whether the slew rate of the output stage of the amplifier needs to be enhanced or not according to the value of the specified digit of the first data and the value of the specified digit of the second data and outputting a control signal PD according to a judgment result;

and the charging module is connected with the output end of the mode detection module, the output end of the first level shifter and a charging voltage end and is used for determining whether the slew rate of the output stage of the amplifier needs to be enhanced or not according to the control signal PD and the current input data, and determining the charging voltage input to the output stage of the amplifier if the slew rate of the output stage of the amplifier needs to be enhanced.

Optionally, the mode detection module includes:

an exclusive-or gate circuit, a D flip-flop and a second level shifter;

the input end of the exclusive-or gate circuit is connected with the first latch and the second latch and is used for judging whether the value of the assigned digit of the input first data is equal to the value of the assigned digit of the second data or not and outputting a judgment result;

the output end of the exclusive-or gate circuit is connected with the D end of the D trigger, the input end of the second level shifter is connected with the Q end of the D trigger, and the exclusive-or gate circuit is used for judging whether the slew rate of the output stage of the amplifier needs to be enhanced according to the judgment result of the exclusive-or gate circuit, wherein:

when the value of the specified digit of the first data is not equal to the value of the specified digit of the second data, obtaining and outputting a judgment result of the slew rate of the output stage of the amplifier needing to be enhanced;

when the value of the designated digit of the first data is equal to the value of the designated digit of the second data, obtaining and outputting a judgment result of the slew rate which does not need to enhance the output stage of the amplifier;

and the output end of the second potential level shifter is connected with the charging module and used for providing the control signal PD for the charging module.

Optionally, the value of the specified number of bits of the first data and the value of the specified number of bits of the second data include:

the value D1< x > of the x-th bit of the first data, and the value D2< x > of the x-th bit of the second data.

Optionally, the xth bit is a most significant bit of the first data and/or the second data.

Optionally, the charging module includes: the first control switch group and the second control switch group;

the first control switch group is connected to a VDD voltage end and is connected with the OUTN port of the amplifier output stage in series after being connected with the first PD control switch;

the second control switch group is connected to the VSS voltage end and is connected with the second PD control switch in series and then is connected to the OUTP port of the amplifier output stage;

the first PD control switch and the second PD control switch are used for controlling the switching on or switching off according to the value of the control signal PD;

the first control switch group is formed by connecting a plurality of switches in series and is used for controlling the on-off of each switch according to whether the current input data belongs to the enabling range of the slew rate enhancement module;

and the second control switch group is formed by connecting a plurality of switches in series, and controls the on or off of each switch according to whether the inverted data of the current input data belongs to the enabling range of the slew rate enhancement module.

Optionally, the charging module further includes two internal fast charging FIC control switches:

wherein a first FIC control switch is connected in series with the first control switch group and the first PD control switch between the VDD voltage terminal and an OUTN port of the amplifier output stage;

the second FIC control switch and the second control switch group are connected in series, and the second PD control switch is connected between the VSS voltage end and an OUTP port of the amplifier output stage;

the first FIC control switch and the second FIC control switch are controlled to be switched on or switched off according to an externally input FIC signal;

the FIC signal is set according to the use state of the slew rate enhancement circuit.

On the one hand, the embodiment of the utility model provides a source driver chip is provided, include the embodiment of the utility model provides an arbitrary item the slew rate reinforcing circuit.

On the one hand, the embodiment of the utility model provides a display device is provided, include the embodiment of the utility model provides a source driver chip.

The embodiment of the utility model provides a beneficial effect that technical scheme brought includes at least: the utility model provides a slew rate reinforcing circuit can realize adjusting the slew rate of amplifier output stage according to the current input data of first data, second data and slew rate reinforcing module, wherein, if need strengthen the slew rate of amplifier output stage, confirm to the charging voltage of amplifier output stage input, wherein the second data is the latter data of first data; by the scheme, the output voltage can be quickly converted under the condition that the quiescent current of the amplifier is not increased, and meanwhile, the stability of the temperature of the IC is ensured.

Drawings

Fig. 1 is a schematic structural diagram of a slew rate enhancement circuit provided in an embodiment of the present invention;

fig. 2 is a schematic diagram of a slew rate enhancement circuit of an 8-bit source code driver IC according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a slew rate enhancement circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a slew rate enhancement circuit according to an embodiment of the present invention;

fig. 5 is a flowchart of a slew rate enhancement method according to an embodiment of the present invention;

fig. 6 is a schematic structural view of a slew rate enhancing apparatus according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a slew rate enhancing apparatus according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;

description of reference numerals:

101-a first latch, 102-a second latch, 103-a first level shifter, 104-a decoder, 105-a gamma voltage supplier, 106-a slew rate enhancement module, 107-an amplifier;

1071-amplifier output stage, 1072-amplifier load stage, 1073-amplifier input stage;

1061-mode detection module, 1062-charging module.

Detailed Description

In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the drawings of the embodiments of the present invention are combined below to clearly and completely describe the technical solution of the embodiments of the present invention. It is to be understood that the embodiments described are only some of the embodiments of the present invention, and not all of them. Based on the described embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without any creative effort belong to the protection scope of the present invention.

The terms "first," "second," and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that embodiments of the invention can be practiced in sequences other than those illustrated or described herein, and the terms "first," "second," and the like are generally used herein in a generic sense without limitation to the number of terms, e.g., the first term can be one, or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.

Furthermore, the technical features mentioned in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other.

Referring to fig. 1, the embodiment of the present invention provides a schematic diagram of a slew rate enhancement circuit, which adds a slew rate enhancement module on a display driving circuit, and can adjust the slew rate of an amplifier output stage according to Data < n:0> input by a DAC (digital-to-analog converter), thereby improving the slew rate of the amplifier output stage. The slew rate is the voltage slew rate (slew rate).

Referring to fig. 1, the slew rate enhancement circuit includes:

a first latch 101, a second latch 102, a first level shifter 103, a slew rate enhancement module 106, and an amplifier 107;

the first latch 101 is configured to store the received first data;

the second latch 102 is configured to store received second data, where the second data is a data subsequent to the first data;

the first level shifter 103 is configured to boost the first data, and use a high-voltage data signal obtained through boosting as current input data of the slew rate enhancement module 106;

the slew rate enhancement module 106 is connected to the amplifier 107, the first level shifter 103, the first latch 101, and the second latch 102, and is configured to adjust a voltage of the amplifier output stage 1071 according to a value of a specified bit of the first data, a value of a specified bit of the second data, and current input data, so as to enhance the slew rate of the amplifier output stage.

Specifically, taking an example that the data input end is an 8-bit DAC (digital-to-analog converter), refer to fig. 2 as a structure diagram of the slew rate enhancement circuit of the 8-bit source code driving IC, so as to illustrate the working mode of the slew rate enhancement circuit provided by the present invention:

the first latch 101 stores and outputs the first data D1<7:0> in a binary form, the second latch 102 stores and outputs the second data D2<7:0> in a binary form, the first level shifter 103 pressurizes the input data D1<7:0> to obtain the high-voltage data signal DH <7:0> and the inverted signal DHB <7:0>, and outputs DH <7:0> and DHB <7:0> to the decoder 104 and the slew rate enhancement module 106, respectively, where DH <7:0> is the current input data of the slew rate enhancement module, and DHB <7:0> is the inverted data of the current input data of the slew rate enhancement module.

Specifically, the value of the specified bit number of the first data and the value of the specified bit number of the second data may be one value, such as the value of the x-th bit D1< x > of the specified first data and the value of the x-th bit D2< x > of the specified second data; or a value specifying a plurality of bits, such as the 7 th bit of the first data D1<7> and the 7 th bit of the second data D2<7>, and the 3 rd bit of the first data D1<3> and the 3 rd bit of the second data D2<3 >; referring to FIG. 2, the value of the designated bit number is the 7 th bit of the first data, the second data, D1<7>, D2<7 >.

It should be noted that the <7:0> symbols in fig. 2 (and the same applies to other figures) are all binary data, and since the example in fig. 2 is 8-bit, the binary data involved is 8-bit binary data, which are respectively the 0 th bit to the 7 th bit, and thus D1< x > and D2< x > are also calculated from the 0 bit.

Optionally, referring to fig. 3, the slew rate enhancement module 106 includes:

a mode detection module 1061, where the mode detection module 1061 is connected to the first latch 101 and the second latch 102, and is configured to determine whether the slew rate of the amplifier output stage 1071 needs to be enhanced according to a value of a specified bit of the first data and a value of a specified bit of the second data, and output a control signal PD according to a determination result;

a charging module 1062, where the charging module 1062 is connected to the output end of the mode detection module 1061, the output end of the first level shifter 103, and a charging voltage end, and is configured to determine whether the slew rate of the amplifier output stage 1071 needs to be enhanced according to the control signal PD and the current input data, and determine a charging voltage input to the amplifier output stage 1071 when the slew rate of the amplifier output stage 1071 needs to be enhanced.

Specifically, the mode detection module 1061 compares D1< x > with D2< x > to determine whether D1< x > is the same as D2< x >, and if D1< x > is the same as D2< x >, the change between the first data and the second data is not large, and the slew rate (i.e., the voltage conversion rate) does not need to be enhanced, for example, when the value of the control signal PD is 0;

d1< x > and D2< x > if different, indicate that the variation between the first data and the second data is large, and the slew rate may need to be enhanced; exemplarily, the value of the control signal PD at this time is 0; and finally whether the slew rate needs to be enhanced or not, further judgment needs to be performed by the charging module 1062 according to the control signal PD and the current input data, when PD is 1 and the current input data belongs to the enabling range of the charging module 1062, the slew rate of the amplifier output stage 1071 needs to be enhanced, and the charging voltage input to the amplifier output stage 1071 is determined by the charging module 1062.

Optionally, the mode detection module 1061 includes:

an exclusive or gate circuit 10611, a D flip-flop 10612, and a second level shifter 10613;

the input end of the xor gate circuit 10611 is connected to the first latch 101 and the second latch 102, and is configured to determine whether the value of the assigned bit of the first data and the value of the assigned bit of the second data are equal, and output a determination result;

the output end of the xor gate 10611 is connected to the D end of the D flip-flop 10612, and the input end of the second level shifter 10613 is connected to the Q end of the D flip-flop 10612, and is configured to determine whether the slew rate of the amplifier output stage 1071 needs to be enhanced according to the determination result of the xor gate 10611, where:

the output end of the second level shifter 10613 is connected to the charging module 1062, and is configured to provide the control signal PD to the charging module.

The Rb end of the D trigger is connected with the inverted signal RSTB signal of the reset signal with low level and effective for resetting the mode detection circuit.

The trigger end of the D trigger is connected to the OENB output enabled inverted signal.

Specifically, referring to fig. 2 and 3, taking the example that 8-Bit Data <7:0> and x is provided at the input end, when D1<7> is the MSB (Most Significant Bit) value of the first Data, D2<7> is the MSB value of the second Data, i.e., D1 is the Data for driving the current display IC, and D2 is the next Data for driving the display IC, when the two values are different, it means that the display mode change is large, and the slew rate needs to be enhanced, specifically, the mode detection module 1061 determines D1<7> and D2<7 >.

Specifically, in making the comparison, when the OENB signal is a rising edge (changes from "0" to "1"), the mode detection module 1061 compares D1<7> and D2<7 >;

if D1<7> is D2<7>, the xor gate circuit in the mode detection module 1061 outputs "0", and PD is 0;

when D1< x > ≠ D2< x >, the mode detection module 1061 outputs "1", and at this time, PD ═ 1 belongs to the enabled range of the mode detection module 1061;

the mode detection module 1061 inputs the value of the control signal PD to the charging module 1062, and if PD is equal to 0, the mode detection module does not belong to the enable range and does not need to enhance the slew rate; if PD is 1, the mode detection module outputs an enable signal at this time, and the slew rate needs to be enhanced, the charging module 1062 needs to further determine according to the current input data, and if the current input data also belongs to the enable range of the charging module 1062, the slew rate of the amplifier output stage 1071 needs to be enhanced, and the charging voltage input to the amplifier output stage 1071 is determined.

Specifically, the above case is a case where only a value of a specified number of bits is specified, as with reference to fig. 2, a value D1<7> of the 7 th bit of the first data, a value D2<7> of the 7 th bit of the second data are specified; the values of different digits are designated for comparison, the enabling range of the mode detection module 1061 can be adjusted, and x can be adjusted according to actual conditions.

Specifically, referring to fig. 2 and fig. 3, an 8-bit binary Data input end is taken as an example, when the total 8 bits of the input Data <7:0> are 0 th bit to 7 th bit, and x is 7, that is, when the seventh bit is designated, the most significant bit is designated, the mode detection module can quickly obtain a judgment result by comparing the most significant bits of the first Data and the second Data, and output the control signal PD.

Optionally, the charging module 1062 includes: a first control switch group 10621 and a second control switch group 10622;

the first control switch group 10621 is connected to the VDD voltage end and connected to the OUTN port of the amplifier output stage 1071 after being connected in series with the first PD control switch 10623;

the second control switch group 10622 is connected to the VSS voltage end and connected in series with the second PD control switch 10624 to the OUTP port of the amplifier output stage 1071;

the first PD control switch 10623 and the second PD control switch 10624 are configured to be turned on or turned off according to a value of the control signal PD;

the first control switch group 10621 is formed by connecting a plurality of switches in series, and is configured to control the on/off of each switch according to whether the current input data belongs to the enabling range of the slew rate enhancement module;

the second control switch group is formed by connecting a plurality of switches 10622 in series, and controls the on/off of each switch according to whether the inverted data of the current input data belongs to the enabling range of the slew rate enhancement module.

Specifically, when the value PD of the received control signal is equal to 1, that is, when the mode detection module 1061 inputs the enable signal to the charging module 1062, the slew rate of the amplifier output stage 1071 needs to be enhanced.

For example, referring to the schematic structure diagram of the slew rate enhancement module 106 shown in fig. 3, taking an 8-bit binary data as an example, wherein 1062 is the schematic structure diagram of the charging module, the first switch group 10621 is formed by serially connecting switches sw <0> to sw <7> respectively corresponding to DH <0> to DH <8>, specifically, when DH < x > of the current input data is equal to the preset value of the first switch group corresponding to the control switch, the switch is closed, otherwise, the switch is open; therefore, all the switches of the first switch group are closed only when the values of DH <0> to DH <8> of the current input data are equal to the preset value, and the current input data belong to the enabling range of the charging module 1062.

The second switch group 10622 is formed by serially connecting switches sw <10> to sw <17> corresponding to DHB <0> to DHB <8 >. Specifically, when the DHB < x > of the current input data is equal to the preset value of the control switch corresponding to the second switch group, the switch is closed, otherwise, the switch is opened; therefore, all switches of the second switch group are closed only when each of the values DHB <0> to DHB <8> of the current input data inverted data is equal to the preset value, and thus belong to the enabling range of the charging module 1062.

The first switch group 10621 controls the on/off of each switch according to whether the current input data belongs to the enabling range of the slew rate enhancement module. Exemplary, when the enabled range is DH <7:0> -00000000 or DHB <7:0> -00000000:

if DH <7:0> -00000001, then switch sw <0> is turned off, the first switch group can not be turned on, the circuit where the first switch group is located can not be connected, at this time, DHB <7:0> -11111110, switches sw <11> -sw <17> are turned off, the circuit where the second switch group is located can not be connected, at this time, the current input data DH <7:0> -00000001 do not belong to the enabling range of the charging module 1062, the control signal output by the on-time mode detection module is the enabling signal PD-1, and the slew rate of the amplifier output stage 1071 does not need to be enhanced;

when DH <7:0> -00000000, DHB <7:0> -11111111, switches sw <0> -sw <10> are closed, and all switches in the first switch group are closed;

when DH <7:0> -11111111, DHB <7:0> -00000000, switches sw <10> -sw <17> are closed, and all switches in the second switch group are closed.

It should be noted that according to different practical requirements, it is not necessary to determine each bit of the current input data or the inverted data thereof, and one or more groups of switches in the first switch and the second switch group may be shifted out, for example, the switches sw <0> and sw <10> corresponding to DH <0> and DHB <0> are shifted out, which does not affect the use of the whole slew rate enhancement module.

Specifically, FIC control switch's effect is equivalent to a switch, can decide whether open the slew rate reinforcing module through user's setting, if set to FIC ═ 0, then slew rate reinforcing module belongs to the off-state, only under the condition that FIC ═ 1, slew rate reinforcing module just belongs to operating condition, and FIC control switch's setting has increased the utility model provides a slew rate reinforcing module's controllability can make the user independently select whether to open slew rate reinforcing module, closes this reinforcing module and can the power saving, opens this module and can obtain better display effect.

After the FIC is reconverted to "0", the RSTB becomes "0", and the slew rate enhancement module is initialized. The FIC signal and RSTB timing added from the outside are changed according to the actual design environment.

With reference to the foregoing embodiments, the slew rate enhancement circuit provided in the embodiments of the present invention is further described.

Referring to fig. 3, a first PD control switch 10623 is connected in series with a first switch group 10621, and a second PD control switch 10624 is connected in series with a second switch group 10622; the two PD control switches are controlled to be turned on or off according to a control signal PD output by the mode detection module 1061, specifically, when PD is equal to 1, the PD control switches are turned on; when the PD is 0, the PD control switch is opened.

The first switch set 10621 is connected to the charging voltage port VDD, and is connected to the OUTN port of the amplifier output stage 1071 after being connected in series with the first PD control switch 10623; the second switch set 10622 is connected to the charging voltage port VSS and is connected in series with the second PD control switch 10624 to the OUTP port of the amplifier output stage 1072.

Specifically, when the FIC control switch closing slew rate enhancement module is in an on state, only when all the switches in the first switch group 10621 and the first PD control switch 10623 belong to the on state, the slew rate enhancement module belongs to an enable state, the charging voltage is determined to be VDD, and the OUTN port of the amplifier output stage 1071 is charged through the VDD voltage terminal; alternatively, when all the switches of the second switch group 10622 and the second PD control switch 10624 are in the closed state, the charging voltage is determined to be VSS, and the OUTP port of the amplifier output stage 1071 is charged by the VSS voltage terminal.

Specifically, the voltage of the accessed charging voltage terminal can be adjusted according to actual requirements, and 2 charging voltage terminals in fig. 3 are provided for the VDD voltage port and the VSS voltage port, respectively, to meet different requirements.

For example, taking 8-bit 2-system Data <7:0>, the value of the specified bit number of the first Data, the specified bit number x of the second Data being 7, the enabling range of the slew rate enhancement module is DH <7:0> -11111111111 (i.e. 255 gray-scale value) and DH <7:0> -00000000 (i.e. 0 gray-scale value) as an example:

1) first, when the OENB signal changes from "0" to "1", the mode detection module 1061 compares D1<7> and D2<7>, and if the output results of the two are the same, the PD signal outputs "0", the first PD control switch SW <8> and the second PD control switch SW <18> are turned off, and the slew rate enhancement module is not enabled.

2) When D1<7> ≠ D2<7>, the PD signal outputs "1", and the switches SW <8> and SW <18> are closed.

3) When SW <8> and SW <18> are closed, and when DH <7:0> is 1-254 gray scale except 11111111(255 gray scale value) or 00000000(0 gray scale value), at least one of SW <0> to SW <7>, SW <10> to SW <17> is opened, and at this time, the at least one of SW <8> and SW <18> does not belong to the enabling range of the slew rate enhancement module, and the slew rate enhancement module is not enabled.

4) When DH <7:0> -11111111 (255 gray-scale value) or DH <7:0> -00000000 (0 gray-scale value), the switches SW <0> -SW <7>, SW <10> -SW <17> are closed.

5) If the FIC is equal to "1", the slew rate enhancement module is started. If DH <7:0> -11111111 (255 gray-scale value), OUTN is connected with VDD voltage end, OUTN port voltage is charged with VDD, reduce the fall time of the output end voltage swing rate (voltage conversion rate) of the amplifier; if DH <7:0> -00000000 (0 gray scale value), OUTP will be connected to VSS, and OUTN voltage will be charged with VSS, so as to reduce the rise time of the slew rate (voltage slew rate) of the output terminal of the amplifier.

For example, when the slew rate enhancement module enables the range:

when PD is 1& FIC, 1& DH <7:0> -11111111111, "OUTN is VDD",

when PD is 1& FIC is 1& DHB <7:0> -11111111, "OUTP is VSS".

When D1<7:0> -11111111 and D2<7:0> -00000000;

d1<7> ≠ D2<7>, PD 1, FIC 1, DH 7:0 11111111, DHB 7:0 00000000, where "OUTN" VDD ".

When D1<7:0> -11111110 and D2<7:0> -00000001;

d1<7> ≠ D2<7>, PD 1, FIC 1, DH 7:0 11111110, and DHB 7:0 00000001, at which time, the slew rate enhancement module does not belong to the enabled state.

When D1<7:0> -11111111 and D2<7:0> -00000001;

When D1<7:0> -11111111 and D2<7:0> -10000000;

d1<7> -D2 <7>, PD-0, FIC-1, DH <7:0> -11111111111, DHB <7:0> -00000000, at which time the slew rate enhancement module does not belong to the enabled state.

When D1<7:0> -00000000, D2<7:0> -01111111;

d1<7> -D2 <7>, PD-0, FIC-1, DH <7:0> -00000000 and DHB <7:0> -11111111, and at this time, the slew rate enhancement module does not belong to the enabled state.

When D1<7:0> -00000000, D2<7:0> -11111111110;

d1<7> ≠ D2<7>, PD 1, FIC 1, DH 7:0 00000000, DHB 7:0 11111111; at this time, "OUTP ═ VSS"

When D1<7:0> -00000001, D2<7:0> -11111111110;

d1<7> ≠ D2<7>, PD 1, FIC 1, DH 7:0 00000001, DHB 7:0 11111110; at this time, the slew rate enhancement module does not belong to the enabled state.

When D1<7:0> -00000000, D2<7:0> -11111111111;

d1<7> ≠ D2<7>, PD 1, FIC 1, DH 7:0 00000000, DHB 7:0 11111111; at this time, "OUTP ═ VSS".

For example, when the slew rate enhancement module enables the range:

when PD is 1& FIC 1& DH <7:0> -1111111 x, "OUTN is VDD";

when PD is 1& FIC is 1& DHB <7:0> -1111111 x, "OUTP is VSS".

When D1<7:0> -11111111 and D2<7:0> -00000000;

d1<7> ≠ D2<7>, PD 1, FIC 1, DH 7:0 11111111, DHB 7:0 00000000; at this time, "OUTN ═ VDD".

When D1<7:0> -11111110 and D2<7:0> -00000001;

d1<7> ≠ D2<7>, PD 1, FIC 1, DH 7:0 11111110, DHB 7:0 00000001; at this time, "OUTN ═ VDD".

When D1<7:0> -11111111 and D2<7:0> -00000001;

When D1<7:0> -11111111 and D2<7:0> -10000000;

d1<7> -D2 <7>, PD ═ 0, FIC ═ 1, DH <7:0> -11111111, DHB <7:0> -00000000; at this time, the slew rate enhancement module does not belong to the enabled state, and the slew rate does not need to be enhanced.

When D1<7:0> -00000000, D2<7:0> -01111111;

d1<7> -D2 <7>, PD-0, FIC-1, DH <7:0> -00000000, DHB <7:0> -11111111; at this time, the slew rate enhancement module does not belong to the enabled state, and the slew rate does not need to be enhanced.

When D1<7:0> -00000000, D2<7:0> -11111111110;

When D1<7:0> -00000001, D2<7:0> -11111111110;

d1<7> ≠ D2<7>, PD 1, FIC 1, DH 7:0 00000001, DHB 7:0 11111110; at this time, "OUTP ═ VSS".

When D1<7:0> -00000000, D2<7:0> -11111111111;

On the one hand, refer to fig. 5, the embodiment of the utility model provides a slew rate reinforcing method is provided, is applied to the utility model provides a slew rate reinforcing circuit, include:

step 501, receiving first data and second data, where the second data is data next to the first data;

step 502, adjusting the voltage of the output stage of the amplifier according to the value of the designated digit of the first data, the value of the designated digit of the second data and the current input data, and enhancing the slew rate of the output stage of the amplifier.

The difference between the first data and the second data can be judged by comparing the value of the designated digit of the first data with the value of the designated digit of the second data, and the difference between the first data and the second data can be enlarged or reduced by comparing the different values of the designated digits of the first data and the second data, so that the enabling range of the slew rate enhancing module can be adjusted. And only when the values of the first data, the second data and the current input data meet the enabling range of the slew rate enhancement module, the slew rate enhancement of the output stage of the amplifier is required, and the charging voltage input to the output stage of the amplifier is determined.

Optionally, the adjusting the voltage of the amplifier output stage and enhancing the slew rate of the amplifier output stage further include:

when the value of the designated digit of the first data is not equal to the value of the designated digit of the second data, judging that the slew rate of the output stage of the amplifier needs to be enhanced;

and when the value of the designated digit of the first data is equal to the value of the designated digit of the second data, judging that the slew rate of the output stage of the amplifier is not required to be enhanced.

Slew rate enhancement of the amplifier output stage is only possible when D1< x > ≠ D2< x >, i.e. the difference between the first data and the second data is large, and the display mode variation is large.

when the slew rate of the output stage of the amplifier needs to be enhanced, if the current input data belongs to the enabling range of the slew rate enhancing module, the charging voltage accessed to the output stage of the amplifier is determined.

When D1< x > ≠ D2< x >, the difference between the first data and the second data is large, and the slew rate enhancement of the amplifier output stage may be required, it is also required to judge whether the current input data belongs to the enabling range of the slew rate enhancement module, if so, the charging voltage accessed to the amplifier output stage is determined, and the specific accessed voltage is preset according to the enabling range.

Optionally, the slew rate enhancement method further includes:

when the internal fast charging signal FIC is equal to 0, the slew rate enhancement module is closed;

and when the internal quick charging signal FIC is equal to 0, starting the slew rate enhancement module.

Specifically, the FIC signal is set according to the use state of the slew rate enhancement circuit, and a user can decide whether to turn on or turn off (disable) the slew rate enhancement module. When the difference of the display driving data input in front and at the back is large, the starting slew rate enhancement module can pre-emphasize the output end of the amplifier, so that the slew rate (voltage conversion rate) of the output end of the amplifier is improved, and a better display effect is brought; and the slew rate enhancement module is closed, so that the electricity can be saved.

Referring to fig. 6, an embodiment of the present invention provides a slew rate enhancement device 60, including:

a first receiving module 601, configured to receive first data and second data, where the second data is a data subsequent to the first data;

the first processing module 602 is configured to adjust a voltage of the output stage of the amplifier according to the value of the specified bit of the first data, the value of the specified bit of the second data, and the current input data, so as to enhance the slew rate of the output stage of the amplifier. Optionally, referring to fig. 7, the first processing module 602 includes:

the first judgment submodule 6021 is configured to judge that the slew rate of the output stage of the amplifier needs to be increased when the value of the specified digit of the first data is not equal to the value of the specified digit of the second data; and when the value of the designated digit of the first data is equal to the value of the designated digit of the second data, judging that the slew rate of the output stage of the amplifier is not required to be enhanced.

Optionally, referring to fig. 7, the first processing module 602 further includes:

the first processing submodule 6022 is configured to determine, when the slew rate of the amplifier output stage needs to be enhanced, a charging voltage to be applied to the amplifier output stage if the current input data belongs to the enabling range of the slew rate enhancement module.

The embodiment of the utility model provides a pair of pressure slew rate reinforcing means 60 with the embodiment of the utility model provides a pressure slew rate reinforcing circuit, pressure slew rate reinforcing method can reach the same technological effect, for avoiding repetitiously, no longer gives unnecessary details here.

On the one hand, the embodiment of the utility model provides a source driver chip is still provided, include the embodiment of the utility model provides an arbitrary item the slew rate reinforcing circuit.

On the one hand, the embodiment of the utility model provides a still provide a display device, include the embodiment of the utility model provides a source driver chip.

Referring to fig. 8, an embodiment of the present invention further provides an electronic device 800, including a processor 801, a memory 802, and a computer program stored in the memory 802 and capable of running on the processor 801, where the computer program is executed by the processor 801 to implement the processes of the embodiment of the slew rate enhancement method, and can achieve the same technical effects, and in order to avoid repetition, the detailed description is omitted here.

The embodiment of the utility model provides a still provide a computer readable storage medium, the last computer program that stores of computer readable storage medium, computer program realizes each process of the embodiment of above-mentioned slew rate reinforcing method when being executed by the treater, and can reach the same technological effect, for avoiding repetitiously, no longer gives unnecessary details here. The computer-readable storage medium may be a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention essentially or the portions contributing to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), and includes a plurality of instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications can be made without departing from the scope of the invention.

Claims

1. A slew rate enhancement circuit, comprising:

the first latch is used for storing the received first data;

the slew rate enhancement module is connected with the amplifier, the first level shifter, the first latch and the second latch, and is used for adjusting the voltage of the output stage of the amplifier according to the value of the specified bit of the first data, the value of the specified bit of the second data and the current input data, so as to enhance the slew rate of the output stage of the amplifier.

2. The slew rate enhancement circuit of claim 1, wherein the slew rate enhancement module comprises:

3. The slew rate enhancement circuit of claim 2, wherein the mode detection module comprises:

an exclusive-or gate circuit, a D flip-flop and a second level shifter;

when the value of the designated digit of the first data is not equal to the value of the designated digit of the second data, obtaining and outputting a judgment result of the slew rate of the output stage of the amplifier which may need to be enhanced;

the output end of the second level shifter is connected with the charging module and is used for providing the control signal PD for the charging module.

4. The slew rate enhancement circuit of claim 1, wherein the values of the specified number of bits of the first data and the specified number of bits of the second data comprise:

5. The slew rate enhancement circuit of claim 4, where the xth bit is the most significant bit of the first and/or second data.

6. The slew rate enhancement circuit of claim 2, wherein the charging module comprises: the first control switch group and the second control switch group;

7. The slew rate enhancement circuit of claim 6, where the charging module further comprises two internal fast charging FIC control switches:

8. A source driver chip comprising the slew rate enhancement circuit of any one of claims 1-7.

9. A display device comprising the source driver chip according to claim 8.