CN114283719B - Switch control circuit, driving method thereof and display device - Google Patents
Switch control circuit, driving method thereof and display device Download PDFInfo
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- CN114283719B CN114283719B CN202111666877.0A CN202111666877A CN114283719B CN 114283719 B CN114283719 B CN 114283719B CN 202111666877 A CN202111666877 A CN 202111666877A CN 114283719 B CN114283719 B CN 114283719B
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Abstract
The invention discloses a switch control circuit, a driving method thereof and a display device. The first signal input end is used for providing a first signal to the first control unit and controlling the potentials of the first node and the second node in a time period, so that the second control unit outputs a signal to at least one of the second output end and the third output end through the second signal input end under the control of the signals of the first node and the second node; alternatively, a signal is output to the first output terminal through the first signal input terminal and the second output terminal. The switch control circuit can realize the control of the output signals of different output ends by only introducing two signal input ends, is beneficial to reducing the number of the signal input ends of the switch control circuit, and is beneficial to reducing the power load and loss when being matched with a power supply.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a switch control circuit, a driving method thereof, and a display device.
Background
The micro light emitting diode (micro LED), namely the technology of light emitting diode miniaturization and matrixing, has the advantages of good stability, service life and operating temperature, inherits the advantages of low power consumption, high color saturation, high reaction speed, high contrast ratio and the like of the LED, and has great application prospect. Displays made from micro leds are a major future development of display devices. In the current production process of micro led displays, before a display panel in a micro led display is cut, in order to detect whether a short circuit exists in a scanning line transmission area and a data line transmission area, an electrical test is performed. And during an electrical test, the voltage is directly poured into the scanning line transmission area and the data line transmission area of the display panel for testing, the power is cut off after the testing is finished, the display panel is cut, and the display panel is packaged after the cutting is finished, so that a display product is finally formed.
In the test circuit in the prior art, each data line of the data line transmission area in the display panel is required to be connected with the output pins of the power supply one by one, so that each output pin of the power supply is required to be output during testing.
Disclosure of Invention
In view of this, the present invention provides a switch control circuit, a driving method thereof, and a display device, in which control of output signals of different output terminals can be achieved by only introducing two signal input terminals, which is beneficial to reducing the number of signal input terminals of the switch control circuit, and is beneficial to reducing operation complexity and reducing power load and loss when being used in cooperation with a power supply.
In a first aspect, the present invention provides a switch control circuit comprising: the first signal input end, the second signal input end, the first control unit, the second control unit, the first output end, the second output end and the third output end; the first control unit comprises a first node and a second node, and the first node and the second node are respectively and electrically connected with the second control unit;
the first signal input end is electrically connected with the first control unit, the second signal input end is electrically connected with the second control unit, the first control unit is also electrically connected with the first output end, and the second control unit is also electrically connected with the second output end and the third output end respectively;
the first signal input terminal is used for providing a first signal to the first control unit and controlling the electric potentials of the first node and the second node in a time period, so that the second control unit outputs a signal to at least one of the second output terminal and the third output terminal through the second signal input terminal under the control of the signals of the first node and the second node; or outputting a signal to the first output terminal through the first signal input terminal and the second output terminal.
In a second aspect, the present invention further provides a driving method of a switch control circuit, which is applied to the switch control circuit provided in the first aspect of the present invention, and the driving method includes:
in a first period, the signal of the first signal input end is a first level signal, so that the potential of the first node is a first potential, and the second signal input end is controlled to output a first data signal to the third output end;
in a second period, the signal of the first signal input end is a second level signal, so that the potential of the second node is a first potential, and the second signal input end is controlled to output a second data signal to the second output end;
and in a third period, the signal of the first signal input end is a second level signal, the signal of the second signal input end is a first level signal, and the first signal input end is controlled to output a third data signal to the first output end.
In a third aspect, the present invention provides a display device including a data line and the switch control circuit provided in the first aspect of the present invention.
Compared with the prior art, the switch control circuit, the driving method thereof and the display device provided by the invention have the advantages that at least the following effects are realized:
The invention provides a switch control circuit, a driving method thereof and a display device. When corresponding level signals or data signals are respectively provided for the first signal input end and the second signal input end, the first output end can be respectively controlled to output the first data signal, the second output end can be controlled to output the second data signal and the third output end can be controlled to output the third data signal, so that the control of the output signals of different output ends can be realized by only introducing two signal input ends into the switch control circuit. When the switch control circuit is arranged in the display device, the same output end can be connected with the data lines corresponding to the sub-pixels with the same color, and when the display device is provided with the sub-pixels with three different colors, the first output end, the second output end and the third output end are respectively connected with the data lines corresponding to the sub-pixels with different colors, so that the test of the sub-pixels connected with all the data lines in the whole display device can be realized through one switch control module, and the circuit complexity of the display device is greatly simplified.
Of course, it is not necessary for any one product embodying the invention to achieve all of the technical effects described above at the same time.
Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a block diagram of a switch control circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a switch control circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of another structure of a switch control circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of another structure of a switch control circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of another structure of a switch control circuit according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating a driving method of a switch control circuit according to an embodiment of the present invention;
FIG. 7 is a timing diagram showing the switch control circuit providing a red display signal;
FIG. 8 is a timing diagram showing a switch control circuit providing a green display signal;
FIG. 9 is a timing diagram showing a switch control circuit providing a blue frame display signal;
FIG. 10 is a timing diagram showing a switch control circuit providing a white display signal;
FIG. 11 is a top view of a display device according to an embodiment of the present invention;
FIG. 12 is a schematic diagram showing a connection between a data line and a switch control circuit on a display panel of the display device;
FIG. 13 is a schematic diagram showing a structure of a power module for testing data lines on a display device;
fig. 14 is a schematic diagram showing another structure of testing the data line on the display device by using the power module.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
Fig. 1 is a block diagram of a switch control circuit according to an embodiment of the present invention, please refer to fig. 1, and the switch control circuit according to an embodiment of the present invention includes: a first signal input terminal D1, a second signal input terminal D2, a first control unit 10, a second control unit 20, a first output terminal OUT1, a second output terminal OUT2, and a third output terminal OUT3; the first control unit 10 includes a first node N1 and a second node N2, and the first node N1 and the second node N2 are electrically connected to the second control unit 20, respectively;
The first signal input end D1 is electrically connected to the first control unit 10, the second signal input end D2 is electrically connected to the second control unit 20, the first control unit 10 is further electrically connected to the first output end OUT1, and the second control unit 20 is further electrically connected to the second output end OUT2 and the third output end OUT3, respectively;
the first signal input terminal D1 is configured to provide the first signal to the first control unit 10 and control the potentials of the first node N1 and the second node N2 such that the second control unit 20 outputs a signal to at least one of the second output terminal OUT2 and the third output terminal OUT3 through the second signal input terminal D2 under the control of the signals of the first node N1 and the second node N2 during a period of time; alternatively, a signal is output to the first output terminal OUT1 through the first signal input terminal D1 and the second output terminal OUT 2.
The switch control circuit provided by the invention comprises two signal input ends, two control modules and three output ends, namely a first signal input end D1 and a second signal input end D2, a first control unit 10 and a second control unit 20, and a first output end OUT1, a second output end OUT2 and a third output end OUT3, wherein the first signal input end D1 is electrically connected with the first control unit 10, and the second signal input end D2 is electrically connected with the second control unit 20. When corresponding level signals or data signals are respectively provided for the first signal input end D1 and the second signal input end D2, the potentials of the first node N1 and the second node N2 can be controlled, and then the first output end OUT1 is respectively controlled to output the first data signals, the second output end OUT2 is controlled to output the second data signals and the third output end OUT3 is controlled to output the third data signals, so that the control of the output signals of different output ends can be realized by only introducing two signal input ends into the switch control circuit. When the switch control circuit is arranged in the display device, the same output end can be connected with the data lines corresponding to the sub-pixels with the same color, and when the display device is provided with the sub-pixels with three different colors, the first output end OUT1, the second output end OUT2 and the third output end OUT3 are respectively connected with the data lines corresponding to the sub-pixels with different colors, so that the test of the sub-pixels connected with all the data lines in the whole display device can be realized through one switch control module, and the circuit complexity of the display device is greatly simplified.
Fig. 1 illustrates only the block configuration of the switch control circuit, and the specific configurations of the first control unit 10 and the second control unit 20 will be described in the following embodiments.
Fig. 2 is a schematic diagram of a switch control circuit according to an embodiment of the present invention, in which the circuit configuration of the first control unit 10 in the switch control circuit is illustrated.
Referring to fig. 2, in an alternative embodiment of the present invention, the first control unit 10 includes a first transistor M1, a second transistor M2, a third transistor M3, a first capacitor C1 and a second capacitor C2, wherein one of the first transistor M1 and the second transistor M2 is a P-type transistor, and the other is an N-type transistor;
the gate of the first transistor M1, the first pole of the first transistor M1, the gate of the second transistor M2 and the first pole of the second transistor M2 are all connected to the first signal input terminal D1; the second pole of the first transistor M1 is connected with the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected with the first node N1; the second pole of the second transistor M2 is connected with a second node N2;
the first pole of the third transistor M3 is connected to the first node N1 and the second node N2, respectively, the gate of the third transistor M3 is connected to the first end of the second capacitor C2, the second pole of the third transistor M3 is connected to the first output terminal OUT1, and the second end of the second capacitor C2 is connected to the second output terminal OUT2.
In the switch control circuit provided in the embodiment of the present invention, the types of the first transistor M1 and the second transistor M2 introduced in the first control unit 10 are different, fig. 2 illustrates that the first transistor M1 is an N-type transistor and the second transistor M2 is a P-type transistor, and in some other embodiments of the present invention, the first transistor M1 may also be a P-type transistor and the second transistor M2 may also be an N-type transistor. When the transistor is a P-type transistor, the gate is turned on under the control of a low level signal and turned off under the control of a high level signal. When the transistor is an N-type transistor, its gate is turned on under control of a high level signal and turned off under control of a low level signal. In the following, a scheme in which the first transistor M1 is an N-type transistor and the second transistor M2 is a P-type transistor will be described with reference to fig. 2.
When the signal of the first signal input terminal D1 is a high level signal, the first transistor M1 is turned on, and the second transistor M2 is turned off, and since the first capacitor C1 is electrically connected to the second electrode of the first transistor M1, when the first transistor M1 is turned on, the high level signal of the first signal input terminal D1 charges the first capacitor C1, increases the potential of the first node N1, and changes the first node N1 to a high potential for transmission to the second control unit 20. When the signal of the first signal input terminal D1 is a low level signal, the first transistor M1 is turned off, the second transistor M2 is turned on, the low level signal of the first signal input terminal D1 is transmitted to the second node N2 through the turned-on second transistor M2, and the signal of the second node N2 is changed into a low level signal, and is further transmitted to the second control unit 20.
The embodiment shown in fig. 2 is exemplified by the third transistor M3 being an N-type transistor, and in other embodiments of the present invention, the third transistor M3 may also be embodied as a P-type transistor. When the third transistor M3 is an N-type transistor, it is turned on under the control of a high level signal and turned off under the control of a low level signal. The gate of the third transistor M3 is connected to the second capacitor C2, the second capacitor C2 is further connected to the second output terminal OUT2, and when the signal output from the second output terminal OUT2 is a high level signal, the high level signal is coupled to the gate of the third transistor M3 through the second capacitor C2, thereby turning on the third transistor M3. When both the third transistor M3 and the second transistor M2 are turned on, a data signal is input at the first signal input terminal D1, and the data signal may be transmitted to the first output terminal OUT1 through the second transistor M2 and the third transistor M3, thereby realizing output of the data signal to the first output terminal OUT 1.
With continued reference to fig. 2, in an alternative embodiment of the invention, the third transistor M3 is of the same type as the first transistor M1.
The third transistor M3 is of the same type as the first transistor M1, meaning that the third transistor M3 and the first transistor M1 are both P-type transistors or the third transistor M3 and the first transistor M1 are both N-type transistors. The embodiment shown in fig. 2 is only exemplified by the case where the third transistor M3 and the first transistor M1 are both N-type transistors, and in some other embodiments of the present invention, the third transistor M3 and the first transistor M1 may also be both P-type transistors.
As can be seen from fig. 2, when the third transistor M3 is turned on, the purpose thereof is to output the data signal to the first output terminal OUT1 through the first signal input terminal D1. At this time, the second transistor M2 is required to be turned on, and at the same time, the second output terminal OUT2 is required to be able to input a high level signal to the gate of the third transistor M3, the high level signal of the second output terminal OUT2 being provided by the second signal input terminal D2. The low level signal input from the first signal input terminal D1 turns on the second transistor M2 and turns off the first transistor M1. When the second transistor M2 and the third transistor M3 are simultaneously turned on, a data signal may be input through the first signal input terminal D1, and the data signal may be transmitted to the first output terminal OUT1 through the second transistor M2 and the third transistor M3.
Fig. 3 is a schematic diagram showing another configuration of a switch control circuit according to an embodiment of the present invention, in which the circuit configuration of the second control unit 20 in the switch control circuit is shown.
Referring to fig. 3, in an alternative embodiment of the present invention, the second control unit 20 includes a fourth transistor M4 and a fifth transistor M5, wherein one of the fourth transistor M4 and the fifth transistor M5 is a P-type transistor, and the other is an N-type transistor;
The grid electrode of the fourth transistor M4 is connected with the second node N2, the first electrode is connected with the second signal input end D2, and the second electrode is connected with the second output end OUT2;
the gate of the fifth transistor M5 is connected to the first node N1, the first pole is connected to the second signal input terminal D2, and the second pole is connected to the third output terminal OUT3.
Fig. 3 shows a specific circuit configuration of the second control unit 20, and this embodiment is described by taking the fourth transistor M4 as a P-type transistor and the fifth transistor M5 as an N-type transistor as an example, and in some other embodiments of the present invention, the fourth transistor M4 may also be embodied as an N-type transistor, and the fifth transistor M5 may also be embodied as a P-type transistor.
Specifically, with continued reference to fig. 3, this embodiment is described taking as an example that the fourth transistor M4 and the second transistor M2 are P-type transistors, and the fifth transistor M5 and the first transistor M1 are N-type transistors.
When the first signal input end D1 is a high level signal, the first transistor M1 is turned on, the second transistor M2 is turned off, the high level signal of the first signal input end D1 charges the first capacitor C1, so that the high level signal is coupled to the gate of the fifth transistor M5, and the fifth transistor M5 is turned on. When a data signal is input to the second signal output terminal, the data signal will be able to be transmitted to the third output terminal OUT3 through the fifth transistor M5, and the data signal output from the second signal input terminal D2 may be set according to the need.
When the first signal input terminal D1 is a low level signal, the first transistor M1 is turned off, the second transistor M2 is turned on, and the low level signal of the first signal input terminal D1 is coupled to the gate of the fourth transistor M4 to control the fourth transistor M4 to be turned on. When a data signal is input to the second signal input terminal D2, the data signal may be transmitted to the second output terminal OUT2 through the fourth transistor M4, and the data signal output from the second signal terminal may be set according to the need.
When the first signal input end D1 is a low level signal and the second signal input end D2 is a high level signal, the first transistor M1 is turned off and the second transistor M2 is turned on, the low level signal of the first signal input end D1 is coupled to the gate of the fourth transistor M4 to turn on the fourth transistor M4, and the high level signal of the second signal input end D2 is coupled to the gate of the third transistor M3 through the second capacitor C2 to turn on the third transistor M3. When a data signal is input to the first signal input terminal D1, the data signal may be transmitted to the first output terminal OUT1 through the second transistor M2 and the third transistor M3, and the data signal output from the first output terminal OUT1 may be set according to the need.
Therefore, the signals of the first output end OUT1, the second output end OUT2 and the third output end OUT3 can be respectively output by controlling the signals of the first signal input end D1 and the second signal input end D2, namely, the output of different signals can be realized by only introducing two signal input ends into the switch control circuit, the number of the signal input ends of the switch control circuit is greatly reduced, and when the switch control circuit is matched with a power supply for testing, the switch control circuit is beneficial to reducing the load and the loss of the power supply.
Fig. 4 is a schematic diagram showing another configuration of a switch control circuit according to an embodiment of the present invention, in which the circuit configuration of the second control unit 20 in the switch control circuit is shown.
Referring to fig. 4, in an alternative embodiment of the present invention, the second control unit 20 further includes a third capacitor C3, wherein a first end of the third capacitor C3 is connected to the gate of the fourth transistor M4, and a second end of the third capacitor C is connected to the second node N2.
Specifically, the third capacitor C3 is introduced between the gate of the fourth transistor M4 and the second node N2, when the signal of the first signal input terminal D1 is a low level signal, the second transistor M2 is turned on, the low level signal of the first signal input terminal D1 can be coupled to the third capacitor C3 through the second transistor M2, the potential of one end connected to the third capacitor C3 and the second node N2 is pulled down, and then the potential of the other end of the third capacitor C3 is pulled down, so that the gate of the fourth transistor M4 is a low level signal, and the fourth transistor M4 is controlled to be turned on. When the fourth transistor M4 is turned on, a data signal can be output to the second output terminal OUT2 through the second signal input terminal D2, or a high level signal can be output through the second signal input terminal D2, so that the high level signal is coupled to the gate of the third transistor M3 through the second capacitor C2, and the third transistor M3 is controlled to be turned on. When both the third transistor M3 and the second transistor M2 are turned on, the first output terminal OUT1 may output a data signal to the first output terminal OUT1 through the second transistor M2 and the third transistor M3.
In the switch control circuit provided by the invention, the first capacitor C1, the second capacitor C2 and the third capacitor C3 are introduced, and the capacity of the capacitors can influence the on-state of the transistors connected with the capacitors. For example, the first capacitor C1 is connected to the gate of the fifth transistor M5, the high level signal is coupled to the fifth transistor M5 through the first capacitor C1 to control the fifth transistor M5 to be turned on, the potential of the gate of the fifth transistor M5 gradually decreases as the first capacitor C1 discharges, the fifth transistor M5 changes from the full-on state to the half-on state, and the value of the data signal transmitted to the third output terminal OUT3 through the fifth transistor M5 also changes, i.e., the value of the data signal output to the third output terminal OUT3 is different in different on states of the fifth transistor M5. Similarly, when the second capacitor C2 is connected to the gate of the third transistor M3, and the second capacitor C2 couples the high level to the gate of the third transistor M3, the third transistor M3 is turned on, and as the potential of the gate of the third transistor M3 gradually decreases due to the discharging of the second capacitor C2, the third transistor M3 changes from the fully-on state to the half-on state, and the value of the data signal transmitted to the first output terminal OUT1 through the third transistor M3 also changes, i.e., the value of the data signal output to the first output terminal OUT1 is different in different on states of the second capacitor C2. Similarly, when the third capacitor C3 is connected to the gate of the fourth transistor M4 and the low level signal is coupled to the gate of the fourth transistor M4 through the third capacitor C3, the fourth transistor M4 is turned on, and as the potential of the end of the third capacitor C3 connected to the third transistor M3 increases, the fourth transistor M4 changes from the fully-on state to the half-on state, and the value of the data signal transmitted to the second output terminal OUT2 through the fourth transistor M4 also changes, i.e., the value of the data signal output to the second output terminal OUT2 is different in different on states of the third capacitor C3.
In an alternative embodiment of the present invention, the capacitance value of the first capacitor C1 is C01, the capacitance value of the second capacitor C2 is C02, and the capacitance value of the third capacitor C3 is C03, wherein 50f is equal to or less than C01 is equal to or less than 800f,50f is equal to or less than C02 is equal to or less than 800f, and 50f is equal to or less than C03 is equal to or less than 800f.
Specifically, in the embodiment of the invention, the capacitance values of the three capacitors in the switch control circuit are set between 50f and 800f, so that the control requirement of each capacitor on the on state of the grid electrode of the corresponding transistor can be met. Alternatively, the capacitance value of each capacitor may be set between 100f and 600f, between 60f and 700f, or the like.
In an alternative embodiment of the invention, C01 > C03 > C02. When the capacitance values of the three capacitors are set to be different, the time for maintaining the on state of the transistors connected with the three capacitors will be different, so that the values of the data signals input to the three output terminals will be different. When the switch control circuit in the embodiment of the present invention is applied to the display device, the three output terminals of the switch control circuit may be electrically connected to the data lines corresponding to the different sub-pixels, for example, the first output terminal OUT1 is electrically connected to the data line corresponding to the first color sub-pixel, the second output terminal OUT2 is electrically connected to the data line corresponding to the second color sub-pixel, and the third output terminal OUT3 is electrically connected to the data line corresponding to the third color sub-pixel. The invention can control the three output ends to output different data signals by setting the three capacitors with different capacitance values, thereby being beneficial to simplifying the structure of the switch control circuit. Alternatively, c01=800 f, c03=200 f, c02=50f.
Fig. 5 is a schematic diagram showing another configuration of a switch control circuit according to an embodiment of the present invention, in which the circuit configuration of the second control unit 20 in the switch control circuit is shown.
In an alternative embodiment of the present invention, the fourth transistor M4 includes a first sub-transistor M41 and a second sub-transistor M42 connected in series between the second signal input terminal D2 and the second output terminal OUT2, and the gates M42 of the first sub-transistor M41 and the second sub-transistor are coupled to the second node N2. Specifically, in the switch control circuit provided by the embodiment of the present invention, the fourth transistor M4 in the second control unit 20 is configured to have a dual-gate structure, that is, includes the first sub-transistor M41 and the second sub-transistor M42 connected in series, and the design of the dual-gate structure is adopted, so that the leakage current of the fourth transistor M4 is reduced.
With continued reference to fig. 4 and 5, in an alternative embodiment of the present invention, the fourth transistor M4 is of the same type as the second transistor M2, and the fifth transistor M5 is of the same type as the first transistor M1.
Specifically, in the embodiment of the present invention, when the fourth transistor M4 and the second transistor M2 are both P-type transistors or both N-type transistors, as an example of the embodiment shown in fig. 5, the fourth transistor M4 and the second transistor M2 are both P-type transistors, when the first signal input terminal D1 inputs a low-level signal, the low-level signal can control the second transistor M2 to be turned on, and the low-level signal is coupled to the gate of the fourth transistor M4 through the third capacitor C3, so that the fourth transistor M4 is turned on, and therefore, no extra control signal terminal is required to be introduced to individually control the on and off of the fourth transistor M4, which is beneficial to reducing the number of signal terminals included in the switch control circuit. Similarly, the fifth transistor M5 and the first transistor M1 may be both N-type transistors or P-type transistors, as long as they are different from the second transistor M2 and the fourth transistor M4. Taking fig. 5 as an example, the fifth transistor M5 and the first transistor M1 are both N-type transistors, when the first signal input end D1 inputs a high level signal, the first transistor M1 is turned on, the high level signal of the first signal input end D1 is coupled to the gate of the fifth transistor M5 through the first capacitor C1, so that the fifth transistor M5 is also turned on, and therefore, no extra control signal end is needed to be introduced to separately control the on and off of the fifth transistor M5, which is beneficial to reducing the number of signal terminals included in the switch control circuit. Therefore, the second transistor M2 and the fourth transistor M4 are set to be of the same type, and the first transistor M1 and the fifth transistor M5 are set to be of the same type, which is beneficial to reducing the number of signal terminals included in the switch control circuit, and only two signal input ends are needed to be introduced to realize the signal output of three output ends, so that the structure of the switch control circuit is simplified, and the power load and loss are beneficial to being reduced when the switch control circuit is applied to the detection circuit.
With continued reference to fig. 5, in an alternative embodiment of the present invention, the aspect ratios of the first transistor M1, the third transistor M3 and the fifth transistor M5 are the same, the aspect ratio of the fourth transistor M4 is smaller than the aspect ratio of the first transistor M1, and the aspect ratio of the second transistor M2 is larger than the aspect ratio of the first transistor M1.
When the aspect ratios of the first transistor M1, the third transistor M3 and the fifth transistor M5 are set to be the same, the same aspect ratio specification is adopted to form the transistors, so that the manufacturing difficulty of different transistors in the switch control circuit is facilitated to be simplified. Since the gate of the third transistor M3 and the gate of the fourth transistor M4 are both connected to the second node N2, when the aspect ratio of the fourth transistor M4 is set to be the minimum, the fourth transistor M4 is made more stable, and the influence of the fourth transistor M4 on the fifth transistor M5 is effectively avoided. Alternatively, the width-to-length ratio of the first transistor M1, the third transistor M3 and the fifth transistor M5 is 6/4, the width-to-length ratio of the fourth transistor M4 is 3/19, and the width-to-length ratio of the second transistor M2 is 8/4.
Based on the same inventive concept, the present invention also provides a driving method of a switch control circuit, and fig. 6 is a flowchart of a driving method of a switch control circuit provided by an embodiment of the present invention, where the driving method is applied to the switch control circuit of any one of the above embodiments of the present invention, and the driving method includes:
In the first period, the signal of the first signal input terminal D1 is a first level signal, so that the potential of the first node N1 is the first potential, and the second signal input terminal D2 is controlled to output the first data signal to the third output terminal OUT 3;
in the second period, the signal of the first signal input terminal D1 is a second level signal, so that the potential of the second node N2 is the first potential, and the second signal input terminal D2 is controlled to output a second data signal to the second output terminal OUT 2;
in the third period, the signal of the first signal input terminal D1 is the second level signal, the signal of the second signal input terminal D2 is the first level signal, and the first signal input terminal D1 is controlled to output the third data signal to the first output terminal OUT 1.
It should be noted that, although the working processes of the first period, the second period and the third period are described in the above driving method, the sequence of the first period, the second period and the third period is not limited, and in some other embodiments of the present invention, the first period, the second period and the third period may be performed in any sequence, which is not particularly limited in this invention.
When the switch control circuit according to the embodiment of the present invention is applied to a display device, the switch control terminal circuit may pass through three output terminals, namely, a red picture signal, a green picture signal, a blue picture signal and a white picture signal, and the operation process of the driving method of the switch control circuit according to the present invention will be described with reference to specific timings. Fig. 7 is a timing chart showing when the switch control circuit provides the red screen display signal, fig. 8 is a timing chart showing when the switch control circuit provides the green screen display signal, fig. 9 is a timing chart showing when the switch control circuit provides the blue screen display signal, and fig. 10 is a timing chart showing when the switch control circuit provides the white screen display signal.
Referring to fig. 5 to fig. 7, when the first signal input terminal D1 inputs a high level signal (e.g., 8V), the first transistor M1 is turned on, and the high level signal of the first signal input terminal D1 is coupled to the fifth transistor M5 through the first capacitor C1, so that the fifth transistor M5 is turned on; the second signal input terminal D2 supplies a red picture display signal (dataR) to the third output terminal OUT3, thereby realizing the output of the red picture display signal.
Referring to fig. 5, fig. 6 and fig. 8, when the first signal input end D1 inputs a low level signal, the second transistor M2 is turned on, and the low level signal of the first signal input end D1 is coupled to the fourth transistor M4 through the third capacitor C3, so that the fourth transistor M4 is turned on; the second signal input terminal D2 inputs the green picture display signal to the second output terminal OUT2, thereby realizing the output of the green picture display signal.
Referring to fig. 5, fig. 6 and fig. 9, when the first signal input end D1 inputs a low level signal, the second transistor M2 is turned on, and the low level signal of the first signal input end D1 is coupled to the fourth transistor M4 through the third capacitor C3, so that the fourth transistor M4 is turned on; the second signal input terminal D2 inputs a high level signal (e.g., 8V) coupled to the gate of the third transistor M3 through the fourth transistor M4 and the second capacitor C2, and turns on the third transistor M3, and at this time, a blue picture display signal (dataB) is input to the first output terminal OUT1 through the first signal input terminal D1, thereby realizing the output of the blue picture display signal.
Referring to fig. 5, 6 and 10, when the first signal input terminal D1 inputs a high level signal (8V), the first transistor M1 is turned on, the high level signal is coupled to the gate of the fifth transistor M5 through the first capacitor C1, and the fifth transistor M5 is turned on; when the first signal input terminal D1 inputs a low level signal (8V), the second transistor M2 is turned on, the low level signal is coupled to the gate of the fourth transistor M4 through the third capacitor C3, so that the fourth transistor M4 is turned on, and at this time, the high level signal of the second signal input terminal D2 is coupled to the third transistor M3 through the second capacitor C2, so that the third transistor M3 is turned on, so that each transistor in the switch control circuit is turned on. The white picture display signal is input to the output end through the second signal input end D2, so that the white picture display signal can be output.
Based on the same inventive concept, the present invention further provides a display device, fig. 11 is a top view of the display device provided by the embodiment of the present invention, fig. 12 is a schematic connection diagram of a data line and a switch control circuit on a display panel of the display device, please refer to fig. 11 and fig. 12, the display device provided by the embodiment of the present invention includes the data line and the switch control circuit of any one of the foregoing embodiments, wherein a first output terminal, a second output terminal and a third output terminal of the switch control circuit are respectively electrically connected with the data line.
When the switch control circuit is applied to the display device, optionally, the switch control circuit is integrated on a display panel in the display device, and an output terminal of the switch control circuit is used for being electrically connected with a data line on the display panel. In the production process of the display device, signals can be input to the first signal input end D1 and the second signal input end D2 in the switch control end circuit by matching with an external detection power supply, so that the detection function of each data line on the display panel is realized. The detection of each data line can be realized by only introducing one switch control circuit into the display device, and the switch control circuit is only provided with two signal input ends, so that the power supply load and loss can be reduced when the switch control circuit is matched with a power supply for testing.
Fig. 13 is a schematic diagram of a structure for testing a data line on a display device using a power module, fig. 14 is a schematic diagram of another structure for testing a data line on a display device using a power module, and fig. 13 shows an implementation in which a display device corresponds to a switch control circuit and a power module is used for testing. In the embodiment shown in fig. 14, one display device corresponds to 4 switch control circuits, and each switch control circuit corresponds to one power module, so that partition detection of the display device can be realized. It will be appreciated that fig. 13 and 14 show only one connection schematic of the switch control circuit to the display area AA on the display panel, and do not represent an actual structure.
Referring to fig. 12, in an alternative embodiment of the present invention, the data lines include a first data line electrically connected to the first output terminal OUT1, a second data line electrically connected to the second output terminal OUT2, and a third data line electrically connected to the third output terminal OUT3.
Optionally, the display panel includes three data lines, wherein the first data line may provide a display signal for a red subpixel on the display panel, the second data line may provide a display signal for a green subpixel on the display panel, and the third data line may provide a display signal for a blue subpixel on the display panel. In an actual display device, each first data line is connected to the third output terminal OUT3 of the switch control circuit, each second data line is connected to the second output terminal OUT2 of the switch control circuit, and each third data line is connected to the third output terminal OUT3 of the switch control circuit. When the display condition of the red picture is required to be detected, a red picture display signal is input to each first data line through a third output end OUT 3; when the display condition of the green picture needs to be detected, a green picture display signal is input to each second data line through a second output end OUT 2; when the display condition of the blue picture needs to be detected, a blue picture display signal is input to each third data line through the third output terminal OUT3.
Therefore, a switch control circuit is introduced into the display device, and two signal input ends and three signal output ends are introduced into the switch control circuit, so that detection of each data line in the display panel can be realized, and the structural complexity of the display device is greatly simplified.
It should be noted that, the embodiment of the display device provided by the present invention may refer to the embodiment of the display module in the present invention, and the repetition is not repeated. The display device provided by the embodiment of the invention can be embodied as any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In summary, the switch control circuit, the driving method thereof and the display device provided by the invention at least realize the following beneficial effects:
the invention provides a switch control circuit, a driving method thereof and a display device. When corresponding level signals or data signals are respectively provided for the first signal input end and the second signal input end, the first output end can be respectively controlled to output the first data signal, the second output end can be controlled to output the second data signal and the third output end can be controlled to output the third data signal, so that the control of the output signals of different output ends can be realized by only introducing two signal input ends into the switch control circuit. When the switch control circuit is arranged in the display device, the same output end can be connected with the data lines corresponding to the sub-pixels with the same color, and when the display device is provided with the sub-pixels with three different colors, the first output end, the second output end and the third output end are respectively connected with the data lines corresponding to the sub-pixels with different colors, so that the test of the sub-pixels connected with all the data lines in the whole display device can be realized through one switch control module, and the circuit complexity of the display device is greatly simplified.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (13)
1. A switch control circuit, comprising: the first signal input end, the second signal input end, the first control unit, the second control unit, the first output end, the second output end and the third output end; the first control unit comprises a first node and a second node, and the first node and the second node are respectively and electrically connected with the second control unit;
the first signal input end is electrically connected with the first control unit, the second signal input end is electrically connected with the second control unit, the first control unit is also electrically connected with the first output end, and the second control unit is also electrically connected with the second output end and the third output end respectively;
The first signal input terminal is used for providing a first signal to the first control unit and controlling the electric potentials of the first node and the second node in a time period, so that the second control unit outputs a signal to at least one of the second output terminal and the third output terminal through the second signal input terminal under the control of the signals of the first node and the second node; or outputting a signal to the first output terminal through the first signal input terminal and the second output terminal.
2. The switch control circuit of claim 1, wherein the first control unit comprises a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor, wherein one of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor;
the gate of the first transistor, the first pole of the first transistor, the gate of the second transistor, and the first pole of the second transistor are all connected to the first signal input terminal; the second pole of the first transistor is connected with the first end of the first capacitor, and the second end of the first capacitor is connected with the first node; a second pole of the second transistor is connected with the second node;
The first electrode of the third transistor is connected to the first node and the second node respectively, the gate of the third transistor is connected to the first end of the second capacitor, the second electrode of the third transistor is connected to the first output end, and the second end of the second capacitor is connected to the second output end.
3. The switch control circuit of claim 2, wherein the third transistor is of the same type as the first transistor.
4. The switch control circuit according to claim 2, wherein the second control unit includes a fourth transistor and a fifth transistor, wherein one of the fourth transistor and the fifth transistor is a P-type transistor, and the other is an N-type transistor;
the grid electrode of the fourth transistor is connected with the second node, the first electrode of the fourth transistor is connected with the second signal input end, and the second electrode of the fourth transistor is connected with the second output end;
and the grid electrode of the fifth transistor is connected with the first node, the first electrode of the fifth transistor is connected with the second signal input end, and the second electrode of the fifth transistor is connected with the third output end.
5. The switch control circuit of claim 4 wherein the second control unit further comprises a third capacitor having a first terminal connected to the gate of the fourth transistor and a second terminal connected to the second node.
6. The switch control circuit of claim 5 wherein the first capacitance is C01, the second capacitance is C02, and the third capacitance is C03, wherein 50f is greater than or equal to C01 and less than or equal to 800f,50f is greater than or equal to C02 and less than or equal to 800f, and 50f is greater than or equal to C03 and less than or equal to 800f.
7. The switch control circuit of claim 6 wherein C01 > C03 > C02.
8. The switch control circuit of claim 4, wherein the fourth transistor comprises a first sub-transistor and a second sub-transistor in series between the second signal input terminal and the second output terminal, the gates of the first sub-transistor and the second sub-transistor each being coupled to the second node.
9. The switch control circuit of claim 4 wherein the fourth transistor is of the same type as the second transistor and the fifth transistor is of the same type as the first transistor.
10. The switch control circuit of claim 4 wherein the first transistor, the third transistor, and the fifth transistor have the same aspect ratio, the fourth transistor has an aspect ratio that is less than the aspect ratio of the first transistor, and the second transistor has an aspect ratio that is greater than the aspect ratio of the first transistor.
11. A driving method of a switch control circuit, applied to the switch control circuit according to any one of claims 1 to 10, characterized by comprising:
in a first period, the signal of the first signal input end is a first level signal, so that the potential of the first node is a first potential, and the second signal input end is controlled to output a first data signal to the third output end;
in a second period, the signal of the first signal input end is a second level signal, so that the potential of the second node is a first potential, and the second signal input end is controlled to output a second data signal to the second output end;
and in a third period, the signal of the first signal input end is a second level signal, the signal of the second signal input end is a first level signal, and the first signal input end is controlled to output a third data signal to the first output end.
12. A display device comprising a data line and the switch control circuit of any one of claims 1 to 10, wherein the first output terminal, the second output terminal, and the third output terminal of the switch control circuit are electrically connected to the data line, respectively.
13. The display device according to claim 12, wherein the data line includes a first data line, a second data line, and a third data line, the first data line is electrically connected to the first output terminal, the second output terminal is electrically connected to the second data line, and the third output terminal is electrically connected to the third data line.
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