CN114283719A - Switch control circuit, driving method thereof and display device - Google Patents
Switch control circuit, driving method thereof and display device Download PDFInfo
- Publication number
- CN114283719A CN114283719A CN202111666877.0A CN202111666877A CN114283719A CN 114283719 A CN114283719 A CN 114283719A CN 202111666877 A CN202111666877 A CN 202111666877A CN 114283719 A CN114283719 A CN 114283719A
- Authority
- CN
- China
- Prior art keywords
- transistor
- signal
- signal input
- output
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Electronic Switches (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a switch control circuit, a driving method thereof and a display device. In a time period, the first signal input end is used for providing a first signal to the first control unit and controlling the electric potentials of the first node and the second node, so that the second control unit outputs a signal to at least one of the second output end and the third output end through the second signal input end under the control of the signals of the first node and the second node; alternatively, a signal is output to the first output terminal through the first signal input terminal. This switch control circuit only introduces two signal input parts and can realize the control to the output signal of different output, is favorable to reducing switch control circuit's signal input part's quantity, is favorable to reducing power load and loss when using with the power cooperation.
Description
Technical Field
The invention relates to the technical field of display, in particular to a switch control circuit, a driving method thereof and a display device.
Background
The Micro light-emitting diode (Micro LED), namely the light-emitting diode Micro and matrixing technology, has the advantages of good stability, service life and operation temperature, inherits the advantages of low power consumption, color saturation, high reaction speed, high contrast and the like of the LED, and has great application prospect. Displays fabricated from Micro LEDs are the mainstream direction of development for the future of display devices. In the production process of the Micro LED display, before a display panel in the Micro LED display is cut, an electrical test is performed to detect whether a short circuit exists in a scan line transmission area and a data line transmission area. During the electricity test experiment, can directly pour into voltage for display panel's scanning line transmission area and data line transmission area and test, cut off the power supply after the test is accomplished, cut display panel, encapsulate after the cutting is accomplished, finally constitute the display product.
In the test circuit in the prior art, each data line of the data line transmission area in the display panel needs to be connected with the output pins of the power supply one by one, so that each output pin of the power supply needs to be output during testing, and under the condition that the resolution of the display panel is high, more data lines of the power supply output pins need to be connected are not beneficial to production operation.
Disclosure of Invention
In view of this, the present invention provides a switch control circuit, a driving method thereof, and a display device, in which only two signal input terminals are introduced to control output signals of different output terminals, which is beneficial to reducing the number of signal input terminals of the switch control circuit, and when the switch control circuit is used in cooperation with a power supply, the switch control circuit is beneficial to reducing the operation complexity, and is also beneficial to reducing the power supply load and loss.
In a first aspect, the present invention provides a switch control circuit, comprising: the first signal input end, the second signal input end, the first control unit, the second control unit, the first output end, the second output end and the third output end; the first control unit comprises a first node and a second node, and the first node and the second node are respectively and electrically connected with the second control unit;
the first signal input end is electrically connected with the first control unit, the second signal input end is electrically connected with the second control unit, the first control unit is also electrically connected with the first output end, and the second control unit is also electrically connected with the second output end and the third output end respectively;
during a time period, the first signal input terminal is used for providing a first signal to the first control unit and controlling the potentials of the first node and the second node, so that the second control unit outputs a signal to at least one of the second output terminal and the third output terminal through the second signal input terminal under the control of the signals of the first node and the second node; or, a signal is output to the first output terminal through the first signal input terminal.
In a second aspect, the present invention further provides a driving method of a switch control circuit, which is applied to the switch control circuit provided in the first aspect of the present invention, the driving method includes:
in a first period, a signal of the first signal input end is a first level signal, so that the potential of the first node is a first potential, and the second signal input end is controlled to output a first data signal to the third output end;
in a second time interval, the signal of the first signal input end is a second level signal, the potential of the second node is made to be a first potential, and the second signal input end is controlled to output a second data signal to the second output end;
in a third time period, the signal of the first signal input end is a second level signal, the signal of the second signal input end is a first level signal, and the first signal input end is controlled to output a third data signal to the first output end.
In a third aspect, the present invention provides a display device comprising a data line and the switch control circuit of the first aspect of the present invention.
Compared with the prior art, the switch control circuit, the driving method thereof and the display device provided by the invention at least realize the following beneficial effects:
in the switch control circuit, the driving method thereof and the display device provided by the invention, the switch control circuit comprises two signal input ends, two control modules and three output ends, namely a first signal input end, a second signal input end, a first control unit, a second control unit, a first output end, a second output end and a third output end, wherein the first signal input end is electrically connected with the first control unit, and the second signal input end is electrically connected with the second control unit. When providing corresponding level signal or data signal respectively to first signal input end and second signal input end, can control first output terminal output first data signal respectively, second output terminal output second data signal and third output terminal output third data signal, so, only introduce two signal input ends and can realize the control to the output signal of different output ends in the on-off control circuit, compare with the mode that the quantity of the signal input end that contains in the on-off control circuit of prior art is the same with the quantity of data line, the quantity of the signal input end of on-off control circuit has been reduced greatly, be favorable to reducing power load and loss when using with the power cooperation. When the switch control circuit is arranged in the display device, the same output end can be connected with the data lines corresponding to the sub-pixels with the same color, and when the display device is provided with the sub-pixels with three different colors, the first output end, the second output end and the third output end are respectively connected with the data lines corresponding to the sub-pixels with different colors.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a block diagram of a switch control circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a switch control circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a switch control circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a switch control circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a switch control circuit according to an embodiment of the present invention;
fig. 6 is a flowchart illustrating a driving method of a switch control circuit according to an embodiment of the invention;
FIG. 7 is a timing diagram of the switching control circuit providing the red display signal;
FIG. 8 is a timing diagram of the switch control circuit providing the green display signal;
FIG. 9 is a timing diagram of the switching control circuit for providing the blue display signal;
FIG. 10 is a timing diagram of the switch control circuit providing the white frame display signal;
fig. 11 is a top view of a display device according to an embodiment of the invention;
FIG. 12 is a schematic diagram showing connection between data lines and a switch control circuit on a display panel of the display device;
FIG. 13 is a schematic diagram of a power module for testing data lines of a display device;
fig. 14 is a schematic diagram illustrating another structure of testing a data line on a display device using a power module.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Fig. 1 is a block diagram of a switch control circuit according to an embodiment of the present invention, and referring to fig. 1, the switch control circuit according to the embodiment of the present invention includes: a first signal input terminal D1, a second signal input terminal D2, a first control unit 10, a second control unit 20, a first output terminal OUT1, a second output terminal OUT2 and a third output terminal OUT 3; the first control unit 10 includes a first node N1 and a second node N2, the first node N1 and the second node N2 being electrically connected to the second control unit 20, respectively;
the first signal input end D1 is electrically connected to the first control unit 10, the second signal input end D2 is electrically connected to the second control unit 20, the first control unit 10 is further electrically connected to the first output end OUT1, and the second control unit 20 is further electrically connected to the second output end OUT2 and the third output end OUT3, respectively;
during a period of time, the first signal input terminal D1 is used to provide a first signal to the first control unit 10, control the potentials of the first node N1 and the second node N2 such that the second control unit 20 outputs a signal to at least one of the second output terminal OUT2 and the third output terminal OUT3 through the second signal input terminal D2 under the control of the signals of the first node N1 and the second node N2; alternatively, a signal is output to the first output terminal OUT1 through the first signal input terminal D1.
The switch control circuit provided by the invention comprises two signal input ends, two control modules and three output ends, namely a first signal input end D1 and a second signal input end D2, a first control unit 10 and a second control unit 20, and a first output end OUT1, a second output end OUT2 and a third output end OUT3, wherein the first signal input end D1 is electrically connected with the first control unit 10, and the second signal input end D2 is electrically connected with the second control unit 20. When corresponding level signals or data signals are respectively provided for the first signal input end D1 and the second signal input end D2, the potentials of the first node N1 and the second node N2 can be controlled, and further the first output end OUT1 is controlled to output a first data signal, the second output end OUT2 is controlled to output a second data signal, and the third output end OUT3 is controlled to output a third data signal. When the switch control circuit is arranged in the display device, the same output end can be connected with the data lines corresponding to the sub-pixels with the same color, and when three sub-pixels with different colors are arranged in the display device, the first output end OUT1, the second output end OUT2 and the third output end OUT3 are respectively connected with the data lines corresponding to the sub-pixels with different colors, so that the test of the sub-pixels connected with all the data lines in the whole display device can be realized through one switch control module, and the circuit complexity of the display device is greatly simplified.
Fig. 1 only illustrates a block structure of the switch control circuit, and a specific structure of the first control unit 10 and the second control unit 20 will be described in the following embodiments.
Fig. 2 is a schematic diagram of a structure of a switch control circuit according to an embodiment of the present invention, which illustrates a circuit configuration of the first control unit 10 in the switch control circuit.
Referring to fig. 2, in an alternative embodiment of the invention, the first control unit 10 includes a first transistor M1, a second transistor M2, a third transistor M3, a first capacitor C1 and a second capacitor C2, wherein one of the first transistor M1 and the second transistor M2 is a P-type transistor, and the other is an N-type transistor;
the gate of the first transistor M1, the first pole of the first transistor M1, the gate of the second transistor M2, and the first pole of the second transistor M2 are all connected to a first signal input terminal D1; a second pole of the first transistor M1 is connected to a first terminal of a first capacitor C1, and a second terminal of the first capacitor C1 is connected to a first node N1; a second pole of the second transistor M2 is connected to the second node N2;
a first pole of the third transistor M3 is connected to the first node N1 and the second node N2, respectively, a gate of the third transistor M3 is connected to a first end of the second capacitor C2, a second pole of the third transistor M3 is connected to the first output terminal OUT1, and a second end of the second capacitor C2 is connected to the second output terminal OUT 2.
In the switch control circuit provided in the embodiment of the present invention, the types of the first transistor M1 and the second transistor M2 introduced in the first control unit 10 are different, and fig. 2 illustrates that the first transistor M1 is an N-type transistor and the second transistor M2 is a P-type transistor, in some other embodiments of the present invention, the first transistor M1 may also be embodied as a P-type transistor, and the second transistor M2 may also be embodied as an N-type transistor. When the transistor is a P-type transistor, the gate thereof is turned on under the control of a low level signal and is turned off under the control of a high level signal. When the transistor is an N-type transistor, its gate is turned on under the control of a high level signal and turned off under the control of a low level signal. A scheme in which the first transistor M1 is an N-type transistor and the second transistor M2 is a P-type transistor will be described below with reference to fig. 2.
When the signal of the first signal input terminal D1 is a high level signal, the first transistor M1 is turned on, the second transistor M2 is turned off, and since the first capacitor C1 is electrically connected to the second pole of the first transistor M1, when the first transistor M1 is turned on, the high level signal of the first signal input terminal D1 charges the first capacitor C1, raises the potential of the first node N1, changes the first node N1 to a high potential, and transmits the high potential to the second control unit 20. When the signal at the first signal input terminal D1 is a low-level signal, the first transistor M1 is turned off, the second transistor M2 is turned on, and the low-level signal at the first signal input terminal D1 is transmitted to the second node N2 through the turned-on second transistor M2, and the signal at the second node N2 is changed to a low-level signal, and then transmitted to the second control unit 20.
The embodiment shown in fig. 2 is illustrated by taking the third transistor M3 as an N-type transistor, and in some other embodiments of the present invention, the third transistor M3 may also be embodied as a P-type transistor. When the third transistor M3 is an N-type transistor, it is turned on by a high-level signal and turned off by a low-level signal. The gate of the third transistor M3 is connected to the second capacitor C2, the second capacitor C2 is further connected to the second output terminal OUT2, and when the signal output from the second output terminal OUT2 is a high-level signal, the high-level signal will be coupled to the gate of the third transistor M3 through the second capacitor C2, so as to turn on the third transistor M3. When the third transistor M3 and the second transistor M2 are both turned on, a data signal is input at the first signal input terminal D1, and the data signal may be transmitted to the first output terminal OUT1 through the second transistor M2 and the third transistor M3, thereby achieving an output of the data signal to the first output terminal OUT 1.
With continued reference to fig. 2, in an alternative embodiment of the present invention, the third transistor M3 is of the same type as the first transistor M1.
The third transistor M3 is of the same type as the first transistor M1, meaning that the third transistor M3 and the first transistor M1 are both P-type transistors or the third transistor M3 and the first transistor M1 are both N-type transistors. The embodiment shown in fig. 2 only exemplifies that the third transistor M3 and the first transistor M1 are both N-type transistors, and in some other embodiments of the present invention, the third transistor M3 and the first transistor M1 may both be embodied as P-type transistors.
As can be seen from fig. 2, when the third transistor M3 is turned on, it is intended to output a data signal to the first output terminal OUT1 through the first signal input terminal D1. At this time, the second transistor M2 is required to be turned on, and the second output terminal OUT2 is required to be able to input a high level signal to the gate of the third transistor M3, and the high level signal of the second output terminal OUT2 is provided from the second signal input terminal D2. The low level signal inputted from the first signal input terminal D1 turns on the second transistor M2 and turns off the first transistor M1. When the second transistor M2 and the third transistor M3 are simultaneously turned on, a data signal may be input through the first signal input terminal D1, and the data signal is transmitted to the first output terminal OUT1 through the second transistor M2 and the third transistor M3.
Fig. 3 is a schematic diagram showing another structure of the switch control circuit according to the embodiment of the present invention, which illustrates a circuit configuration of the second control unit 20 in the switch control circuit.
Referring to fig. 3, in an alternative embodiment of the present invention, the second control unit 20 includes a fourth transistor M4 and a fifth transistor M5, wherein one of the fourth transistor M4 and the fifth transistor M5 is a P-type transistor and the other is an N-type transistor;
the gate of the fourth transistor M4 is connected to the second node N2, the first pole is connected to the second signal input terminal D2, and the second pole is connected to the second output terminal OUT 2;
the gate of the fifth transistor M5 is connected to the first node N1, the first pole is connected to the second signal input terminal D2, and the second pole is connected to the third output terminal OUT 3.
Fig. 3 shows a specific circuit configuration of the second control unit 20, and this embodiment is described by taking the fourth transistor M4 as a P-type transistor and the fifth transistor M5 as an N-type transistor as an example, in some other embodiments of the present invention, the fourth transistor M4 may also be embodied as an N-type transistor, and the fifth transistor M5 may also be embodied as a P-type transistor.
Specifically, with continued reference to fig. 3, this embodiment will be described by taking as an example that the fourth transistor M4 and the second transistor M2 are both P-type transistors, and the fifth transistor M5 and the first transistor M1 are both N-type transistors.
When the first signal input terminal D1 is a high-level signal, the first transistor M1 is turned on, the second transistor M2 is turned off, and the high-level signal of the first signal input terminal D1 charges the first capacitor C1, so that the high-level signal is coupled to the gate of the fifth transistor M5, and the fifth transistor M5 is turned on. When a data signal is input to the second signal output terminal, the data signal can be transmitted to the third output terminal OUT3 through the fifth transistor M5, and the data signal output from the second signal input terminal D2 can be set as desired.
When the first signal input terminal D1 is a low-level signal, the first transistor M1 is turned off, the second transistor M2 is turned on, and a low-level signal at the first signal input terminal D1 is coupled to the gate of the fourth transistor M4 to control the fourth transistor M4 to be turned on. When a data signal is input to the second signal input terminal D2, the data signal may be transmitted to the second output terminal OUT2 through the fourth transistor M4, and the data signal output from the second signal terminal may be set as desired.
When the first signal input terminal D1 is a low-level signal and the second signal input terminal D2 is a high-level signal, the first transistor M1 is turned off, the second transistor M2 is turned on, the low-level signal of the first signal input terminal D1 is coupled to the gate of the fourth transistor M4, so that the fourth transistor M4 is turned on, and the high-level signal of the second signal input terminal D2 is coupled to the gate of the third transistor M3 through the second capacitor C2, so that the third transistor M3 is turned on. When a data signal is input to the first signal input terminal D1, the data signal may be transmitted to the first output terminal OUT1 through the second transistor M2 and the third transistor M3, and the data signal output from the first output terminal OUT1 may be set as desired.
It can be seen that, through the signals of controlling the first signal input end D1 and the second signal input end D2, the output of the signals of the first output end OUT1, the second output end OUT2 and the third output end OUT3 can be respectively realized, that is, the output of different signals can be realized only by introducing two signal input ends into the switch control circuit, the number of the signal input ends of the switch control circuit is greatly reduced, and when the switch control circuit is used in cooperation with a power supply for testing, the reduction of power supply load and loss is facilitated.
Fig. 4 is a schematic diagram showing another structure of the switch control circuit according to the embodiment of the present invention, which illustrates a circuit configuration of the second control unit 20 in the switch control circuit.
Referring to fig. 4, in an alternative embodiment of the invention, the second control unit 20 further includes a third capacitor C3, a first terminal of the third capacitor C3 is connected to the gate of the fourth transistor M4, and a second terminal thereof is connected to the second node N2.
Specifically, in the embodiment of the present invention, a third capacitor C3 is introduced between the gate of the fourth transistor M4 and the second node N2, when the signal of the first signal input terminal D1 is a low-level signal, the second transistor M2 is turned on, the low-level signal of the first signal input terminal D1 can be coupled to the third capacitor C3 through the second transistor M2, the potential of the end of the third capacitor C3 connected to the second node N2 is pulled low, and the potential of the other end of the third capacitor C3 is also pulled low, so that the gate of the fourth transistor M4 is a low-level signal, and the fourth transistor M4 is controlled to be turned on. When the fourth transistor M4 is turned on, the data signal can be output to the second output terminal OUT2 through the second signal input terminal D2, and a high-level signal can also be output through the second signal input terminal D2, so that the high-level signal is coupled to the gate of the third transistor M3 through the second capacitor C2, and the third transistor M3 is controlled to be turned on. When both the third transistor M3 and the second transistor M2 are turned on, the first output terminal OUT1 may output a data signal to the first output terminal OUT1 through the second transistor M2 and the third transistor M3.
In the switch control circuit provided by the invention, the first capacitor C1, the second capacitor C2 and the third capacitor C3 are introduced, and the capacity of the capacitors influences the opening state of the transistor connected with the capacitors. For example, the first capacitor C1 is connected to the gate of the fifth transistor M5, the high-level signal is coupled to the fifth transistor M5 through the first capacitor C1 to control the fifth transistor M5 to be turned on, the potential of the gate of the fifth transistor M5 gradually decreases with the discharge of the first capacitor C1, the fifth transistor M5 changes from the fully-on state to the half-on state, and the value of the data signal transmitted to the third output terminal OUT3 through the fifth transistor M5 changes, i.e., the value of the data signal output to the third output terminal OUT3 is different when the fifth transistor M5 is in different on states. Similarly, when the second capacitor C2 is connected to the gate of the third transistor M3, and the second capacitor C2 couples a high level to the gate of the third transistor M3, the third transistor M3 is turned on, and the potential of the gate of the third transistor M3 gradually decreases with the discharge of the second capacitor C2, so that the third transistor M3 is turned from the fully open state to the half open state, and the value of the data signal transmitted to the first output terminal OUT1 through the third transistor M3 changes, that is, the value of the data signal output to the first output terminal OUT1 is different in different on states of the second capacitor C2. Similarly, when the third capacitor C3 is connected to the gate of the fourth transistor M4, when a low-level signal is coupled to the gate of the fourth transistor M4 through the third capacitor C3, the fourth transistor M4 is turned on, and as the potential of the end of the third capacitor C3 connected to the third transistor M3 increases, the fourth transistor M4 will change from a fully open state to a half open state, and the value of the data signal transmitted to the second output terminal OUT2 through the fourth transistor M4 will also change, that is, the value of the data signal output to the second output terminal OUT2 is different in different on states of the third capacitor C3.
In an optional embodiment of the invention, the capacitance value of the first capacitor C1 is C01, the capacitance value of the second capacitor C2 is C02, and the capacitance value of the third capacitor C3 is C03, wherein 50f ≦ C01 ≦ 800f, 50f ≦ C02 ≦ 800f, and 50f ≦ C03 ≦ 800 f.
Specifically, the capacitance values of the three capacitors in the switch control circuit are set to be between 50f and 800f, so that the control requirement of each capacitor on the on state of the gate of the corresponding transistor can be met. Optionally, the capacitance of each capacitor may also be set between 100f and 600f, or between 60f and 700f, and so on.
In an alternative embodiment of the invention, C01 > C03 > C02. The capacitance values of the three capacitors are set to be different, the time for maintaining the on state of the transistor connected with the three capacitors is different, and the values of the data signals input to the three output ends are different. When the switch control circuit in the embodiment of the invention is applied to a display device, three output terminals of the switch control circuit may be electrically connected to data lines corresponding to different sub-pixels, for example, the first output terminal OUT1 is electrically connected to the data line corresponding to the sub-pixel of the first color, the second output terminal OUT2 is electrically connected to the data line corresponding to the sub-pixel of the second color, and the third output terminal OUT3 is electrically connected to the data line corresponding to the sub-pixel of the third color. The invention can control the three output ends to output different data signals by setting the three capacitors with different capacitance values, thereby being beneficial to simplifying the structure of the switch control circuit. Alternatively, C01 ═ 800f, C03 ═ 200f, and C02 ═ 50 f.
Fig. 5 is a schematic diagram showing another structure of the switch control circuit according to the embodiment of the present invention, which illustrates a circuit configuration of the second control unit 20 in the switch control circuit.
In an alternative embodiment of the present invention, the fourth transistor M4 includes a first sub-transistor M41 and a second sub-transistor M42 connected in series between the second signal input terminal D2 and the second output terminal OUT2, and the gates M42 of the first and second sub-transistors M41 and M42 are both coupled to the second node N2. Specifically, in the switch control circuit provided in the embodiment of the present invention, the fourth transistor M4 in the second control unit 20 is configured as a dual-gate structure, that is, the dual-gate structure includes the first sub-transistor M41 and the second sub-transistor M42 connected in series, and the design of the dual-gate structure is adopted, which is beneficial to reducing the leakage current of the fourth transistor M4.
With continued reference to fig. 4 and 5, in an alternative embodiment of the present invention, the fourth transistor M4 is of the same type as the second transistor M2 and the fifth transistor M5 is of the same type as the first transistor M1.
Specifically, when the fourth transistor M4 and the second transistor M2 are both P-type transistors or both N-type transistors, taking the embodiment shown in fig. 5 as an example, the fourth transistor M4 and the second transistor M2 are both P-type transistors, and when a low-level signal is input to the first signal input terminal D1, the low-level signal can control the second transistor M2 to turn on, and at the same time, the low-level signal is coupled to the gate of the fourth transistor M4 through the third capacitor C3, so that the fourth transistor M4 is turned on, and therefore, an extra control signal terminal does not need to be introduced to separately control the turn-on and turn-off of the fourth transistor M4, which is beneficial to reducing the number of signal terminals included in the switch control circuit. Likewise, the embodiment of the invention may set both the fifth transistor M5 and the first transistor M1 as N-type transistors or both as P-type transistors as long as they are different from the second transistor M2 and the fourth transistor M4. Taking fig. 5 as an example, the fifth transistor M5 and the first transistor M1 are both N-type transistors, when a high level signal is input at the first signal input terminal D1, the first transistor M1 is turned on, and the high level signal at the first signal input terminal D1 is coupled to the gate of the fifth transistor M5 through the first capacitor C1, so that the fifth transistor M5 is also turned on, and therefore, an extra control signal terminal is not required to be introduced to separately control the on and off of the fifth transistor M5, which is beneficial to reducing the number of signal terminals included in the switch control circuit. Therefore, the second transistor M2 and the fourth transistor M4 are set to be the same type, and the first transistor M1 and the fifth transistor M5 are set to be the same type, so that the number of signal terminals included in the switch control circuit is favorably reduced, the signal output of three output ends can be realized only by introducing two signal input ends, the structure of the switch control circuit is simplified, and when the detection circuit is applied, the power supply load and the loss are favorably reduced.
With continued reference to fig. 5, in an alternative embodiment of the present invention, the width-to-length ratios of the first transistor M1, the third transistor M3, and the fifth transistor M5 are the same, the width-to-length ratio of the fourth transistor M4 is less than the width-to-length ratio of the first transistor M1, and the width-to-length ratio of the second transistor M2 is greater than the width-to-length ratio of the first transistor M1.
When the width-to-length ratios of the first transistor M1, the third transistor M3, and the fifth transistor M5 are set to be the same, the transistors may be formed with the same width-to-length ratio, which is advantageous to simplify the difficulty of manufacturing different transistors in the switch control circuit. Since the first pole of the third transistor M3 and the gate of the fourth transistor M4 are both connected to the second node N2, when the width-to-length ratio of the fourth transistor M4 is set to be minimum, the fourth transistor M4 is made more stable, and the influence of the fourth transistor M4 on the fifth transistor M5 is effectively avoided. Alternatively, the width-to-length ratio of the first transistor M1, the third transistor M3, and the fifth transistor M5 is 6/4, the width-to-length ratio of the fourth transistor M4 is 3/19, and the width-to-length ratio of the second transistor M2 is 8/4.
Based on the same inventive concept, the present invention further provides a driving method of a switch control circuit, and fig. 6 is a flowchart of the driving method of the switch control circuit according to the embodiment of the present invention, where the driving method is applied to the switch control circuit according to any of the above embodiments of the present invention, and the driving method includes:
in the first period, the signal at the first signal input terminal D1 is a first level signal, the potential of the first node N1 is a first potential, and the second signal input terminal D2 is controlled to output a first data signal to the third output terminal OUT 3;
in the second period, the signal at the first signal input terminal D1 is a second level signal, the potential of the second node N2 is a first potential, and the second signal input terminal D2 is controlled to output a second data signal to the second output terminal OUT 2;
in the third period, the signal at the first signal input terminal D1 is the second level signal, the signal at the second signal input terminal D2 is the first level signal, and the first signal input terminal D1 is controlled to output the third data signal to the first output terminal OUT 1.
It should be noted that, although the working processes of the first time period, the second time period and the third time period are respectively described in the above driving method, the order of the first time period, the second time period and the third time period is not limited, in some other embodiments of the present invention, the first time period, the second time period and the third time period may be executed according to any order, and the present invention is not specifically limited to this.
When the switch control circuit according to the embodiment of the present invention is applied to a display device, the switch control circuit can utilize three output terminals, namely a red image signal, a green image signal, a blue image signal and a white image signal, and the following description will describe the operation process of the driving method of the switch control circuit according to the present invention with reference to specific timing sequences. Fig. 7 is a timing chart of the switching control circuit for supplying a red picture display signal, fig. 8 is a timing chart of the switching control circuit for supplying a green picture display signal, fig. 9 is a timing chart of the switching control circuit for supplying a blue picture display signal, and fig. 10 is a timing chart of the switching control circuit for supplying a white picture display signal.
Referring to fig. 5 to 7, when a high-level signal (e.g., 8V) is inputted from the first signal input terminal D1, the first transistor M1 is turned on, and the high-level signal at the first signal input terminal D1 is coupled to the fifth transistor M5 through the first capacitor C1, so that the fifth transistor M5 is turned on; the second signal input terminal D2 provides the red picture display signal (data R) to the third output terminal OUT3, thereby enabling output of the red picture display signal.
Referring to fig. 5, fig. 6 and fig. 8, when the first signal input terminal D1 inputs a low-level signal, the second transistor M2 is turned on, and the low-level signal at the first signal input terminal D1 is coupled to the fourth transistor M4 through the third capacitor C3, so that the fourth transistor M4 is turned on; the second signal input terminal D2 inputs the green picture display signal to the second output terminal OUT2, thereby implementing the output of the green picture display signal.
Referring to fig. 5, fig. 6 and fig. 9, when the first signal input terminal D1 inputs a low-level signal, the second transistor M2 is turned on, and the low-level signal at the first signal input terminal D1 is coupled to the fourth transistor M4 through the third capacitor C3, so that the fourth transistor M4 is turned on; the second signal input terminal D2 inputs a high level signal (e.g., 8V) coupled to the gate of the third transistor M3 through the fourth transistor M4 and the second capacitor C2 to turn on the third transistor M3, and at this time, a blue picture display signal (data B) is input to the first output terminal OUT1 through the first signal input terminal D1, thereby realizing output of the blue picture display signal.
Referring to fig. 5, fig. 6 and fig. 10, when the first signal input terminal D1 inputs a high-level signal (8V), the first transistor M1 is turned on, the high-level signal is coupled to the gate of the fifth transistor M5 through the first capacitor C1, and the fifth transistor M5 is turned on; when the first signal input terminal D1 receives a low-level signal (8V), the second transistor M2 is turned on, and the low-level signal is coupled to the gate of the fourth transistor M4 through the third capacitor C3 to turn on the fourth transistor M4, and at this time, the high-level signal at the second signal input terminal D2 is coupled to the third transistor M3 through the second capacitor C2 to turn on the third transistor M3, so that the transistors in the switch control circuit are turned on. The white picture display signal is input to the output terminal through the second signal input terminal D2, and the output of the white picture display signal is realized.
Based on the same inventive concept, the present invention further provides a display device, fig. 11 is a top view of the display device according to the embodiment of the present invention, fig. 12 is a schematic connection diagram of a data line and a switch control circuit on a display panel of the display device, please refer to fig. 11 and fig. 12, the display device according to the embodiment of the present invention includes the data line and the switch control circuit according to any one of the above embodiments of the present invention, wherein a first output terminal, a second output terminal and a third output terminal of the switch control circuit are respectively electrically connected to the data line.
When the switch control circuit is applied to a display device, the switch control circuit is optionally integrated on a display panel in the display device, and an output terminal of the switch control circuit is used for electrically connecting with a data line on the display panel. In the production process of the display device, signals can be input to the first signal input end D1 and the second signal input end D2 of the switch control circuit by matching with an external detection power supply, so that the detection function of each data line on the display panel is realized. The detection of each data line can be realized by only introducing one switch control circuit in the display device, and the switch control circuit is only provided with two signal input ends, so that the power supply load and the loss can be reduced when the switch control circuit is matched with a power supply for testing.
Fig. 13 is a schematic diagram showing a structure of testing a data line on a display device by using a power module, fig. 14 is a schematic diagram showing another structure of testing a data line on a display device by using a power module, and in the implementation shown in fig. 13, one display device corresponds to one switch control circuit and is tested by using one power module. In the embodiment shown in fig. 14, one display device corresponds to 4 switch control circuits, and each switch control circuit corresponds to one power module, so that partition detection of the display device can be realized. It is to be understood that fig. 13 and 14 only show one connection schematic of the switch control circuit to the display area AA on the display panel, and do not represent an actual structure.
Referring to fig. 12, in an alternative embodiment of the present invention, the data lines include a first data line, a second data line and a third data line, the first data line is electrically connected to the first output terminal OUT1, the second output terminal OUT2 is electrically connected to the second data line, and the third output terminal OUT3 is electrically connected to the third data line.
Optionally, the display panel includes three data lines, wherein a first data line may provide a display signal for a red sub-pixel on the display panel, a second data line may provide a display signal for a green sub-pixel on the display panel, and a third data line may provide a display signal for a blue sub-pixel on the display panel. In an actual display device, each of the first data lines is connected to the third output terminal OUT3 of the switch control circuit, each of the second data lines is connected to the second output terminal OUT2 of the switch control circuit, and each of the third data lines is connected to the third output terminal OUT3 of the switch control circuit. When the display condition of the red picture needs to be detected, a red picture display signal is input to each first data line through the third output end OUT 3; when the display condition of the green picture needs to be detected, a green picture display signal is input to each second data line through a second output end OUT 2; when it is necessary to detect the display of the blue screen, the blue screen display signal may be input to each of the third data lines through the third output terminal OUT 3.
Therefore, the display device is provided with the switch control circuit, and the detection of each data line in the display panel can be realized by introducing the two signal input ends and the three signal output ends into the switch control circuit, so that the structural complexity of the display device is greatly simplified.
It should be noted that, the embodiment of the display device provided by the present invention can refer to the embodiment of the display module in the present invention, and repeated descriptions are omitted. The display device provided by the embodiment of the invention can be embodied as any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In summary, the switch control circuit, the driving method thereof and the display device provided by the invention at least achieve the following beneficial effects:
in the switch control circuit, the driving method thereof and the display device provided by the invention, the switch control circuit comprises two signal input ends, two control modules and three output ends, namely a first signal input end, a second signal input end, a first control unit, a second control unit, a first output end, a second output end and a third output end, wherein the first signal input end is electrically connected with the first control unit, and the second signal input end is electrically connected with the second control unit. When providing corresponding level signal or data signal respectively to first signal input end and second signal input end, can control first output terminal output first data signal respectively, second output terminal output second data signal and third output terminal output third data signal, so, only introduce two signal input ends and can realize the control to the output signal of different output ends in the on-off control circuit, compare with the mode that the quantity of the signal input end that contains in the on-off control circuit of prior art is the same with the quantity of data line, the quantity of the signal input end of on-off control circuit has been reduced greatly, be favorable to reducing power load and loss when using with the power cooperation. When the switch control circuit is arranged in the display device, the same output end can be connected with the data lines corresponding to the sub-pixels with the same color, and when the display device is provided with the sub-pixels with three different colors, the first output end, the second output end and the third output end are respectively connected with the data lines corresponding to the sub-pixels with different colors.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (13)
1. A switch control circuit, comprising: the first signal input end, the second signal input end, the first control unit, the second control unit, the first output end, the second output end and the third output end; the first control unit comprises a first node and a second node, and the first node and the second node are respectively and electrically connected with the second control unit;
the first signal input end is electrically connected with the first control unit, the second signal input end is electrically connected with the second control unit, the first control unit is also electrically connected with the first output end, and the second control unit is also electrically connected with the second output end and the third output end respectively;
during a time period, the first signal input terminal is used for providing a first signal to the first control unit and controlling the potentials of the first node and the second node, so that the second control unit outputs a signal to at least one of the second output terminal and the third output terminal through the second signal input terminal under the control of the signals of the first node and the second node; or, a signal is output to the first output terminal through the first signal input terminal.
2. The switch control circuit according to claim 1, wherein the first control unit comprises a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor, wherein one of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor;
the gate of the first transistor, the first pole of the first transistor, the gate of the second transistor, and the first pole of the second transistor are all connected to the first signal input terminal; the second pole of the first transistor is connected with the first end of the first capacitor, and the second end of the first capacitor is connected with the first node; a second pole of the second transistor is connected to the second node;
a first pole of the third transistor is connected to the first node and the second node, a gate of the third transistor is connected to a first end of the second capacitor, a second pole of the third transistor is connected to the first output terminal, and a second end of the second capacitor is connected to the second output terminal.
3. The switch control circuit of claim 2, wherein the third transistor is of the same type as the first transistor.
4. The switch control circuit according to claim 2, wherein the second control unit comprises a fourth transistor and a fifth transistor, wherein one of the fourth transistor and the fifth transistor is a P-type transistor, and the other is an N-type transistor;
a gate of the fourth transistor is connected to the second node, a first pole of the fourth transistor is connected to the second signal input end, and a second pole of the fourth transistor is connected to the second output end;
and the grid electrode of the fifth transistor is connected with the first node, the first pole of the fifth transistor is connected with the second signal input end, and the second pole of the fifth transistor is connected with the third output end.
5. The switch control circuit according to claim 4, wherein the second control unit further comprises a third capacitor, a first terminal of the third capacitor is connected to the gate of the fourth transistor, and a second terminal of the third capacitor is connected to the second node.
6. The switch control circuit according to claim 5, wherein the capacitance of the first capacitor is C01, the capacitance of the second capacitor is C02, and the capacitance of the third capacitor is C03, wherein 50f ≦ C01 ≦ 800f, 50f ≦ C02 ≦ 800f, and 50f ≦ C03 ≦ 800 f.
7. The switch control circuit of claim 6, wherein C01 > C03 > C02.
8. The switch control circuit of claim 4, wherein the fourth transistor comprises a first sub-transistor and a second sub-transistor connected in series between the second signal input terminal and the second output terminal, and wherein gates of the first sub-transistor and the second sub-transistor are both coupled to the second node.
9. The switch control circuit of claim 4, wherein the fourth transistor is of the same type as the second transistor, and wherein the fifth transistor is of the same type as the first transistor.
10. The switch control circuit according to claim 4, wherein the width-to-length ratios of the first transistor, the third transistor, and the fifth transistor are the same, the width-to-length ratio of the fourth transistor is smaller than the width-to-length ratio of the first transistor, and the width-to-length ratio of the second transistor is larger than the width-to-length ratio of the first transistor.
11. A driving method of a switching control circuit applied to the switching control circuit according to any one of claims 1 to 10, the driving method comprising:
in a first period, a signal of the first signal input end is a first level signal, so that the potential of the first node is a first potential, and the second signal input end is controlled to output a first data signal to the third output end;
in a second time interval, the signal of the first signal input end is a second level signal, the potential of the second node is made to be a first potential, and the second signal input end is controlled to output a second data signal to the second output end;
in a third time period, the signal of the first signal input end is a second level signal, the signal of the second signal input end is a first level signal, and the first signal input end is controlled to output a third data signal to the first output end.
12. A display device comprising a data line and the switch control circuit according to any one of claims 1 to 10, wherein the first output terminal, the second output terminal, and the third output terminal of the switch control circuit are electrically connected to the data line, respectively.
13. The display device according to claim 12, wherein the data line includes a first data line, a second data line, and a third data line, wherein the first data line is electrically connected to the first output terminal, wherein the second output terminal is electrically connected to the second data line, and wherein the third output terminal is electrically connected to the third data line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111666877.0A CN114283719B (en) | 2021-12-31 | 2021-12-31 | Switch control circuit, driving method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111666877.0A CN114283719B (en) | 2021-12-31 | 2021-12-31 | Switch control circuit, driving method thereof and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114283719A true CN114283719A (en) | 2022-04-05 |
| CN114283719B CN114283719B (en) | 2023-07-14 |
Family
ID=80879311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111666877.0A Active CN114283719B (en) | 2021-12-31 | 2021-12-31 | Switch control circuit, driving method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114283719B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114882844A (en) * | 2022-05-18 | 2022-08-09 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060244710A1 (en) * | 2005-04-27 | 2006-11-02 | Nec Corporation | Active matrix type display device and driving method thereof |
| CN102436789A (en) * | 2011-11-18 | 2012-05-02 | 友达光电股份有限公司 | Display panel and method of driving the same |
| CN205282051U (en) * | 2015-12-24 | 2016-06-01 | 厦门天马微电子有限公司 | Drive unit , drive circuit , display panel and display device |
| KR20160094556A (en) * | 2015-01-30 | 2016-08-10 | 삼성디스플레이 주식회사 | Inspecting appratus for display panel and display apparatus having the same |
| CN109741703A (en) * | 2019-03-06 | 2019-05-10 | 京东方科技集团股份有限公司 | Clock control circuit and its control method, display panel and test device |
| CN110178175A (en) * | 2019-04-08 | 2019-08-27 | 京东方科技集团股份有限公司 | Display panel and its driving method, display device |
| CN112201198A (en) * | 2020-10-21 | 2021-01-08 | 合肥京东方卓印科技有限公司 | Multi-path selection circuit, multi-path selector, driving method, display panel and device |
| US20210225222A1 (en) * | 2020-01-22 | 2021-07-22 | Samsung Display Co., Ltd. | Display panel inspecting apparatus and display apparatus having the same |
-
2021
- 2021-12-31 CN CN202111666877.0A patent/CN114283719B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060244710A1 (en) * | 2005-04-27 | 2006-11-02 | Nec Corporation | Active matrix type display device and driving method thereof |
| CN102436789A (en) * | 2011-11-18 | 2012-05-02 | 友达光电股份有限公司 | Display panel and method of driving the same |
| KR20160094556A (en) * | 2015-01-30 | 2016-08-10 | 삼성디스플레이 주식회사 | Inspecting appratus for display panel and display apparatus having the same |
| CN205282051U (en) * | 2015-12-24 | 2016-06-01 | 厦门天马微电子有限公司 | Drive unit , drive circuit , display panel and display device |
| CN109741703A (en) * | 2019-03-06 | 2019-05-10 | 京东方科技集团股份有限公司 | Clock control circuit and its control method, display panel and test device |
| CN110178175A (en) * | 2019-04-08 | 2019-08-27 | 京东方科技集团股份有限公司 | Display panel and its driving method, display device |
| US20210225222A1 (en) * | 2020-01-22 | 2021-07-22 | Samsung Display Co., Ltd. | Display panel inspecting apparatus and display apparatus having the same |
| CN112201198A (en) * | 2020-10-21 | 2021-01-08 | 合肥京东方卓印科技有限公司 | Multi-path selection circuit, multi-path selector, driving method, display panel and device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114882844A (en) * | 2022-05-18 | 2022-08-09 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114283719B (en) | 2023-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10043429B2 (en) | AMOLED panel test circuit | |
| CN100468510C (en) | Display device and driving device | |
| CN107154234B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN1744440B (en) | Level conversion circuit, power supply voltage generation circuit, shift circuit, shift register circuit, and display apparatus | |
| CN104217680B (en) | Common electric voltage compensating circuit, its compensation method, array base palte and display unit | |
| CN103106869B (en) | Level shift circuit, scanning circuit, display device and electronic equipment | |
| CN104637430B (en) | Gate driving circuit and display device | |
| CN110737140B (en) | Display panel, control method thereof and display device | |
| CN109243351A (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN101587688B (en) | Power sequence control circuit, grid driver and liquid crystal display panel applied by power sequence control circuit | |
| CN108447448A (en) | A kind of scan drive circuit, scanner driver and display device | |
| CN114283719B (en) | Switch control circuit, driving method thereof and display device | |
| CN110322851A (en) | A kind of scan drive circuit and display panel | |
| CN113963652B (en) | Display panel and driving method thereof | |
| CN108877646B (en) | Display circuit and display | |
| CN107452349B (en) | Drive circuit and liquid crystal display device | |
| CN107507565B (en) | Scanning signal generation method and device, display device | |
| CN100578583C (en) | Multi-mode switch for plasma display panel | |
| CN103325346A (en) | Driving control method and correlative source electrode driver | |
| CN110322828B (en) | Pixel driving circuit, driving method thereof and display device | |
| CN111739476B (en) | Shift register and display panel | |
| CN214226480U (en) | Circuit for improving driving current of display screen | |
| CN101419345B (en) | Display driver and built-in test circuit thereof | |
| CN107978278A (en) | Scanning circuit, organic light-emitting display device and its driving method | |
| CN113035117A (en) | Array substrate, driving method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |