CN1744440B - Level conversion circuit, power supply voltage generation circuit, shift circuit, shift register circuit, and display apparatus - Google Patents
Level conversion circuit, power supply voltage generation circuit, shift circuit, shift register circuit, and display apparatus Download PDFInfo
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- CN1744440B CN1744440B CN 200510106735 CN200510106735A CN1744440B CN 1744440 B CN1744440 B CN 1744440B CN 200510106735 CN200510106735 CN 200510106735 CN 200510106735 A CN200510106735 A CN 200510106735A CN 1744440 B CN1744440 B CN 1744440B
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Abstract
The present invention provides a level conversion circuit including first and second transistors, a clock terminal, first switch means, second switch means, and a capacitance element. The first and second transistors are of the opposite conduction types to each other connected in series between a first power supply potential and a second power supply potential. The clock terminal is inputted a clock signal. The first switch means is connected between the clock terminal and the gate of the first transistor and has an on state when a circuit operation control signal is in an active state. The second switch means is connected between the second power supply potential and the gate of the second transistor and has an off state when the circuit operation control signal is in an active state. The capacitance element is connected between the clock terminal and the gate of the second transistor.
Description
Technical field
The present invention relates to a kind of level shifting circuit (level shift circuit), supply voltage generation circuit, shift circuit, shift register and display device, and relate in particular to the level shifting circuit that is formed on the insulating circuit board, the supply voltage generation circuit that adopts this level shifting circuit formation and the display device of incorporating this supply voltage generation circuit therein into.
Background technology
A kind of current mirror type level shifting circuit that adopts current mirror circuit to form is known in the prior art.For example, disclosed a kind of in this current mirror type level shifting circuit at the open No.2003-347926 (hereinafter being called patent documentation 1) of Japan Patent.
Figure 76 illustrates the embodiment of a kind of current mirror type level shifting circuit structure of the prior art.With reference to Figure 76, shown this current mirror type level shifting circuit 100 comprises circuit operation control section 101, two bias voltage displacing parts 102 and 103, level shift part 104 and outputs 105.
Circuit operation control section 101 comprises two P channel MOS transistors (hereinafter the P channel MOS transistor being called the PMOS transistor) p101 and p102 and N-channel MOS transistor (hereinafter being called " nmos pass transistor ") n101.PMOS transistor p101 and nmos pass transistor n101 are connected in series between a power line (hereinafter being called " Vdd line ") and another power line (hereinafter being called " Vss line "), apply forward supply voltage Vdd on the power line Vdd line, apply negative sense supply voltage Vss on another power line Vss line.PMOS transistor p101 and nmos pass transistor n101 are connected to each other at grid and drain electrode.
Circuit operation control signal xstb is applied to the grid of PMOS transistor p101 and nmos pass transistor n101 from the outside.Circuit operation control signal xstb has low-voltage usually when circuit is in holding state (not working) state, but has high voltage when circuit working usually.PMOS transistor p102 source electrode is connected to the grid that Vdd line and its grid are connected to PMOS transistor p101 and nmos pass transistor n101.
Bias voltage displacing part 102 is formed by two PMOS transistor p103 and p104 and nmos pass transistor n102.PMOS transistor p103 and nmos pass transistor n102 are connected in series between Vdd line and Vss line, and its canopy utmost point is connected to each other and is connected to the drain electrode of PMOS transistor p101 and nmos pass transistor n101.PMOS transistor p103 and nmos pass transistor n102 drain electrode are connected to each other.PMOS transistor p104 is parallel-connected to nmos pass transistor n102 and receive clock CK on its grid.Bias voltage displacing part 102 is realized the shifting function of the DC bias voltage of clock CK.
Bias voltage displacing part 103 is formed by two PMOS transistor p105 and p106 and nmos pass transistor n103.PMOS transistor p105 and nmos pass transistor n103 are connected in series between Vdd line and the Vss line, and its grid and drain electrode are connected to each other.PMOS transistor 106 is parallel-connected to nmos pass transistor n103 and at its grid receiving phase clock xCK opposite with clock CK.Bias voltage displacing part 103 is realized the shifting function of the DC bias voltage of inversion clock xCK.
Level shift part 104 is formed by two PMOS transistor p107 and p108 and two nmos pass transistor n104 and n105.Two PMOS transistor p107 and the p108 source electrode is connected on the Vdd line and its grid is connected to each other.Grid and the drain electrode of PMOS transistor p107 are connected to each other.Thus, form current mirror circuit.The drain electrode (grid) of PMOS transistor p107 is connected to the drain electrode of PMOS transistor p102.
Nmos pass transistor n104 drain electrode is connected to the drain electrode (grid) of PMOS transistor p107 and the drain electrode that its grid is connected to PMOS transistor p103 and nmos pass transistor n102.Inversion clock xCK is applied to the source electrode of nmos pass transistor n104.The drain electrode of nmos pass transistor n105 is connected to the drain electrode of PMOS transistor p108 and the drain electrode that its grid is connected to PMOS transistor p105 and nmos pass transistor n103.Clock CK is applied to the source electrode of nmos pass transistor n105.
We can find from said structure, and level shift part 104 has the circuit structure of the imported current mirror amplifier of source electrode.Inversion clock xCK and positive phase clock CK are input to the source electrode of nmos pass transistor n104 and n105 respectively.
Output 105 is formed by nmos pass transistor n106, and the drain electrode of nmos pass transistor n106 is connected to the drain electrode of PMOS transistor p108 and nmos pass transistor n105, and its source electrode is connected to the Vss line.The grid of nmos pass transistor n106 is also connected to the grid of PMOS transistor p105 and nmos pass transistor n103.
As a kind of shift circuit, it is as the transfer level (shift stages) of shift-register circuit, known shift circuit with level shift function, its with clock pulse level shift (level conversion) as operation reference from first amplitude to second amplitude.For example, disclosed a kind of of this shift circuit with level shift function at the open No.2002-287711 (hereinafter being called patent documentation 2) of Japan Patent.The shift-register circuit of described type is as a kind of shift-register circuit, and it forms the scanner that uses in display device or image pick-up device.
Figure 77 shows a kind of embodiment with shift circuit structure of level shift function.With reference to Figure 77, shown shift circuit 100 comprises the current mirror circuit 101 as basic circuit.This current mirror circuit 101 is formed by grid nmos pass transistor n101 connected to one another and n102.Nmos pass transistor n101 is diode and connects, and wherein its grid and drain electrode are connected to each other.Clock CK inverting each other and xCK have low voltage amplitudes (for example, 0 to 3V), are input to the source electrode of nmos pass transistor n101 and n102 respectively.
In current mirror circuit 101, the drain electrode of nmos pass transistor n102 output has the high voltage amplitude of VSS-VDD (for example, 0 arrives 8V), and shifts pulse OUT output at it by inverter 102 anti-phase back conducts.PMOS transistor p101 and p102 are connected between the drain electrode and supply voltage VDD of nmos pass transistor n101 and n102.
Nmos pass transistor n103 and n104 are connected in series between the drain electrode and supply voltage VSS of nmos pass transistor n101.Shift pulse IN by the inverter 103 anti-phase after-applied canopy utmost points to nmos pass transistor n103.The drain electrode output of nmos pass transistor n102 is applied directly to the grid of nmos pass transistor n104.
PMOS transistor p103 and p104 are connected in series between the grid and supply voltage VDD of PMOS transistor p101.PMOS transistor p105 and p106 are connected in series to grid and the supply voltage VDD of PMOS transistor p102.PMOS transistor p107 and p108 are connected in parallel between the drain electrode (drain electrode of PMOS transistor p102) of nmos pass transistor n102 and supply voltage VDD.
The drain electrode output of nmos pass transistor n102 after anti-phase by inverter 102 (that is, shifting pulse OUT) is applied to the grid of PMOS transistor p103, p105 and p107.Shift the grid that pulse IN is applied directly to PMOS transistor p104, p106 and p108.
The grid that clock pulse xCK is applied to PMOS transistor p101 by the nmos pass transistor n105 that is connected in parallel with each other and n106.The canopy utmost point that clock signal C K is applied to inverter 102 by the nmos pass transistor n107 that is connected in parallel with each other and n108.Shift the grid that pulse IN is applied directly to nmos pass transistor n105 and n107.Shift the canopy utmost point that pulse OUT is applied to nmos pass transistor n106 and n108.
PMOS transistor p109 and p110 are connected between the grid of nmos pass transistor n103 and the supply voltage VDD and between the drain electrode (drain electrode of PMOS transistor p102) and supply voltage VDD of nmos pass transistor n102.Low level active homing pulse rst is applied to the canopy utmost point of PMOS transistor p109 and p110.
Find out obviously that from above-mentioned circuit structure shift circuit 100 of the prior art is configured to use the combination of the current mirror type level shift circuit and the Clock Extraction shift circuit of current mirror circuit 101.Has high level or shifts pulse OUT level shift circuit work when having high level when shifting pulse IN.
Summary of the invention
Have in the current mirror type level shifting circuit 100 of said structure in prior art, the DC bias voltage of clock CK and xCK is shifted by bias voltage displacing part 102 and 103 at first respectively, and clock CK and xCK are the clock of Vss-Vdd for amplitude by level shift part 104 level shifts (level conversion) at last.Therefore, leakage current (infiltration electric current) is being flowed by the represented circuit part of dashdotted each the arrow mark among Figure 77 always.This leakage current causes the high power consumption of level shifting circuit 100.
In addition, current mirror type level shifting circuit 100 has the problem that will solve, wherein, must have identical characteristic owing to form the PMOS transistor p107 each other in right of current mirror circuit with p108, so this current mirror type level shifting circuit 100 poor toughness in the diffusion of antagonism transistor characteristic.
In addition, have in the shift circuit with level shift function 100 of said structure in prior art, because it has and comprises the circuit structure of current mirror circuit 101 as basic circuit, therefore when this level shift circuit work, leakage current (infiltration electric current) always between supply voltage VDD and clock CK and xCK (by the represented part of dash-dot arrows mark) mobile.This leakage current causes the high power consumption of shift circuit 100.
In addition, because leakage current is mobile between supply voltage VDD and clock CK and xCK always, so requirement can absorb the output capacity of this leakage current.Therefore, the load height on clock CK and the xCK.In addition, since form current mirror circuit 101 must have identical characteristic each other in right nmos pass transistor n101 with n102, so current mirror circuit 101 poor toughness in the diffusion of antagonism transistor characteristic.
Be desirable to provide a kind of level shifting circuit, a kind of supply voltage generation circuit, a kind of shift circuit, a kind of shift-register circuit and a kind of display device, it can reduce to work under the power consumption and can strongly tackle the transistor characteristic diffusion.
According to embodiments of the invention, a kind of level shifting circuit is provided, and it comprises being one another in series and is connected between first supply voltage and the second source voltage and first and second transistors of type opposite each other in an electrically conductive, the clock end of input clock signal, be connected between clock end and the first transistor grid and first switching device that when circuit operation control signal is in effective status, has conducting state, be connected between the grid of second source voltage and transistor seconds and when circuit operation control signal is in effective status, have the second switch device of off state, and be connected capacity cell between clock end and the transistor seconds.
In having the level shifting circuit of said structure, when the circuit operation signal was in effective status, first switch sections had conducting state, and therefore, clock signal offers the grid of the first transistor by first switching device from clock end.Simultaneously, the second switch device places off state.Therefore, second source voltage interrupts for the supply of transistor seconds grid, and the grid of transistor seconds places floating dummy status.In addition, clock signal is by being passed to the grid of transistor seconds by the capacity cell coupling.
At this moment, the clock signal that offers first and second transistor gates has identical phase place, and the voltage that imposes on the high-side of clock signal of grid of transistor seconds becomes second source voltage.Second source voltage is applied to the voltage of high-side of clock signal of the first transistor grid and the voltage that produces and obtaining as relative displacement.In addition, the amplitude of clock signal has the value that is higher than the first and second transistorized threshold level Vth.Therefore, in the moment that first and second transistors will turn-off, be pursuant to the relation of above-mentioned grid voltage, they are guaranteed to place off state.Therefore, in the complementary circuit that forms by first and second transistors, can be definite prevent that transistor from turn-offing the time leakage current.
According to another embodiment of the present invention, a kind of shift circuit is provided, this shift circuit comprises level shifting apparatus, be used for when control impuls is in effective status clock pulse is displaced to second amplitude and exports the clock pulse of this level shift from first amplitude level, and the control impuls generating means that is used to produce control impuls, this level shifting apparatus is included in and is connected in series between first supply voltage and the second source voltage and first and second transistors of type opposite each other in an electrically conductive, the clock end of input clock pulse, be connected between the grid of clock end and the first transistor and first switching device that when control impuls is in effective status, has conducting state, be connected between the grid of second source voltage and transistor seconds and when this control impuls is in effective status, have the second switch device of off state, and be connected capacity cell between the grid of clock end and transistor seconds.
In having the shift circuit with level shift function of said structure, when control impuls is in effective status, first switching device has conducting state, and therefore, clock pulse offers the grid of the first transistor from clock end by first switching device.Simultaneously, the second switch device places off state.Therefore, second source voltage is interrupted for the supply of transistor seconds grid, and the grid of transistor seconds places floating dummy status.In addition, clock pulse passes to the grid of transistor seconds by the coupling of capacity cell.
At this moment, impose on the first and second transistorized clock pulse and have identical phase place, and the voltage of high-side that imposes on the clock pulse of transistor seconds grid becomes second source voltage.This second source voltage is applied to the voltage of high-side of clock pulse of the first transistor grid and the voltage that produces and obtaining as displacement relatively.In addition, the amplitude of clock pulse has the value that is higher than the first and second transistorized threshold level Vth.Therefore, in the moment that first and second transistors will turn-off, according to the relation of above-mentioned grid voltage, they are guaranteed to place off state.Therefore, in the complementary circuit that forms by first and second transistors, can be definite prevent that transistor from turn-offing the time leakage current.
According to another embodiment of the present invention, a kind of shift-register circuit is provided, this shift-register circuit comprises that a plurality of first shift circuits of alternately cascade connection are to right with a plurality of second shift circuits, each first shift circuit is to first shift circuit that comprises cascade and connect and second shift circuit and three shift circuit and four shift circuit of each second shift circuit to comprising that cascade is connected simultaneously, when first control impuls has effective status, first shift circuit can be operated, dash with the low level lateral vein that extracts first clock pulse, this low level lateral vein dashed be displaced to second amplitude from first amplitude level, and the low level lateral vein of exporting this level shift dashes, when first control impuls has effective status, second shift circuit can be operated, equate with first clock pulse frequency but relative first clock pulse has the second clock pulses low lateral vein of 1/4 cycle phase shift dashes to extract, this low level lateral vein dashed be displaced to second amplitude from first amplitude level, and the low level lateral vein of exporting this level shift dashes, when second control impuls has effective status, the 3rd shift circuit can be operated, to extract the high-side pulse of first clock pulse, this high-side pulse is displaced to second amplitude from first amplitude level, and the level lateral vein of exporting this level shift dashes, and when second control impuls has effective status, the 4th shift circuit can be operated, to extract the high-side pulse of second clock pulse, this high-side pulse is displaced to second amplitude from first amplitude level, and exports the high-side pulse of this level shift.
In having the shift-register circuit of said structure, a plurality of first shift circuits mean first to a plurality of second shift circuits cascade alternately being connected, the second, the third and fourth shift circuit cascade connects and organizes four such shift circuits more and repeat setting and cascade connection.Then, the setting that repeats at the first, second, third and the 4th shift circuit alternately applies first clock pulse and the second clock pulse in 1/4 cycle of phase shift each other.Therefore, the frequency that will be used to drive shift-register circuit can be reduced to half of the employed clock pulse of shift register of the prior art, and its a plurality of shift circuits by the same circuits structure that repeats to be provided with form.In first and second shift circuits, low level (hereinafter being called " the low-voltage ") lateral vein of each first and second clock pulse is rushed in row extract to realize level shift (level conversion).In third and fourth shift circuit, (hereinafter being called " high voltage) lateral vein rushes in row and extracts to realize level shift with the high level of each first and second clock pulse.Extract and the pulse of level shift is shifted the level (shift circuit) from each and exported as shifting pulse.
In having the shift-register circuit of said structure, each first and second shift circuit can comprise type opposite each other in an electrically conductive and first and second transistors that are connected in series between first supply voltage and second source voltage, import first clock end of first and second clock pulse, be connected between the grid of first clock end and the first transistor and first switching device that when first control impuls is in effective status, has conducting state, be connected between the grid of second source voltage and transistor seconds and when first control impuls is in effective status, have the second switch device of off state, and be connected first capacity cell between the grid of first clock end and transistor seconds.Simultaneously, each third and fourth shift circuit can comprise type opposite each other in an electrically conductive and third and fourth transistor that is connected in series between first supply voltage and second source voltage, import the second clock end of first and second clock pulse, be connected between second clock end and the 3rd transistorized grid and the 5th switching device that when second control impuls is in effective status, has conducting state, be connected than second source voltage and hang down between the 3rd supply voltage of amplitude voltage of first and second clock pulse and the 4th transistorized grid and when second control impuls is in effective status, have the 6th switching device of off state, and be connected second capacity cell between second clock end and the 4th transistorized grid.
In having first and second shift circuits of said structure, because first switching device has conducting state when first control impuls is in effective status, this clock pulse (first clock pulse of first shift circuit, and the second clock pulse of second shift circuit) is applied to the grid of the first transistor from first clock end by first switching device.Simultaneously, the second switch device places off state.Therefore, interrupt of the supply of second source voltage, and the grid of transistor seconds places floating dummy status to the transistor seconds grid.In addition, this clock pulse is by being passed to the grid of transistor seconds by the coupling of first capacity cell.
At this moment, the clock pulse that imposes on first and second transistor gates has identical phase place, and the voltage that imposes on the clock pulse high-side of transistor seconds grid becomes second source voltage.This second source voltage imposes on the voltage of high-side of clock pulse of the first transistor grid and the voltage that produces and obtaining as displacement relatively.In addition, the amplitude of this clock pulse is higher than the first and second transistorized threshold level Vth.Therefore, turn-offing for the first and second transistorized moment, according to the relation between the above-mentioned grid voltage, they are guaranteed to place off state.Therefore, in the complementary circuit that forms by first and second transistors, can guarantee to prevent the leakage current when transistor turn-offs.Equally, in third and fourth shift circuit, carry out its operation and the substantially similar operation of first and second shift circuits.
By means of this level shifting circuit, shift circuit, and shift-register circuit, owing to can guarantee to prevent leakage current when transistor turn-offs, so can reduce power consumption.In addition, because this level shifting circuit, shift circuit, and shift-register circuit has the circuit structure that does not use current mirror circuit, so they can resist the diffusion of transistor characteristic forcefully.
Description of drawings
In conjunction with the accompanying drawings, will clearer these and other objects of the present invention with reference to specification, wherein:
Fig. 1 is the circuit diagram that illustrates according to the level shifting circuit structure of first embodiment of the invention;
Fig. 2 is the sequential chart that the level shifting circuit basic circuit operation of Fig. 1 when circuit operation control signal is in effective status is shown;
Fig. 3 is the sequential chart that the recommendation sequential of circuit operation control signal relative time clock pulse is shown;
Fig. 4 is the sequential chart that the sequential relationship when circuit operation control signal rises to high level simultaneously clock pulse is in low level state is shown;
Fig. 5 is the circuit diagram that illustrates according to the level shifting circuit structure of second embodiment of the invention;
Fig. 6 is the sequential chart of circuit operation that the level shifting circuit of Fig. 5 is shown;
Fig. 7 illustrates the block diagram of using 1 supply voltage generation circuit structure according to the present invention;
Fig. 8 is the block diagram that the embodiment of the buffer portion structure shown in Fig. 7 is shown;
Fig. 9 is the circuit diagram that the inverter circuit structure embodiment shown in Fig. 8 is shown;
Figure 10 is the circuit diagram that the negative supply generating unit separation structure embodiment shown in Fig. 7 is shown;
Figure 11 illustrates the circuit diagram of using 2 supply voltage generation circuit structure according to the present invention;
Figure 12 is the circuit diagram that the NAND circuit structure embodiment shown in Figure 11 is shown;
Figure 13 illustrates the sequential chart of sequential relationship that produces the place of reset pulse based on the output of the buffer portion shown in Figure 11;
Figure 14 is the circuit diagram of embodiment that the active array type liquid crystal display structure of the Application Example according to the present invention is shown;
Figure 15 is the circuit diagram that illustrates according to the circuit structure of the shift circuit of third embodiment of the invention;
Figure 16 is the clock pulse that the shift circuit of Figure 15 is shown, input pulse, control impuls, anti-phase control impuls and the level relationship of output pulse and the sequential chart of sequential relationship;
Figure 17 is the circuit diagram that illustrates according to the level shift part-structure of embodiment 1;
Figure 18 is the sequential chart of the level shift circuit operation partly of Figure 17;
Figure 19 is the circuit diagram that illustrates according to the level shift part-structure of embodiment 2;
Figure 20 is the sequential chart that the level shift circuit operation partly of Figure 19 is shown;
Figure 21 is the block diagram that illustrates according to the circuit structure of the shift circuit of the distortion 1 of the 3rd embodiment;
Figure 22 is the circuit diagram that illustrates according to the level shift part-structure of embodiment 3;
Figure 23 is the sequential chart that the level shift circuit operation partly of Figure 22 is shown;
Figure 24 is the block diagram that illustrates according to the circuit structure of the shift circuit of the distortion 2 of the 3rd embodiment;
Figure 25 is the block diagram that illustrates according to the control impuls generating unit separation structure of embodiment 1;
Figure 26 is the sequential chart that the control impuls generation circuit operation partly of Figure 25 is shown;
Figure 27 is the circuit diagram that the embodiment of the NOR circuit structure shown in Figure 25 is shown;
Figure 28 is the circuit diagram that the embodiment of the inverter circuit structure shown in Figure 25 is shown;
Figure 29 is the block diagram that illustrates according to the control impuls generating unit separation structure of embodiment 2;
Figure 30 is the sequential chart that the control impuls generation circuit operation partly of Figure 29 is shown;
Figure 31 is the block diagram that illustrates according to the control impuls generating unit separation structure of embodiment 3;
Figure 32 is the sequential chart that the control impuls generation circuit operation partly of Figure 31 is shown;
Figure 33 is the block diagram that illustrates according to the control impuls generating unit separation structure of embodiment 4;
Figure 34 is the block diagram that illustrates according to the circuit structure of the shift circuit of the distortion 3 of the 3rd embodiment;
Figure 35 is the block diagram that illustrates according to the circuit structure of the shift circuit of the distortion 4 of the 3rd embodiment;
Figure 36 is the block diagram that illustrates according to the circuit structure of the shift circuit of the distortion 5 of the 3rd embodiment;
Figure 37 illustrates Figure 34, the sequential chart of the circuit operation of 35 and 36 shift circuit;
Figure 38 illustrates the block diagram of using 3 shift-register circuit structure according to the present invention;
Figure 39 is the sequential chart that the shift-register circuit operation of Figure 38 is shown;
Figure 40 illustrates the block diagram of using 4 shift-register circuit structure according to the present invention;
Figure 41 is the sequential chart that the shift-register circuit operation of Figure 40 is shown;
Figure 42 illustrates the block diagram of using 5 shift-register circuit structure according to the present invention;
Figure 43 is the sequential chart that the shift-register circuit operation of Figure 42 is shown;
Figure 44 is a block diagram of using 6 shift-register circuit structure according to the present invention;
Figure 45 illustrates the block diagram of using 7 shift-register circuit structure according to the present invention;
Figure 46 is the sequential chart that the shift-register circuit operation of Figure 45 is shown;
Figure 47 is the circuit diagram that the TRN circuit structure embodiment shown in Figure 45 is shown;
Figure 48 is the sequential chart that the TRN circuit operation of Figure 47 is shown;
Figure 49 and 50 illustrates wherein shifting the sequential chart that the sequential relationship of blanking cycle is set between the pulse;
Figure 51 is the circuit diagram that the embodiment of Vin voltage generating circuit structure is shown;
Figure 52 and 53 is sequential charts of different operating that the Vin voltage generating circuit of Figure 51 is shown;
Figure 54 is the block diagram of embodiment that the active array type liquid crystal display structure of the Another Application embodiment according to the present invention is shown;
Figure 55 is the block diagram that illustrates according to the shift-register circuit structure of fourth embodiment of the invention;
Figure 56 is the sequential chart that the shift-register circuit operation of Figure 55 is shown;
Figure 57 is the block diagram that the embodiment of the first and second shift circuit structures shown in Figure 55 is shown;
Figure 58 is the circuit diagram that the embodiment of the level shift part-structure shown in Figure 57 is shown;
Figure 59 is the sequential chart that the level shift part operation of Figure 58 is shown;
Figure 60 is the block diagram that the embodiment of the control impuls generating unit separation structure shown in Figure 56 is shown;
Figure 61 is the sequential chart that the control impuls generating unit parallel circuit operation of Figure 60 is shown;
Figure 62 is the block diagram that the embodiment of the third and fourth shift circuit structure shown in Figure 55 is shown;
Figure 63 is the circuit diagram that the embodiment of the level shift part-structure shown in Figure 62 is shown;
Figure 64 is the sequential chart that the level shift partial circuit operation of Figure 63 is shown;
Figure 65 is the block diagram that illustrates according to the shift-register circuit structure of fifth embodiment of the invention;
Figure 66 is the sequential chart that the shift-register circuit operation of Figure 65 is shown;
Figure 67 is the block diagram that the embodiment of the first and second shift circuit structures shown in Figure 65 is shown;
Figure 68 is the block diagram that the control impuls generating unit separation structure shown in Figure 67 is shown;
Figure 69 is the sequential chart that the control impuls generating unit parallel circuit operation of Figure 67 is shown;
Figure 70 is the block diagram that the embodiment of the third and fourth shift circuit structure shown in Figure 65 is shown;
Figure 71 is the circuit diagram that the embodiment of the input of 3 shown in Figure 55 AND circuit structure is shown;
Figure 72 is the circuit diagram that the embodiment of inverter circuit structure is shown;
Figure 73 is the circuit diagram that the embodiment of the input of 2 shown in Figure 60 NOR circuit structure is shown;
Figure 74 is the circuit diagram that the embodiment of the input of 3 shown in Figure 65 NOR circuit structure is shown;
Figure 75 is the circuit diagram that the embodiment of the input of 2 shown in Figure 68 NAND circuit structure is shown;
Figure 76 is the circuit diagram that the embodiment of current mirror type level shifting circuit structure in the prior art is shown; And
Figure 77 is the circuit diagram that the shift circuit that has the level shift function in the prior art is shown.
Embodiment
[first embodiment]
Fig. 1 shows the circuit structure according to the level shifting circuit of first embodiment of the invention.With reference to figure 1, level shifting circuit 10 according to present embodiment uses the first supply voltage Vss and second source voltage Vdd as operating power voltage, and carry out and realize that for example the 0 clock signal C K level conversion (level shift) that arrives first amplitude of 3V arrives the especially circuit operation of another clock signal of second amplitude of Vss-Vdd (for example, 0 to 8V).
This level shifting circuit 10 comprises complementary circuit 11, inverter 12, the first to the 3rd switching circuits 13 to 15, one-way circuit 16, and capacity cell C.
Circuit operation control signal " xstb " has supply voltage Vss (hereinafter being called " low-voltage ") usually when circuit is in holding state (off position), but has supply voltage Vdd (hereinafter being called " high voltage ") when circuit is in running order usually.
First switching circuit 13 is formed by cmos switch, and this cmos switch comprises nmos pass transistor n13 and the PMOS transistor p13 that is connected in parallel with each other.First switching circuit, 13 inputs are connected to clock end 19 (for example amplitude is that 0 to 3V clock pulse CK is fed to clock end 19 from the outside), and its output is connected to the grid of nmos pass transistor n1.
In addition, the grid of nmos pass transistor n13 is connected to the input (grid of nmos pass transistor n12 and PMOS transistor p12) of inverter 12.Simultaneously, PMOS transistor p13 input is connected to the output (drain electrode of nmos pass transistor n12 and PMOS transistor p12) of inverter 12.Therefore, circuit operation control signal " xstb " is fed to the grid of nmos pass transistor n13, and simultaneously, the signal provision that phase place is opposite with circuit operation control signal " xstb " arrives the grid of PMOS transistor p13.
Should be noted that, although cmos switch is herein as first switching circuit 13, to such an extent as to wherein the high voltage of clock pulse CK needn't be considered transistorized threshold level Vth well below supply voltage Vdd, even but switch only form by a nmos pass transistor, also can guarantee enough allowances.Therefore, in this case, the switch that only has a nmos pass transistor to form can be used as first switching circuit 13.Wherein use the place of the switch that a nmos pass transistor formation is only arranged, needn't produce and the opposite signal of circuit operation control signal " xstb " phase place, and therefore, can omit inverter 12.
The 3rd switching circuit 15 is formed by the PMOS transistor p15 between the canopy utmost point that is connected supply voltage Vdd and nmos pass transistor n11, and it receives the circuit operation control signal " xstb " as the grid input like this.The 3rd switching circuit 15 places off state when circuit operation control signal " xstb " when being in effective status, with the canopy utmost point and the electric each other disconnection of supply voltage Vdd with nmos pass transistor n11.
One-way circuit 16 comprise have diode connect-nmos pass transistor n14 that to be grid be connected jointly with drain electrode with have the PMOS transistor p16 that diode is connected equally.One-way circuit 16 is connected between the grid and supply voltage Vdd of PMOS transistor p11.One-way circuit 16 is when the voltage of Node B, and promptly the voltage on the grid of PMOS transistor p11 carries out work when being higher than supply voltage Vdd, makes it equal supply voltage Vdd with the voltage of adjusting Node B.
Yet, even the voltage adjustment of Node B carry out by one-way circuit 16, but in fact the voltage of Node B only drop to the threshold level Vth that equals MOS transistor n14 and p16 and supply voltage Vdd's and voltage.
Capacity cell C is connected to the grid of clock end 19 and nmos pass transistor n11.Therefore, clock pulse CK is delivered to the grid of PMOS transistor p11 by capacity cell C coupling.
Now, with reference to figs. 2 to 4 circuit operations of describing according to the level shifting circuit with said structure 10 of first embodiment.
At first, work as circuit operation control signal " xstb " with reference to figure 2 descriptions and be in effective status, that is, and the basic circuit of level shifting circuit 10 operation when having high level (supply voltage Vdd).
Ifs circuit operating control signal " xstb " places effective status, and first switching circuit 13 places conducting state so, and the second and the 3rd switching circuit 14 and 15 places off state simultaneously.When first switching circuit 13 placed conducting state, clock pulse CK was applied to the canopy utmost point of nmos pass transistor n11 from clock end 19 by first switching circuit 13.
Simultaneously, when the second and the 3rd switching circuit 14 and 15 places off state, interrupt the supply voltage Vdd of the grid of supply PMOS transistor p11 and nmos pass transistor n11, and the grid of PMOS transistor p11 places floating dummy status.Therefore, be delivered to the grid of PMOS transistor p11 by capacity cell C coupling from the clock pulse of clock end 19.
At this moment, have identical phase place although be applied to the clock pulse CK of the canopy utmost point of PMOS transistor p11 and nmos pass transistor n11, the high side voltage of clock pulse CK that imposes on the grid of PMOS transistor p11 has supply voltage Vdd.Therefore, the voltage VB of Node B, that is, the grid voltage of PMOS transistor p11 is considered to the voltage VA from node A, i.e. the voltage of the relative displacement of the grid voltage of nmos pass transistor n11.
In addition, the amplitude of clock pulse CK is greater than the value of the threshold level Vth of PMOS transistor p11 and nmos pass transistor n11.Therefore, in the moment that PMOS transistor p11 and nmos pass transistor n11 will turn-off, according to the voltage VA of node A and B and the relation of VB, their are guaranteed to place off state.Therefore, the complementary circuit 11 that is formed by PMOS transistor p11 and nmos pass transistor n11 can guarantee to prevent to be in the MOS transistor p11 of off state and the leakage current of n11 simultaneously with the clock pulse " output " of clock pulse CK level conversion to the Vss-Vdd amplitude.
Fig. 3 shows the recommendation time of circuit operation control signal " xstb " with respect to clock pulse CK.From the sequential chart of Fig. 3 as can be seen, the time of circuit operation control signal " xstb " so preferably sets and makes that when clock pulse CK was in high state, circuit operation control signal " xstb " became effective status from disarmed state, that is, rise to high level from low level.The result who carries out time set like this is that before circuit operation control signal " xstb " rose to high level, second switch circuit 14 was in conducting state at once.Therefore, the voltage VB on the Node B is supply voltage Vdd, and therefore, the voltage VB on the Node B begins action in the plan mode from driving to put the zero hour.
Fig. 4 shows the sequential relationship when circuit operation control signal " xstb " rises to high level simultaneously clock pulse CK is in low level state.When circuit operation control signal " xstb " rose to high level simultaneously clock pulse CK is in low level state, wherein the high voltage of clock pulse CK was represented by Vin, and circuit operation begins when the voltage VB of Node B rises to the state of Vdd+Vin.
In this case, the voltage VB on the Node B is regulated by one-way circuit 16 so that equal supply voltage Vdd, one-way circuit 16 work when the voltage VB on the Node B is higher than supply voltage Vdd.Yet, in fact, the voltage VB on the Node B only drop to equal supply voltage Vdd and MOS transistor n14 and p16 threshold level Vth's and voltage.
Obviously find out from the front, although wherein sequential relationship is as shown in Figure 4 and circuit operation does not have problem even, also considered to arrive the time period of the guaranteed or further stable operation of circuit operation, but quite preferably adopt the sequential relationship of Fig. 3, that is the circuit operation control signal when, clock pulse CK is in high state " xstb " rises to the sequential relationship of high level.
As mentioned above, be used for that (for example, (for example, the level shifting circuit 10 of clock pulse 0-8V) " output " comprises clock pulse CK level conversion 0-3V) to second amplitude with first amplitude, as basic circuit, by nmos pass transistor n11 and the formed complementary circuit 11 of PMOS transistor p11.Then, in case level shifting circuit 10 beginning circuit operations, clock pulse CK is applied to the grid of nmos pass transistor n11, and the clock pulse CK that will be displaced to supply voltage Vdd rear flank simultaneously by capacity cell C coupling relatively is applied to the grid of PMOS transistor p11.Therefore, in the moment that nmos pass transistor n11 and PMOS transistor p11 will turn-off, guarantee that they are placed in off state.Therefore, there is not leakage current to flow to complementary circuit 11.
Owing to do not have leakage current to flow through level shifting circuit 10 in this mode, therefore can realize reducing of level shifting circuit 10 power consumptions.In addition, the complementary circuit 11 that forms owing to the transistor by conductivity type opposite is used as basic circuit, therefore compare as the level shifting circuit of the prior art of basic circuit with adopting current mirror circuit, this level shifting circuit can favourable antagonism transistor characteristic (threshold level Vth, drain-source current Ids, or the like) in diffusion.In addition, only require two kinds of signals of clock pulse CK and circuit operation control signal " xstb " as the clock signal that will import, thereby with prior art in require the level shifting circuit of the clock pulse CK xCK opposite to compare with phase place, can reduce the quantity of desired clock signal.
[second embodiment]
Fig. 5 shows the circuit structure according to the level shifting circuit of second embodiment of the invention.
With reference to figure 5, remove the element of the level shifting circuit 10 of first embodiment according to the level shifting circuit 20 of second embodiment, promptly, complementary circuit 11, inverter 12, the first to the 3rd switching circuits 13 to 15, one-way circuit 16, and also comprise reset circuit 21 beyond the capacity cell C.
The circuit operation of the level shifting circuit 20 of second embodiment with said structure is described with reference to figure 6 now.
Reset pulse " rst " has the sequential relationship of setting like this, and than the length in the high level period, and this low-level period is included in the high level period of clock pulse CK in its duty ratio in the low-level period.At this, the low-level period that requires reset pulse " rst " is a time period that is enough to the voltage VB on the Node B is charged to supply voltage Vdd.
It can also be seen that from the sequential chart of Fig. 6 the voltage VB on the Node B should equal supply voltage Vdd in logic.Yet in fact, voltage VB and supply voltage Vdd on the Node B a little depart from.Reset circuit 21 is set so that little the departing between adjusting and the supply voltage Vdd.
In reset circuit 21, PMOS transistor p17 response shows low level reset pulse " rst " and places conducting state when clock pulse CK has high level.Therefore, whenever clock pulse CK performance high level, supply voltage Vdd just is supplied to Node B (grid of PMOS transistor p11).
The result is that the voltage VB on the Node B guarantees to equal supply voltage Vdd in the high level period of clock pulse CK.In other words, in the present embodiment, after each cycle of clock pulse CK, reset circuit 21 is periodically carried out the operation of guaranteeing the voltage VB on the Node B is set at supply voltage Vdd.Therefore, guarantee to carry out the circuit operation of level shifting circuit 20.
To describe in more detail below and guarantee the executive circuit operation.Circuit operation cycle in of circuit operation control signal " xstb " with high level therein, because PMOS transistor p14 shows as off state, so Node B has floating dummy status.Therefore, the voltage VB on the Node B similarly is vulnerable to sneak into the influence of noise etc. by intrinsic capacity or other, and must be when keeping floating dummy status control voltage VB.Be higher than supply voltage Vdd if voltage VB becomes, practical adjustments becomes voltage Vdd+Vth to the voltage VB on the Node B by the action of one-way circuit 16 so, and voltage VB equals supply voltage Vdd like this.
Yet, one-way circuit 16 circuit for only becoming and just move when being higher than supply voltage Vdd as voltage VB.Therefore, if becoming, voltage VB is lower than voltage voltage Vdd, so wherein the state that is lower than supply voltage Vdd of the voltage VB on the Node B will continue, unless circuit operation signal " xstb " is placed on high level state in case turn back to low level state at it, if and voltage VB becomes quite low, circuit operation can not continue so.
On the contrary, by means of level shifting circuit 20 according to second embodiment, owing to guarantee by reset circuit 21 in the cycle and will be set to the action that voltage VB on the Node B of Node B of floating dummy status periodically is set at supply voltage Vdd at circuit operation, especially true for this situation, so just can prevent the excessive descent of voltage VB.Therefore, can guarantee the executive circuit operation.
[using 1]
Fig. 7 shows the structure of using 1 supply voltage generation circuit according to the present invention.With reference to figure 7, according to comprising level shift part (LSa) 31 with 1 supply voltage generation circuit 30, buffer portion (BUFa) 32, and negative supply voltage generation part (GENa) 33.In addition, supply voltage generation circuit 30 comprises according to the level shifting circuit 10 of first embodiment or according to the level shifting circuit 20 of above-mentioned second embodiment, as its level shift part 31.
Fig. 8 illustrates the embodiment of the structure of buffer portion 32.With reference to figure 8, three inverter circuits 321,322 that shown buffer portion 32 comprises that cascade connects and 323.These three inverter circuits 321,322 and 323 are constructed like this, and the inverter circuit 323 of transistor size on from the inverter circuit on the input side 321 to outlet side increases gradually, so that guarantee the driving capacity of next stage.
With reference to figure 9, for example, for inverter circuit 321,322 and 323, use the CMOS inverter, wherein PMOS transistor p21 and nmos pass transistor n21 are connected in series between supply voltage Vdd and the supply voltage Vss, make its grid be connected separately from each other with drain electrode like this.Yet in fact, inverter 321,322 and 323 needn't be formed by the CMOS inverter.
Figure 10 shows the embodiment of negative supply voltage generation part 33 structures.With reference to Figure 10, shown negative supply voltage generation part 33 comprises two capacitor CA1 and CA2, two clamp circuits 331 and 332, and sample circuit 333.The clock pulse that phase place is opposite " xin " and " in " are input to negative supply voltage generation part 33 by clock end 334 and 335 respectively.It is that the clock pulse " output " of Vss-Vdd obtains that the clock pulse that phase place is opposite " xin " and " in " transmit amplitude by level shift part 31 level conversion by buffer portion 32.
Two capacitor CA1 and CA2 action are to block the DC composition of clock pulse " xin " and " in " respectively.Clamp circuit 331 by between output that is connected capacitor CA1 and the supply voltage Vss and the PMOS transistor p22 that is connected to the output of capacitor CA2 form and the output level of the capacitor CA1 on the clamp supply voltage Vss.Clamp circuit 332 by between output that is connected capacitor CA2 and the supply voltage Vss and the PMOS transistor p23 that is connected on the output of capacitor CA1 form and the output level of the capacitor CA2 on the clamp supply voltage Vss.
As mentioned above, wherein the level shifting circuit 10 or 20 according to the first or second above-mentioned embodiment is used as level shift part 31 in the supply voltage generation circuit 30, this supply voltage generation circuit 30 has level shift part 31, buffer portion 32, and negative supply generation part 33, owing in level shifting circuit 10 or 20, prevent leakage current, so power consumption can be repressed very low.Therefore, can realize the low-power consumption of supply voltage generation circuit 30.
[using 2]
Figure 11 illustrates the structure of using 2 supply voltage generation circuit according to the present invention.
With reference to Figure 11, according to using in 2 the supply voltage generation circuit 40, use level shifting circuit 20 according to second embodiment as level shift part 31.Level shifting circuit 20 according to second embodiment is constructed like this, makes it comprise that the voltage VB that periodically guarantees to set on the Node B is the reset circuit 21 of supply voltage Vdd, and wherein in the circuit operation phase, Node B is placed in floating dummy status.Therefore, need be used to control the reset pulse " rst " of reset circuit 21.
Be characterised in that according to the supply voltage generation circuit 40 of using 2: use the delay in the supply voltage generation circuit 30 to make reset pulse " rst " supply voltage generation circuit 40 inner generations.More particularly, the output x1 of the inverter circuit on the first order of buffer portion 32 321 and the output x2 of the inverter circuit 322 on the second level are extracted, and be input to two inputs of NAND circuit 34, the effective reset pulse of low level " rst " produces as the output of NAND circuit 34 like this.
Figure 12 illustrates the embodiment of NAND circuit 34 structures.With reference to Figure 12, shown NAND circuit 34 comprises being one another in series and is connected between circuit output end 343 and the supply voltage Vss and its grid is connected to the nmos pass transistor n23 and the n24 of circuit input end 341 and 342, and is connected in parallel with each other between supply voltage Vdd and circuit output end 343 and its grid is connected respectively to the PMOS transistor p24 and the p25 of circuit input end 341 and 342.Should be noted that described circuit structure only is an embodiment, and the structure of NAND circuit 34 is not limited to the just described circuit structure of stating.
Figure 13 shows the sequential relationship based on the output x1 of buffer portion 32 and x2 generation reset pulse " rst ".As shown in figure 13, export execution NAND operation between the x2 by the delay of adopting supply voltage generation circuit 30 at the output x1 and the inverter circuit on the second level 322 of the inverter circuit on the first order 321, and low level active homing pulse " rst " can be produced in supply voltage generation circuit 40.
The place that needs bigger delay at buffer portion 32, can adopt a kind of method of the progression (this quantity should be odd number) that wherein increases the inverter in the buffer portion 32, also can adopt by another kind of method or the similar approach that circuit constant causes further delay is set.
Wherein, in supply voltage generation circuit 40 (it adopts level shifting circuit 20 according to second embodiment as level shift part 31), adopt the delay in the buffer portion 32 and produce the effective reset pulse of low level " rst ", therefore eliminated from the necessity of outside input reset pulse " rst " in the inside of supply voltage generation circuit 40.Therefore, can remove the terminal that is used to receive reset pulse " rst ".
Should notice, although in above-mentioned application 1 and 2, supply voltage generation circuit 30 and 40 forms the negative supply voltage generation circuit that comprises negative supply voltage generation part 33, but can also use the positive voltage generation circuit with positive voltage part equally.
Can be widely used in the supply voltage generation circuit of operating based on the clock pulse executive circuit according to the supply voltage generation circuit 30 and 40 of using 1 and 2.As an embodiment, supply voltage generation circuit 30 and 40 can be used as a peripheral drive circuit with the display device of drive circuit integrated-type.In this display device, peripheral drive circuit (it is used to drive comprising the pixel of the photoelectric cell pixel array part with the row and column two-dimensional arrangements) is formed on the plate that forms pixel array portion.
[Application Example 1]
Figure 14 illustrates an embodiment of the display device structure of the Application Example according to the present invention.Display device shown in Figure 14 forms the active array type liquid crystal display, and wherein liquid crystal cells is as the photoelectric cell of pixel.
With reference to Figure 14, according to should comprising pixel array portion 51 with the active array type liquid crystal display 50 of embodiment, vertical driver 52, horizontal driver 53, supply voltage generation circuit 54, or the like.Comprise vertical driver 52, the peripheral drive circuit of horizontal driver 53, and supply voltage generation circuit 54 are formed on the liquid crystal panel 58 that pixel array portion 51 is set.Display panels 58 is constructed like this, and two insulating bases (as glass film plates) are provided with according to relativeness, reserve the fixed interval (FI) therebetween, and in this gap the encapsulated liquid crystals material.
In above-mentioned dot structure, the grid of the TFT 61 of each pixel 60 is connected to scan line 55 (55-1 is to 55-m) and its source electrode is connected to holding wire 56 (56-1 is to 56-n).Simultaneously, another electrode of the comparative electrode of liquid crystal cells 62 and maintenance capacitor 63 is connected on the common wire 57, applies common electric voltage VCOM on common wire 57.
Supply voltage generation circuit 54 is the circuit that for example produce negative supply voltage, and places the peripheral drive circuit (for example vertical driver 52) of pixel array portion 51 so that negative supply voltage is provided.As supply voltage generation circuit 54, can use supply voltage generation circuit 30 or 40 according to above-mentioned application 1 or 2.
For example, supply voltage generation circuit 54 receive frequencies are higher than the clock pulse of vertical clock pulse VCK to be imported as it, imports the reference of this vertical clock pulse as the vertical scanning of vertical driver 52.For example, circuit 54 receives horizontal clock pulse HCK, imports this horizontal clock pulse HCK as the reference that is used for the horizontal sweep of horizontal driver 53.Therefore supply voltage generation circuit 54 produces negative supply voltage and this negative supply voltage is supplied with negative power line on vertical driver 52 output stages based on horizontal clock pulse HCK operation.
In other words, horizontal clock pulse HCK is corresponding to being input to according to the clock pulse CK in the level shift part 31 of the supply voltage generation circuit 30 of above-mentioned application 1 or 2 or 40.The input clock pulse that should be noted that supply voltage generation circuit 54 is not limited to horizontal clock pulse HCK.
Comprise vertical driver 52, the peripheral drive circuit of horizontal driver 53, and above-mentioned supply voltage generation circuit 54 is formed on the display panels (insulating base) 58 this display panels use multi-crystal TFT with pixel array portion 51.
In addition, in the last few years, for reducing of voltage, such as the increase of performances such as contrast increase, and the requirement that liquid crystal display picture quality increases had increased and had increased in continuation.Usually, contrast increases that to reduce with voltage be reciprocal requirement.Particularly, in order to increase contrast, must increase the amplitude of the vision signal that is input to liquid crystal display, and the result is that the driving voltage of liquid crystal display uprises, and causes reducing the failure of voltage.On the contrary, in order to reduce voltage, the amplitude of vision signal reduces, and this will cause reducing of contrast.
In order both to satisfy reducing of voltage, satisfy the increase of contrast again, it is quite necessary adopting a kind of method, in the method, the level of the low voltage side of vision signal reduces lowly as far as possible (reducing so that reach ground level), and the end value of vision signal also reduces, and the high-voltage side of vision signal reduces the dynamic range increase of vision signal simultaneously in addition.
Yet, if adopt described method, may exist so, if the threshold level Vth of TFT 61 (it keeps the high-voltage side of vision signal), deflection descends, have 0V and holding wire 56 (56-1 is to 56-n) has low level when scan line 55 (55-1 is to 55-m) so, TFT 61 may leak with the generation bright spot, and this bright spot is called the leakage bright spot.Yet,, can fully obtain so at enough allowances of leaking bright spot if the low level of scan line 55 (55-1 is to 55-m) can be set at negative voltage.
Therefore, as mentioned above, with the integrated liquid crystal display 50 of drive circuit in, supply voltage generation circuit 54 is integrated on the display panels 58 as a kind of peripheral drive circuit, and the negative supply voltage that is produced by supply voltage generation circuit 54 is supplied to vertical driver 52, makes the low level of scan line 55 (55-1 is to 55-m) be set at negative level.Therefore, owing to can reduce the level of the low voltage side of vision signal low as far as possible and reduce the end value of vision signal together, and the high-voltage side that reduces vision signal in addition increases the dynamic range of vision signal simultaneously, therefore can realize simultaneously that voltage reduces and the increase of contrast, and can not occur by leaking bright spot.
In addition, because supply voltage generation circuit 54 is formed on the display panels 58, therefore needn't outside display panels 58, provide supply voltage generation circuit.In addition, owing to eliminated the necessity that is used to receive from the terminal of the negative supply voltage of panel outside, therefore can reduce in the burden that is provided with in the design.
In addition, in supply voltage generation circuit 30 or 40 places as supply voltage generation circuit 54 according to above-mentioned application 1 or 2, because supply voltage generation circuit 30 or 40 adopts level shifting circuit 10 or 20 as level shift part 31, so can prevent leakage current.Therefore, can reduce power consumption, and, can realize that the power consumption of active array type liquid crystal display 50 reduces.
Particularly, can guarantee the circuit operation realization in the place that is used as supply voltage generation circuit 54 according to the supply voltage generation circuit 40 of using 2.In addition, because supply voltage generation circuit 54 portion within it produces reset pulse " rst " and needn't receive reset pulse " rst " from the outside of display panels 58, therefore, benefit needn't provide exactly and be specifically designed to the terminal that receives reset pulse " rst ".
Should be noted that, in above-mentioned Application Example, although the negative supply voltage that is produced by supply voltage generation circuit 54 is supplied to vertical driver 52, but the object that provides negative supply voltage is not limited to vertical driver 52, and can be any peripheral drive circuit that needs negative supply voltage.In addition, supply voltage generation circuit 54 is not limited to produce the circuit of negative supply voltage, and can form another circuit that alternately produces positive voltage.
In addition, in above-mentioned Application Example, although supply voltage generation circuit 30 or 40 is applied to the liquid crystal display as the photoelectric cell of pixel of liquid crystal cells wherein, supply voltage generation circuit 30 or 40 application are not limited to be used for liquid crystal display.Especially, supply voltage generation circuit 30 or 40 can be applicable to universal display equipment, wherein, adopts the drive circuit formation of negative supply voltage to form on the plate of pixel array portion thereon.The embodiment of this display equipment is EL (electroluminescence) display device, and wherein EL element is as the photoelectric cell of pixel.
[the 3rd embodiment]
Figure 15 illustrates the circuit structure according to the shift circuit of third embodiment of the invention.With reference to Figure 15, shift circuit 10 comprises level shift part 11 and control impuls generation part 12.
When the control impuls NSW that supplies with from control impuls generation part 12 is in effective status, level shift part 11 with clock pulse CK from the VSS-Vin amplitude (for example, 0 to 3V) level shift to the VSS-VDD amplitude (for example, 0 to 8V), and the clock pulse CK that exports this level shift is as output pulse OUT.Should be noted that the high voltage Vin of clock pulse CK is higher than transistorized threshold level Vth (VDD＞Vin＞Vth) be necessary.Control impuls generation part 12 only produces the pulse that shows effective status in a period of time of the one-period of clock pulse CK, and this pulse is fed to level shift part 11 as control impuls NSW.
Figure 16 illustrates clock pulse CK, the input pulse IN of control impuls generation part 12, control impuls NSW, the anti-phase control impuls PSW of control impuls NSW, and level relationship and the sequential relationship of output pulse OUT.
The specific circuit architecture of level shift part 11 and control impuls generation part 12 will be described respectively below.At first, level shift part 11 is described.
[form 1 of level shift part 11]
Figure 17 shows the structure according to level shift part (LS1) 11A of form 1.With reference to Figure 17, comprise complementary circuit 21, the first to the 3rd switching circuits 22 to 24, capacity cell Cap, and buffer 25 according to the level shift part 11A of form 1.Level shift part 11A has clock end 26, control end 27, and output 28.
First switching circuit 22 is formed by nmos pass transistor n12, and its drain electrode is connected to clock end 26, and its source electrode is connected to the grid of nmos pass transistor n11, and its grid is connected to control end 27.Clock end 26 receives the clock pulse (CK) of VSS-Vin amplitude (for example, 0 to 3V) as its input.Control end 27 receives the control impuls NSW that is produced by control impuls generation part 12 and imports as it, makes it show effective status (high voltage=supply voltage VDD) in a period of time of the one-period of clock pulse CK.
The 3rd switching circuit 24 is by between the canopy utmost point that is connected supply voltage VDD and nmos pass transistor n11 and be used to receive control impuls NSW and form as the PMOS transistor p15 of its grid input.When control impuls NSW showed as effective status, the 3rd switching circuit 24 showed as off state, the electrical connection between the canopy utmost point of wherein cut off the power supply source voltage VDD and nmos pass transistor n11.
Capacity cell Cap is connected between the grid of clock end 26 and nmos pass transistor n11.Therefore, clock pulse CK is delivered to the grid of PMOS transistor p11 by the coupling of capacity cell Cap.
Now, with reference to Figure 18 the circuit operation according to the level shift part 11A of form 1 with said structure is described.
At first, when control impuls NSW had low-voltage (supply voltage VSS), nmos pass transistor n12 showed as off state, and PMOS transistor p12 and p13 show as conducting state.Therefore, no matter what the logic state of clock pulse CK is, the voltage VA of node A (grid of PMOS transistor p11) and the voltage VB of another Node B (grid of nmos pass transistor n11) equal supply voltage VDD.Therefore, PMOS transistor p11 turn-offs and nmos pass transistor n11 conducting, and therefore, output pulse OUT equals supply voltage VSS.
When control impuls NSW has high voltage (supply voltage VDD), that is, when level shift part 11A was in driving condition, nmos pass transistor n12 showed as conducting state and PMOS transistor p12 and p13 and shows as off state.Therefore, node A shows as floating dummy status and is coupled to clock pulse CK by capacity cell Cap.Clock pulse CK is applied on the Node B by nmos pass transistor n12.
At this, control impuls NSW only shows as effective status (high voltage) in a period of time in the one-period of clock pulse CK, and level shift part 11A only the one-period of clock pulse CK during this period of time in be driven.This section in the period clock amplitude on Node B be VSS/Vin, and the clock amplitude on the node A is VDD-Vin/VDD.In addition, the clock that is applied to node A and B has identical phase place.
Therefore, in the moment that PMOS transistor p11 and nmos pass transistor n11 will turn-off, according to voltage VA on node A and B and the relation of VB, they guarantee to be placed in off state.Therefore, but by complementary circuit 21 level shifts (level conversion) the clock pulse CK that PMOS transistor p11 and nmos pass transistor n11 form is the output pulse OUT of VSS-VDD amplitude, and the leakage that MOS transistor p 11 and n11 are produced when guaranteeing to turn-off simultaneously is prevented.
As mentioned above, (it with VSS-Vin (for example for level shift part 11A, 0 to 3V) the clock pulse CK level shift of amplitude is VSS-VDD (for example, 0 to 8V) output pulse OUT), adopts by nmos pass transistor n11 and the formed complementary circuit 21 of PMOS transistor p11 as its basic circuit.In addition, when level shift part 11A will be actuated to realize level shift, clock pulse CK is applied to the grid of nmos pass transistor n11, simultaneously by the coupling of capacity cell Cap relatively shift clock pulse CK be applied to the grid of PMOS transistor p11 to the resulting clock pulse of supply voltage VDD side.Therefore, therein the moment that will turn-off of nmos pass transistor n11 and PMOS transistor p11, they will guarantee to place off state.Therefore, electric leakage does not flow to complementary circuit 21.
Because leakage current does not flow to level shift part 11A by this way, reduces so can reckon with the power consumption of shift circuit 10.In addition, because the complementary circuit 21 that is formed by the transistor of conductivity type opposite is as basic circuit, so there is not leakage current to cross and shift circuit 10 is driven in transistorized saturation region always.Therefore, can realize level shift part 11A like this, promptly its can favourable antagonism such as level shift circuit of the prior art in the transistor characteristic (threshold level Vth, the drain-source current Ids that are seen, or the like) in diffusion, adopt current mirror circuit as basic circuit in the prior art.That is, the circuit performance of level shift part 11A is not subjected to the appreciable impact of transistor characteristic diffusion.In addition, do not occur owing between supply voltage VDD and clock pulse CK, leak, so the load on the clock pulse can reduce.
Yet, use is according to the circuit structure of the level shift part 11A of form 1, possiblely be, also have as control impuls NSW when low-voltage and node A be fixed as supply voltage VDD that the coupling of clock pulse CK may exert an influence to node A by capacity cell Cap.Possible is that the voltage VA on the node A may fluctuate owing to the influence of coupling, and the fluctuation of voltage may be as for example must appearing on the output pulse OUT by the shape noise.Improved in this circuit structure is the following level shift part 11B according to form 2.
[form 2 of level shift part 11]
Figure 19 shows the structure according to level shift part (LS2) 11B of form 2.
With reference to Figure 19, except that element, also have the 4th switching circuit 31 and the 5th switching circuit 32 according to the level shift part 11A of form 1 according to the level shift part 11B of this form 2.The 4th switching circuit 31 is by between the end that is connected clock end 26 and capacitor Cap and be used to receive control impuls NSW and form as the nmos pass transistor n13 of its grid input.The 5th switching circuit 32 is by between the end that is connected voltage end 33 and capacity cell Cap and be used to receive control impuls NSW and form as the PMOS transistor p14 of its grid input.Voltage end 33 receives fixed voltage Vin and imports as it.
Now, with reference to Figure 20 the circuit operation according to the level shift part 11B of form 2 with said structure is described.The basic circuit operation of level shift part 11B is identical with the level shift part 11A according to form 1.Therefore, the 4th and the 5th switching circuit 31 increase newly and 32 operating principle are described.
In the 4th switching circuit 31, nmos pass transistor n13 shows as conducting state, and provides clock pulse CK to node C (end of capacity cell Cap) when control impuls NSW is in effective status (high voltage=supply voltage VDD).Yet when control impuls NSW was in disarmed state (low-voltage=supply voltage VSS), nmos pass transistor n13 showed as the electrical connection between off state and interrupt clock end 26 and the capacity cell Cap, made that clock pulse CK can be not influential to node A.
On the other hand, in the 5th switching circuit 32, PMOS transistor p14 shows as off state, and the electrical connection between interrupt voltage end 33 and the node C when control impuls NSW is in effective status.On the other hand, when control impuls NSW was in disarmed state, the 5th switching circuit 32 showed as conducting state to be electrically connected voltage end 33 and node C, so that the voltage VC on the node C is fixed as fixed voltage Vin.
As mentioned above, at the level shift part 11B according to form 2, when control impuls NSW was in disarmed state, the electrical connection between clock end 26 and the node C was interrupted and voltage VC is fixed as fixed voltage Vin.Therefore, the coupling that can prevent clock pulse CK exerts an influence to node A by capacity cell Cap.Therefore, the palpus shape noise owing to the fluctuation of the voltage VA on the node A causes can be prevented from appearing on the output pulse OUT.
At this, detect the conducting resistance of nmos pass transistor n12 and n13.Nmos pass transistor n12 and n13 are for to make that when control impuls NSW is in effective status clock pulse CK is provided to the switch of Node B and C.Because the service time section of clock pulse CK is corresponding to the one-period of clock pulse CK, so switching circuit 22 and 31 must have high side voltage Vin and the downside voltage VSS of enough capacity so that clock pulse CK to be provided.Yet if switching circuit 22 and 31 is made up of nmos pass transistor n12 or n13 respectively itself, the conducting resistance of nmos pass transistor n12 or n13 is higher at the high side voltage Vin of clock pulse CK with respect to the supply voltage VDD of conducting state so.
Now, detect the coupling of grid leak or grid source.When the state of control impuls NSW when effective status (supply voltage VDD) is changed into disarmed state (supply voltage VSS), canopy leaks coupling or the coupling action of grid source.The noise that enters by coupling may cause misoperation like this.
The sort circuit structure is the improvement of making about the possible situation of the conducting resistance of nmos pass transistor n12 and n13 and grid leak or the coupling of grid source, is the level shift part 11C according to form 3.
Shown in Figure 21 wherein according to the level shift part 11B of form 2 as the structure of the shift circuit 10 of level shift part 11 as shift circuit 11A according to the distortion 1 of the 3rd embodiment.
[form 3 of level shift part 11]
Figure 22 illustrates the structure according to level shift part (LS3) 11C of form 3.
With reference to Figure 22, be with difference according to the level shift part 11B of form 2 according to the level shift part 11C of form 3: cmos switch is used for switching circuit 22,23, and 24,31 and 32.Particularly, switching circuit 22 is made up of nmos pass transistor n21 that is connected in parallel with each other and PMOS transistor p21, and be applied to the grid of nmos pass transistor n21 by the control impuls NSW of control end 27 input, be applied to the grid of PMOS transistor p21 simultaneously by control end 34 inputs and the phase place anti-phase control impuls PSW opposite with control impuls NSW.
The 4th switching circuit 31 is made up of nmos pass transistor 24 that is connected in parallel with each other and PMOS transistor p24, and positive control impuls NSW is applied to the grid of nmos pass transistor n24, and anti-phase control impuls PSW is applied to the grid of PMOS transistor p24 simultaneously.Switching circuit 32 is made up of nmos pass transistor n25 that is connected in parallel with each other and PMOS transistor p25, and anti-phase control impuls PSW is applied to the grid of nmos pass transistor n25, and the control impuls NSW of opposite phase is applied to the grid of PMOS transistor p25 simultaneously.
Figure 23 illustrates the circuit operation according to the level shift part 11C of form 3.The anti-phase control impuls PSW of control impuls NSW and opposite phase is applied on the level shift part 11C of this form 3.
As mentioned above, in level shift part 11C according to form 3, cmos switch is used to form switching circuit 22 and 31, be used to form switching circuit 22 and at 31 o'clock (promptly at single nmos pass transistor about the possible situation of the conducting resistance of nmos pass transistor, conducting resistance compares in the high possibility of supply voltage VDD at the high side voltage Vi of clock pulse CK under the transistor turns state), can eliminate by the action of PMOS transistor p21 and p24.
In addition, because switching circuit 23,24 and 32 are made up of cmos switch respectively, at switching circuit 23, the possible situation of 24 and 32 couplings of grid leak when forming by single nmos pass transistor respectively or the coupling of grid source (, circuit is owing to the noise that coupling causes enters and the possibility of fault), can be by PMOS transistor p22, p23 and p25 move and eliminate.
Should be noted that, in form 3, although switching circuit 22,23,24, whether 31 and 32 are made up of cmos switch respectively and eliminate above-mentioned possibility, but needn't make requirement to the countermeasure of eliminating, and can select take some countermeasures by the necessity that detects the countermeasure of the described possibility of antagonism situation according to circuit constant and drive condition (various voltage setting value).
Shown in Figure 24 wherein according to the level shift part 11C of form 3 as the structure of the shift circuit 10 of level shift part 11 as shift circuit 10B according to the distortion 2 of the 3rd embodiment.
Now, description control pulse generation part 12, it produces control impuls NSW (anti-phase control impuls PSW).
This control impuls NSW is the pulse signal that shows effective status (high voltage) in a period of time of above-mentioned one-period at clock pulse CK.Two kinds of methods of following this can be used as the method that produces control impuls NSW.
In the description subsequently of these methods, presuppose each shift stages (shifting level) that for example is used for shift-register circuit according to the shift circuit 10 of present embodiment.First method adopts the input and output of every grade of shift-register circuit.It is described as embodiment 1.Second method adopts the every grade of input of shift register and the output of next stage.Second method is described as embodiment 2,3 and 4.
[embodiment 1 of control impuls generation part 12]
Figure 25 illustrates the structure according to the control impuls generation part 12A (APga) of embodiment 1.
With reference to Figure 25, the control impuls generation part 12A of embodiment 1 comprises NOR circuit 41, inverter circuit 42,43, two inputs 44 of reset circuit and 45, two outputs 46 and 47, and reset terminal 48.The input pulse IN1 that input 44 received pulse width equal clock pulse CK imports as it.Input pulse IN1 is corresponding to the input pulse of the shift register corresponding levels.The input pulse IN2 in 1/2 cycle of input 45 receptions and input pulse IN1 phase shifted clock pulse CK imports as it.Input pulse IN2 is corresponding to the output pulse of the shift register corresponding levels.
NOR circuit 41 logic OR input pulse IN1 and input pulse IN2.The output pulse of inverter circuit 42 anti-phase NOR circuit 41 is with the control impuls NSW of generation positive and by output 46 output control pulse NSW.The output pulse of NOR circuit 41 when its during as the control impuls PSW of positive by output 47 outputs.Anti-phase control impuls PSW is that place according to the level shift part 11C of embodiment 3 is needs in level shift part 11.Figure 26 illustrates the sequential relationship of input pulse IN1 and IN2 and control impuls NSW and PSW.
Figure 27 illustrates an embodiment of NOR circuit 41 structures.With reference to Figure 27, NOR circuit 41 is made up of PMOS transistor p31 and p32 and nmos pass transistor n31 and n32 in the present embodiment.PMOS transistor p31 and p32 are connected in series between supply voltage VDD and output node " Nout " and are used for receiving respectively input pulse IN1 and IN2 as its grid input.Nmos pass transistor n31 and n32 are connected in parallel between output node " Nout " and supply voltage VSS and are used for receiving respectively input pulse IN1 and IN2 as its grid input.Yet the structure of NOR circuit 41 is not limited to described above.
Figure 28 illustrates an embodiment of inverter circuit 42 structures.With reference to Figure 28, inverter circuit 42 has the CMOS inverter structure.This structure comprises and is connected in series between supply voltage VDD and the supply voltage VSS and its grid and the drain electrode public each other PMOS transistor p33 that is connected and nmos pass transistor n33.Yet the structure of inverter circuit 42 is not limited to described above.
Control impuls generation part 12A among the embodiment 1 is used as the shift circuit 10 according to the 3rd embodiment (Figure 15), according to the shift circuit 10A of distortion 1 (Figure 21), and according to the control impuls generation part 12 among the shift circuit 10B of distortion 2 (Figure 24).
[embodiment 2 of control impuls generation part 12]
Figure 29 illustrates the structure that part (APGb1) 12B1 takes place according to the control impuls of embodiment 2.
With reference to Figure 29, comprise change-over circuit 51 according to the control impuls generation part 12B1 of embodiment 2, latch cicuit 52,53, two inputs 54 of reset circuit and 55, two outputs 56 and 57, and reset terminal 58.The input pulse PRIN that input 54 received pulse width equal clock pulse CK imports as it.Input pulse PRIN is corresponding to the input pulse of the shift-register circuit corresponding levels.Input 55 receives the input pulse NXIN with input pulse IN1 (PRIN) clock pulse CK cycle of phase shift.This input pulse NXIN is corresponding to the output pulse of next stage in the shift-register circuit.
Change-over circuit 51 comprises PMOS transistor p41 and the nmos pass transistor n41 that is connected in series between supply voltage VDD and the supply voltage VSS, and inverter circuit 511.Input pulse PRIN at it by the inverter circuit 511 anti-phase after-applied canopy utmost points to PMOS transistor p41.Input pulse NXIN is applied directly to the grid of nmos pass transistor n41.Change-over circuit 51 response input pulse PRIN/NXIN carry out the conversion of control impuls NSW between downside voltage VSS and high side voltage VDD.
The output end voltage of change-over circuit 51 when its during as the control impuls NSW of positive from output 56 outputs, and export as anti-phase control impuls PSW from output 57 by latch cicuit 52.Anti-phase control impuls PSW is that place according to the level shift part 11C of embodiment 3 is needs in level shift part 11.The sequential relationship of input pulse PRIN and NXIN and control impuls NSW and PSW is shown in Figure 30.
In above-mentioned control impuls generation part 12B1 according to embodiment 2, because it has the structure that adopts latch cicuit 52, whenever conversion occurring between the downside voltage VSS of control impuls NSW and high side voltage VDD, the conflict between the output of the output of change-over circuit 51 and latch cicuit 52 appears on the output and the holding wire between the output 56 of change-over circuit 51.Thus, in order to realize level and smooth conversion, the output of change-over circuit 51 must be higher than the output of latch cicuit 52.Therefore, in the design of control impuls generation part 12B1, must consider that above-mentioned necessity is to determine circuit constant.
In order to realize the stabilized driving of control impuls generation part 12, preferably avoid the conflict between the output of the output of change-over circuit 51 and latch cicuit 52.Avoid the circuit structure of this conflict between the output of the output of change-over circuit 51 and latch cicuit 52 to be included among the control impuls generation part 12B2 and 12B3 according to embodiment 3 and 4.
[embodiment 3 of control impuls generation part 12]
Figure 31 illustrates the structure that part (APGb2) 12B2 takes place according to the control impuls of embodiment 3.
With reference to Figure 31, outside the element of digging up the roots, comprise the switching circuit 59 between the output of the output that is inserted in change-over circuit 51 and latch cicuit 52 according to the control impuls generation part 12B1 of embodiment 3 according to the control impuls generation part 12B1 of embodiment 2.
In control impuls generation part 12B2 with said structure according to embodiment 3, it is non-that input pulse PRIN and NXIN carry out logic OR by NOR circuit 591, and the output of the output of change-over circuit 51 and latch cicuit 52 is by electrical control, so that be connected to each other or disconnect based on the non-result of described logic OR.By means of this control, when between the downside voltage VSS of control impuls NSW and high side voltage VDD, conversion occurring, just can prevent other potentially conflicting between the output of the output of change-over circuit 51 and latch cicuit 52.Figure 32 illustrates input pulse PRIN and NXIN, voltage VA and VB on node A and the B, and the sequential relationship between control impuls NSW and the PSW.
[embodiment 4 of control impuls generation part 12]
Figure 33 illustrates the structure that part (APGb3) 12B3 takes place according to the control impuls of embodiment 4.
With reference to Figure 33, control impuls generation part 12B3 according to embodiment 4 constructs like this, it is included in two switching circuit 59A and the 59B that is connected in series between the output of the output of change-over circuit 51 and latch cicuit 52, replaces the switching circuit 59 according to the control impuls generation part 12B2 of embodiment 3.
Switching circuit 59A is by comprising that the nmos pass transistor n43 that is connected in parallel with each other and the cmos switch of PMOS transistor p43 form.Input pulse NXIN at it by inverter circuit 592 anti-phase after-applied grids to nmos pass transistor n43.In addition, input pulse NXIN is directly inputted to the grid of PMOS transistor p43.
Switching circuit 59B is by comprising that the nmos pass transistor n44 that is connected in parallel with each other and the cmos switch of PMOS transistor p44 form.Input pulse PXIN at it by inverter circuit 511 anti-phase after-applied grids to nmos pass transistor n44.In addition, input pulse PXIN is applied directly to the grid of PMOS transistor p44.
In the control impuls generation part 12B3 with said structure according to embodiment 4, two switching circuit 59A and 59B are connected in series between the output of the output of change-over circuit 51 and latch cicuit 52 and by input pulse NRIN and input pulse PXIN and carry out conducting/shutoff control.Therefore, when between the downside voltage VSS of control impuls NSW and high side voltage VDD, conversion occurring, just can prevent between the output of the output of change-over circuit 51 and latch cicuit 52, other possible conflict to occur.
Equally, 12B is (according to embodiment 2 for control impuls generation part, 3, with 4 control impuls generation part 12B1,12B2, and 12B3) (it adopts the method for utilizing in the above-mentioned register circuit that the corresponding levels are imported and next stage is exported), can be similar to control impuls generation part 12A as the control impuls generation part 12 in the shift circuit 10, in control impuls generation part 12A, in shift register, adopt the method for utilizing input at the corresponding levels and output at the corresponding levels.
The shift circuit as control impuls generation part 12 of control impuls generation part 12B wherein is described below.Particularly, shown in Figure 34 wherein according to the level shift part 11A of embodiment 1 as the structure of the shift circuit 10 of level shift part 11 as shift circuit 10C according to the distortion 3 of the 3rd embodiment; Shown in Figure 35 wherein according to the level shift part 11B of embodiment 2 as the structure of the shift circuit 10 of level shift part 11 as shift circuit 10D according to the distortion 4 of the 3rd embodiment; And shown in Figure 36 wherein according to the level shift part 11C of embodiment 3 as the structure of the shift circuit 10 of level shift part 11 as shift circuit 10E according to the distortion 5 of the 3rd embodiment.
According to the shift circuit 10C of distortion 3,4 and 5, the employed clock pulse CK of 10D and 10E, input pulse PRIN and NXI, control impuls NSW and PSW, and the sequential relationship of output pulse OUT is shown among Figure 37.
Should be noted that, although be according to distortion 4 and 5 shift circuit 10D and 10E and according to the difference of the shift circuit 10C of embodiment 3: fixed voltage Vin is applied to level shift part 11B and 11C, but the meaning of above-mentioned application fixed voltage Vin is as the level shift part 11B given description of top combination according to embodiment 2, and shift circuit 10C, 10D carries out identical basic operation with 10E.
In addition, although according to embodiment 2,3 and 4 control impuls generation part 12B1,12B2 and 12B3 use as control impuls generation part 12B, but because its basic operation is identical, therefore with according to three kinds of forms that combine of the control impuls generation part 12B of embodiment 2,3 and 4 and level shift part 11A, 11B and 11C as mentioned above.Yet, in fact, according to embodiment 2, but 3 and 4 control impuls generation part 12B1,12B2 and 12B3 and according to level shift part 11A, 11B and the 11C combination with one another of embodiment 1,2 and 3, and therefore, nine kinds of compound modes can appear altogether.
Each that be can be used as the general shift circuit with level shift function and be can be used as shift-register circuit by the formed shift circuit 10 of various compound modes (10A, 10B, 10C, 10D and 10E) of level shift part 11 (11A, 11B and 11C) and control impuls generation part 12 (12A, 12B1,12B2 and 12B3) shifts level (shift stages).Subsequently, the application that wherein is used for each shift stages of shift register according to the shift circuit 10 (10A, 10B, 10C, 10D or 10E) of first embodiment is described.
[using 3]
Figure 38 illustrates the structure of using 3 shift-register circuit according to the present invention.With reference to Figure 38, comprise that connect as the cascade shift stages, a plurality of according to the shift-register circuit 61A that uses 3 according to the shift circuit 10 of the 3rd embodiment or according to the distortion 1 of the 3rd embodiment or 2 shift circuit 10A or 10B.Clock pulse CK and inversion clock pulse xCK alternately are applied to and shift level, and the inceptive impulse ST of triggering shifting function is applied on first shift stages as input pulse IN.In addition, each shifts output pulse OUT on the level as the input pulse IN of next stage, and this output pulse OUT is as shifting pulse o1, o2, and o3 ... draw.
In addition, show as the reset pulse " rest " of high voltage (supply voltage VDD) and fixed voltage Vin in the driving process is applied to and shifts on the level always jointly.Yet, be used for the place that each shifts level at shift circuit 10 according to first embodiment, needn't apply fixed voltage Vin.Figure 39 illustrates clock pulse CK and xCK, inceptive impulse ST, and the control impuls NSW on first and second grades, and shift transfer pulse o1 on the level, and o2, o3, o4 ... sequential relationship.
[using 4]
Figure 40 illustrates the structure of using 4 shift-register circuit according to the present invention.With reference to Figure 40,, 2N (N be natural number) level (even level) that cascade connects according to comprising with 4 shift-register circuit 61B according to the shift circuit 10C of the distortion 3 to 5 of the 3rd embodiment to 10E.Clock pulse CK and inversion clock pulse xCK alternately are applied to and shift on the level, and input pulse PRIN and inceptive impulse ST are applied on first shift stages.In addition, shift on the level at each, output pulse OUT at the corresponding levels is as the input pulse PRIN of next stage, and this output pulse OUT is as shifting pulse o1, o2, and o3 ... draw.
In addition, being usually expressed as the reset pulse " rest " of low-voltage (supply voltage VSS) and fixed voltage Vin in the driving process is applied to jointly and shifts on the level.Yet the place that is used to shift level therein according to the shift circuit 10C of distortion 3 needn't apply fixed voltage Vin.
Figure 41 illustrates clock pulse CK and xCK, inceptive impulse ST, and the first, the second and the control impuls NSW of 2N level, shift output pulse (transfer pulse) o1 of level, o2, o3 ..., and o2N, and the sequential relationship that finishes pulse ED.
[using 5]
Figure 42 illustrates the structure of using 5 shift-register circuit according to the present invention.With reference to Figure 42, according to the shift-register circuit 61C that uses 5 comprise that the individual cascade of 2N-1 (odd number) connects according to the shift circuit 10C of the distortion 3 to 5 of the 3rd embodiment to 10E, and be according to the difference of using 4 shift-register circuit 61B: the progression that shifts grade is that the progression of the transfer level of odd number and shift-register circuit 61B is even number.
Figure 43 illustrates clock pulse CK and xCK, inceptive impulse ST, the first, the second and the 2N-1 level on control impuls NSW, shift output pulse (transfer pulse) o1 on the level, o2, o3..., and o2N-1, and the sequential relationship that finishes pulse ED.
[using 6]
Figure 44 illustrates the structure of using 6 shift-register circuit according to the present invention.With reference to Figure 44, according to should comprising that 2N is shifted level (even level) and adopt the shift circuit 10C according to the distortion 3 to 5 of the 3rd embodiment to shift level to 10E as first to 2N-1 with 6 shift-register circuit 61D, but adopt according to the shift circuit 10 of the 3rd embodiment or according to the shift circuit 10A of the distortion 1 of shift circuit 10 or 2 or 10B as last transfer grade (a 2N level).
Owing to be arranged to last transfer level according to the shift circuit 10 of the 3rd embodiment or according to the distortion 1 of the 3rd embodiment or 2 shift circuit 10A or 10B, so its benefit is to have eliminated from outside finishing the necessity that pulse ED is provided to last transfer level.Although embodiment described herein comprises even number and shifts level, number in the transfer level is the place (Figure 42) of odd number equally, is provided with according to the shift circuit 10 of the 3rd embodiment or according to the distortion 1 of the 3rd embodiment or 2 shift circuit 10A or 10B also to be fine as last transfer level.
[using 7]
Figure 45 illustrates the structure of using 7 shift-register circuit according to the present invention.With reference to Figure 45, construct like this according to the shift-register circuit 61E that uses 7, according to the distortion 3,4 of the 3rd embodiment, or 5 shift circuit 10C connects to 2N level (even level) cascade of 10E, and supply voltage VSS replaces finishing pulse ED and is applied to last and shifts on the level.In addition, shift-register circuit 61E also comprises TRN circuit 62.
If replacing finishing pulse ED, supply voltage VSS is input to last transfer level, so in case by according to the shift circuit 10C of the distortion 3 to 5 of the 3rd embodiment when the formed control impuls NSW that shifts on the level of 10E becomes high voltage, shift level and serve as level shift circuit till they are reset.Therefore, the output o2N on the afterbody has from the waveform of clock pulse CK level shift.Therefore, it is important that TRN circuit 62 is provided, so that produce the control impuls NSW of the 2N-1 level that is used for normal waveform.In addition, replace to finish the place that pulse ED uses at inceptive impulse ST, afterbody inceptive impulse ST at every turn becomes ST=height (afterbody is only serving as level shifter from the o2N-1=height in the time period high to ST=) time and resets.In this case, do not need TRN circuit 62.
Figure 46 illustrates clock pulse CK and xCK, inceptive impulse ST, the first, the second and the 2N-1 level on control impuls NSW, and shift output pulse (transfer pulse) o1 on the level, o2, o3 ..., and the sequential relationship of o2N-1.
Figure 47 illustrates an embodiment of the structure of TRN circuit 62.Figure 48 illustrates input pulse IN, control impuls CNT, and the sequential relationship of output pulse OUT.
With reference to Figure 47, the TRN circuit 62 of illustrated embodiment comprises PMOS transistor p51 and the nmos pass transistor n51 that is connected in series between input 621 and the supply voltage VSS.The grid of PMOS transistor p51 and nmos pass transistor n51 is connected jointly and is connected to control end 622, and the drain electrode of PMOS transistor p51 and nmos pass transistor n51 is connected jointly and is connected to output 623.TRN circuit 62 also comprises the nmos pass transistor n52 that is connected in parallel with PMOS transistor p51, and is used for anti-phase and applies the inverter circuit 624 of control impuls CNT to the grid of nmos pass transistor n52.
Therefore, in shift-register circuit 61E, be out of shape 3 to 5 shift circuit 10C according to the 3rd embodiment and go up cascade to 10E in 2N level (even level) and connect.TRN circuit 62 is arranged on last and shifts near the level, and supply voltage VSS is applied on last transfer level by this way.Its benefit is to have eliminated to be applied to last and to shift necessity on the level finishing pulse ED.
Should be noted that, although embodiment described herein comprises even number and shifts level, be the place of odd number shifting progression equally, shift near the level (2N-1 level) and supply voltage VSS is applied to the structure that last shifts level if adopt TRN circuit 62 wherein to be arranged on last, same operation and benefit can reckon with.
In addition, the shift-register circuit 61A that has described according to above-mentioned application produces the transfer pulse o1 that does not have blanking cycle therebetween to 61E, o2, and o3 ...Yet, shift-register circuit (its adopt according to the shift circuit 10C of the distortion 3 to 5 of the 3rd embodiment to 10E as shifting level), that is, can provide blanking cycle according to the shift-register circuit 61B of the application 4 of Figure 40 and according to the shift-register circuit 61E of the application 5 of Figure 45.By forming blanking cycle in moment of clock pulse CK as shown in the sequential chart of Figure 49 and 50 and xCK, blanking cycle just is set at and shifts between the pulse.
At this, a kind of Vin voltage generating circuit is described, be used to produce by according to using 3 to 7 shift-register circuit 61A to the employed fixed voltage Vin of 61E.
Can import from the outside to the fixed voltage Vin on the transfer level of 61E although will impose on according to the shift-register circuit 61A that uses 3 to 7, but because fixed voltage Vin is the high voltage of clock pulse CK and xCK, so fixed voltage Vin can be produced by the Vin voltage generating circuit 71 with the structure shown in Figure 51.
With reference to Figure 51, Vin voltage generating circuit 71 comprises the clock end 711 that is connected clock pulse CK input and the PMOS transistor p61 between the output 713, and is connected another clock end 712 of clock pulse xCK input and another PMOS transistor p62 between the output 713.Clock pulse xCK is applied to the grid of PMOS transistor p61, and clock pulse CK is applied to the grid of PMOS transistor p62.
The sequential relationship of the output OUT of clock pulse CK and xCK and fixed voltage Vin is shown in Figure 52.In addition, wherein the sequential relationship that is arranged between clock pulse CK and the xCK of blanking cycle is shown in Figure 53.Be arranged on place between clock pulse CK and the xCK at blanking cycle, fixed voltage Vin can be provided at the place except that blanking cycle.
A plurality of therein shift-register circuits that shift level (shift stages) cascade connection shift level for each and use by level shift part 11 (11A, 11B, or 11C) and control impuls generation part 12 (12A, 12B1,12B2, or 12B3) combining form formed shift circuit 10 (10A, 10B, 10C, 10D, or 10E) the place, electric leakage does not flow to level shift part 11 (11A, 11B, or 11C) and power consumption reduce.Therefore, the power consumption that can reckon with shift-register circuit reduces.
Can be used as general bit shifting register circuit use to 61E according to using 3 shift-register circuit 61A with level shift function to application 7.In addition, as an embodiment, shift-register circuit 61A to 61E can be used as with the display device of drive circuit integrated-type in be formed for the scanner of vertical driver or horizontal driver shift-register circuit use.In display device, the peripheral drive circuit that drives pixel array portion forms and is provided with thereon on the plate of pixel array portion, and wherein each comprises that the pixel of photoelectric cell is expert at and lists two-dimensional arrangements.
[Application Example 2]
Figure 54 illustrates an embodiment of the display device structure of the Application Example according to the present invention.Display device shown in Figure 54 forms the active array type liquid crystal display.Liquid crystal cells uses as the photoelectric cell of pixel.
With reference to Figure 54, according to should comprising pixel array portion 81 with the active array type liquid crystal display 80 of embodiment, vertical driver 82, horizontal driver 83, or the like.The peripheral drive circuit that comprises vertical driver 82 and horizontal driver 83 is formed on the liquid crystal board 84, on this LCD panel 84 pixel array portion 81 is set.Liquid crystal board 84 is constructed like this, for example as two insulating bases of glass film plates and so on the relativeness setting, reserve the fixed interval (FI) therebetween simultaneously, and liquid crystal material is sealed in this gap.
Has pixel 90 capable with m and that n row two dimension is provided with on the pixel array portion 81.In addition, on the active array of pixel 90, for every row arranges that scan line 85-1 is to 85-m and be that every row layout holding wire 86-1 is to 86-n.Each pixel 90 comprises TFT (thin-film transistor) 91 as pixel transistor, and pixel electrode is connected to the liquid crystal cells 92 of the drain electrode of TFT 91, and one electrode is connected to the maintenance capacitor 93 in the drain electrode of TFT 91.
In above-mentioned dot structure, TFT 91 grids of each pixel 90 are connected to scan line 85 (85-1 is to 85-m), and source electrode is connected to holding wire 86 (86-1 is to 86-n).Simultaneously, another electrode of the comparative electrode of liquid crystal cells 92 and maintenance capacitor 93 is connected on the common wire 87, and common electric voltage VCOM is applied on the common wire 87.
Vertical driver 82 is formed by shift-register circuit etc., and selects the pixel 90 of pixel array portion 81 with behavior unit.Horizontal driver 83 is by shift-register circuit, formation such as sampling switch, and be unit sequence ground (according to dot sequency) or simultaneously will be from the outside vision signal of importing of panel be written to pixel 90 by vertical driver 82 selected row with behavior unit sequence ground (according to the line order) with the pixel.
In having the active array type liquid crystal display 80 of said structure, use as at least one the shift-register circuit that forms in vertical driver 82 and the horizontal driver 83 to 61E according to the shift-register circuit 61A of above-mentioned application 1 to 5.
Be used as the place of the shift-register circuit that forms vertical driver 82 or horizontal driver 83 by this way to 61E at shift-register circuit 61A, owing to shift level for each, shift-register circuit 61A uses to 61E and comprises level shift part 11 (11A, 11B, or 11C) shift circuit 10 (it does not comprise leakage current and shows low-power consumption) is so shift-register circuit 61A low in energy consumption to 61E.The result is to realize that the power consumption of liquid crystal display 80 reduces.
In above-mentioned Application Example, the present invention is applied on the liquid crystal display as the photoelectric cell of pixel of liquid crystal cells wherein.Application of the present invention is not limited to liquid crystal display, and the present invention also may be used on the various display devices.The vertical driver or the horizontal driver that for example adopt shift-register circuit to form form onboard, form pixel array portion on this plate, and as the EL display device, wherein EL (electroluminescence) element is as the photoelectric cell of pixel.In addition, it may be used on comprising in the various devices of the scanner that adopts shift-register circuit formation.
[the 4th embodiment]
Figure 55 illustrates the structure according to the shift-register circuit of fourth embodiment of the invention.With reference to Figure 55, according to the shift-register circuit 10 of present embodiment comprise each other in to and the cascade first shift circuit 11-1 and the second shift circuit 11-2 that connect, and each other in to and cascade the 3rd shift circuit 11-3 and the 4th shift circuit 11-4 that connect.Two shift circuits are to alternately cascade connection.In other words, shift circuit 11-1 connects as the shift register cell (shifting level/shift stages) of cascade connection to 11-4, and a plurality of this four shift circuit 11-1 repeat to be provided with and the cascade connection to the 11-4 group.
As hereinafter describing in detail, the first shift circuit 11-1 has identical circuit structure with the second shift circuit 11-2, and the 3rd shift circuit 11-3 and the 4th shift circuit 11-4 have another circuit structure.The first clock pulse CK1 is applied to the first and the 3rd shift circuit 11-1 and 11-3, the CK2 of second clock pulse simultaneously is applied to the second and the 4th shift circuit 11-2 and 11-4, and the frequency of second clock pulse CK2 equals the frequency of the first clock pulse CK1 and has the phase shift in 1/4 cycle with the first clock pulse CK1.
The first order first shift circuit 11-1 receives the effective inceptive impulse ST of high level as its control impuls IN.When control impuls IN is in effective status (high voltage), shift circuit 11-1 extracts the low voltage side pulse (effectively low) of the first clock pulse CK1, this low voltage side pulse is displaced to second amplitude from first amplitude level, and exports the low voltage side pulse of this level shift.The high effectively output pulse OUT of shift circuit 11-1 is applied on the shift circuit 11-2 of the second level as control impuls IN.
When control impuls IN was in effective status, second level shift circuit 11-2 extracted the low voltage side pulse of second clock pulse CK2, this low voltage side pulse is displaced to second amplitude from first amplitude level, and exports the low voltage side pulse of this level shift.The high effectively output pulse OUT of shift circuit 11-2 is applied on the third level shift circuit 11-3 as control impuls IN.
When control impuls IN was in effective status, third level shift circuit 11-3 extracted the high-voltage side pulse of the first clock pulse CK1, and this high-voltage side pulse is displaced to second amplitude from first amplitude level, and exported the high-voltage side pulse of this level shift.The high effectively output pulse OUT of shift circuit 11-3 is applied on the fourth stage shift circuit 11-4 as control impuls IN.
When control impuls IN was in effective status, fourth stage shift circuit 11-4 extracted the high-voltage side pulse of second clock pulse CK2, this high-voltage side pulse is displaced to second amplitude from first amplitude level, and exports the high-voltage side pulse of this level shift.The high effectively output pulse OUT of shift circuit 11-4 is applied on the level V shift circuit 11-1 as control impuls IN.
After this, repeat the circuit operation of four shift circuit 11-1 equally to the combination of 11-4.
At shift circuit (shifting level) 11-1,11-2 ..., in, input pulse (control impuls) IN at the corresponding levels and output pulse OUT at the corresponding levels import AND circuit 12-1 as three, 12-2 ... two inputs.Compare the very little low effective enabling pulse EN of pulsewidth with the pulsewidth of clock pulse CK1 and CK2 and be applied to AND circuit 12-1 as a remaining input, 12-2 ...Then, AND circuit 12-1,12-2 ... high effectively output pulse shift the transfer pulse o1 of level as each, o2 ... draw.Should be noted that described enabling pulse EN can only use when it will provide blanking cycle between the transfer pulse.
Figure 56 clock pulse CK1 and CK2, enabling pulse EN, inceptive impulse ST, the output pulse SR_out on first and second grades are shown and shift pulse o1, o2, o3 ... sequential relationship.Obviously find out from the sequential chart of Figure 56, shift circuit 11-1,11-2 ... extract the clock pulse CK1 of first amplitude (VSS-Vin) and CK2 and level shift this clock pulse CK1 and CK2 to the transfer pulse o1 of second amplitude (VSS-VDD), o2, o3 ...
As mentioned above, in shift-register circuit 10 according to the 4th embodiment, the first shift circuit 11-1 and the second shift circuit 11-2 each other in to and cascade connect, simultaneously the 3rd shift circuit 11-3 and the 4th shift circuit 11-4 each other in to and cascade connect.Then, two such shift circuits connect cascade alternately, and the first clock pulse CK1 that has the phase shift of 1/4 cycle each other and second clock pulse CK2 alternately are applied to the repeated arrangement of this shift register cell (shift grade).Therefore, clock pulse CK1 that can be used for driving and the frequency of CK2 are lowered to 1/2 of employed clock pulse CK and xCK in the shift-register circuit of prior art, and the shift register cell of same circuits structure repeats to be provided with in the prior art.
Therefore, the load that is used to produce the clock generating circuit (not shown) of clock pulse CK1 and CK2 is kept to half.In addition, because driving frequency can be kept to half, so shift-register circuit 10 power consumptions own reduce.
Now, the ad hoc structure of first to the 4th shift circuit (shift register cell) 11-1 to 11-4 described.
Figure 57 illustrates an embodiment of the structure of shift circuit 11-1 and 11-2.With reference to Figure 57, to construct like this according to each the shift circuit 11-1 and the 11-2 of present embodiment, it comprises level shift part 20 and control impuls generation part 40.
When the control impuls NSW that applies from control impuls generation part 40 is in effective status, level shift part 20 with clock pulse CK from the VSS-Vin amplitude (for example, the 0-3V amplitude) level shift to the VSS-VDD amplitude (for example, 0 to the 8V amplitude), and the clock pulse CK that exports this level shift is as output pulse OUT.The input pulse of the control impuls generation part 40 reception corresponding levels is as an one input IN1 and receive output pulse OUT at the corresponding levels as its another input.Then, control impuls generation part 40 produces control impuls NSW and the PSW that phase place is opposite each other, is used for the drive condition based on input pulse IN1 and IN2 control level displacing part 20.
At this, the specific circuit architecture of level shift part 20 and control impuls generation part 40 is described.The circuit structure of level shift part 20 at first, is described.
Figure 58 illustrates an embodiment of the structure of level shift circuit (LS1) 20.With reference to Figure 58, comprise complementary circuit 21, the first to the 5th switching circuits 22 to 26, capacity cell Cap, and buffer 27 according to the level shift part 20 of present embodiment.Level shift part 20 also has clock end 28, control end 29 and 30, voltage end 31 and output 32.
First switching circuit 22 is by comprising that the nmos pass transistor n21 that is connected in parallel with each other and the cmos switch of PMOS transistor p21 form.Terminal of cmos switch is connected to clock end 28, and the other end is connected to the grid of nmos pass transistor n11.The grid of nmos pass transistor n11 and PMOS transistor p11 is connected respectively to control end 29 and 30.
Opposite control impuls NSW and the PSW of phase place each other that is produced by control impuls generation part 40 is fed to control end 29 and 30 respectively.Control impuls NSW is high effective impulse signal, and control impuls PSW is low effective impulse signal simultaneously.Fixing voltage Vref1 (for example, the high side voltage Vin of clock pulse CK1/CK2) is applied to voltage end 31.
The 3rd switching circuit 24 is by comprising that the nmos pass transistor n23 that is connected in parallel with each other and the cmos switch of PMOS transistor p23 form.Cmos switch one end is connected to the grid that supply voltage VDD and its other end are connected to nmos pass transistor n11.The canopy utmost point of nmos pass transistor n23 and PMOS transistor p23 is connected respectively to control end 29 and 30.When control impuls NSW and PSW were in effective status, the 3rd switching circuit 24 showed off state, with the electrical connection between the canopy utmost point that interrupts supply voltage VDD and nmos pass transistor n11, thereby the grid of nmos pass transistor n11 was placed floating dummy status.
The 4th switch 25 is by comprising that the nmos pass transistor n24 that is connected in parallel with each other and the cmos switch of PMOS transistor p24 form.Cmos switch one end is connected to the end that clock end 28 and its other end are connected to capacity cell Cap.The grid of nmos pass transistor n24 and PMOS transistor p24 is connected respectively to control end 29 and 30.When control impuls NSW and PSW were in effective status, the 4th switching circuit 25 showed conducting state, so that can be fed to clock pulse CK the end of capacity cell Cap.Yet when control impuls NSW and PSW were in disarmed state, the 4th switching circuit 25 showed as the electrical connection between off state and interrupt clock end 28 and capacity cell Cap one end.
The 5th switching circuit 26 is by comprising that the nmos pass transistor n25 that is connected in parallel with each other and the cmos switch of PMOS transistor p25 form.Cmos switch one end is connected to the end that voltage end 31 and the other end are connected to capacity cell Cap.Anti-phase control impuls PSW is applied to the grid of nmos pass transistor n25, and the control impuls NSW of positive is applied to the grid of PMOS transistor p25 simultaneously.When control impuls NSW and PSW were in effective status, the 5th switching circuit 26 showed as off state, with the electrical connection between interrupt voltage end 31 and capacity cell Cap one end.Yet when control impuls NSW and PSW were in disarmed state, the 5th switching circuit 26 showed as conducting state and is electrically connected the end of voltage end 31 and capacity cell Cap.
Capacity cell Cap is connected between the grid of the other end of the 4th and the 5th switching circuit 25 and 26 and nmos pass transistor n11.Therefore, when the 4th switching circuit 25 was in conducting state, clock pulse CK was applied to the end of capacity cell Cap by switching circuit 25 and is delivered to the grid of PMOS transistor p11 by the coupling of capacity cell Cap.
The circuit operation of the level shift part 20 with said structure is described with reference to Figure 59 now.
At first, when control impuls NSW and PSW were in disarmed state, the first and the 4th switch 22 and 25 had off state, and the second, the three and the 5th switch 23,24 and 26 has conducting state simultaneously.Therefore, voltage VA on the node A (grid of PMOS transistor p11) and the voltage VB on another Node B (grid of nmos pass transistor n11) equal supply voltage VDD, and no matter the logic state of clock pulse CK (CK1/CK2).Therefore, because PMOS transistor p11 places off state and nmos pass transistor n11 to place conducting state, therefore exporting pulse OUT has supply voltage VSS.
When control impuls NSW and PSW are in effective status, that is, when level shift part 20 was in driving condition, the first and the 4th switch 22 and 25 had conducting state and the second, the three and the 5th switch 23,24 and 26 has off state.Therefore, node A places floating dummy status and is coupled to clock pulse CK by capacity cell Cap.Clock pulse CK is applied on the Node B by first switching circuit 22.
In the effective period of control impuls NSW and PSW, carry out the process of the low voltage side pulse (that is effectively low pulse) of extracting clock pulse CK (CK1/CK2) and another process that clock pulse CK is displaced to the VSS-VDD amplitude from the VSS-Vin amplitude level.
In addition, the clock amplitude on the effective period of control impuls NSW and PSW interior nodes B is VSS/Vin, and the clock amplitude on the node A is VDD-Vin/VDD, and is applied to node A in addition and has identical phase place with clock on the Node B.Therefore, in the moment that PMOS transistor p11 and nmos pass transistor n11 will turn-off, according to voltage VA on node A and B and the relation of VB, their are guaranteed to place off state.Therefore, in the complementary circuit 21 that forms by PMOS transistor p11 and nmos pass transistor n11, can guarantee to prevent the leakage when MOS transistor p11 and n11 are in off state.
As mentioned above, with VSS-Vin (for example, 0 to 3V) the clock pulse CK level shift of amplitude comprises to the level shift part 20 of the output pulse OUT of VSS-VDD (for example, 0 to 8V) amplitude: as complementary circuit 21 basic circuit, that formed by nmos pass transistor n11 and PMOS transistor p11.Then, when level shift part 20 is driven for level shift, clock pulse CK is applied to the grid of nmos pass transistor n11, simultaneously by by the coupling of capacity cell Cap relatively shift clock pulse CK be applied to the grid of PMOS transistor p11 to the resulting clock pulse of supply voltage VDD side.Therefore, in the moment that nmos pass transistor n11 and PMOS transistor p11 will turn-off, will guarantee that they are placed in off state.Therefore, electric leakage does not flow to complementary circuit 21.
Owing to do not have leakage current to flow to level shift part 20 by this way, so the power consumption of shift-register circuit 10 reduces and can realize.In addition, owing to use as basic circuit,, and be driven in transistorized saturation region so complementary circuit 21 does not suffer the influence of leakage current by the formed complementary circuit 21 of the transistor of conductivity type opposite always.Therefore, the diffusion of the strong antagonism of level shift part 20 transistor characteristics (threshold level Vth, drain-source current Ids, or the like), this characteristic is diffused in the level shift circuit of available technology adopting current mirror circuit as basic circuit and occurs.In other words, the circuit performance of level shift part 20 is not subjected to too big influence of transistor characteristic diffusion.In addition, do not appear between supply voltage VDD and the clock pulse CK owing to leak, the load on the clock pulse CK reduces.
In addition, when control impuls NSW and PSW are in disarmed state, the 4th switching circuit 25 shows as off state, and wherein it interrupts the electrical connection between clock end 28 and the node C (end of capacity cell Cap), and the influence of clock pulse CK may not appear on the node A like this.In addition, the 5th switching circuit 26 places conducting state being electrically connected voltage end 31 and node C, thus the voltage VC on the stationary nodes C to fixed voltage Vref1 (=Vin).Therefore, the coupling that can prevent clock pulse CK exerts an influence to node A by capacity cell Cap.Therefore, can prevent to export pulse OUT and go up the palpus shape noise that appearance takes place owing to the fluctuation of the voltage VA on the node A.
In addition, because the first and the 4th switch 22 and 25 adopts cmos switch to form, when the first and the 4th switch 22 and 25 is formed by single nmos pass transistor respectively about the possible situation of the conducting resistance of nmos pass transistor (, the high side voltage Vin of clock pulse CK (CK1/CK2) may become the possibility that is higher than supply voltage VDD under conducting state), can eliminate by the action of PMOS transistor p21 and p24.
In addition, because second, third and the 5th switch 23,24 and 26 are formed by cmos switch respectively, therefore when second, third and the 5th switch 23,24 and 26 are formed by single nmos pass transistor respectively, leak coupling or the coupling of grid source about canopy and the possible situation of generation (, because the noise that enters by coupling causes the possibility of fault), can eliminate by the action of PMOS transistor p22, p23 and p25.
Should be noted that, in the present embodiment, although above-mentioned possible situation can be eliminated to 26 by adopting cmos switch to form first to the 5th switching circuit 22, but needn't make requirement to the countermeasure of eliminating, and can select whether should take some countermeasures by the necessity that detects the countermeasure of the described possibility of antagonism situation according to circuit constant and drive condition (various voltage setting value).
Now, the circuit structure of description control pulse generation part 40.Figure 60 illustrates an embodiment of the structure of control impuls generation part 40.
With reference to Figure 60, comprise NOR circuit 41,42, two inverter circuit 43A of switching circuit and 43B, and reset circuit 44 according to the control impuls generation part 40 of present embodiment.In addition, control impuls generation part 40 has two inputs 45 and 46, two outputs 47 and 48, and reset terminal 49.
The input pulse IN1 that input 45 reception pulsewidths equal clock pulse CK (CK1/CK2) imports as it.Input pulse IN1 is corresponding to input pulse at the corresponding levels in the shift-register circuit 10.The input pulse IN2 of input 46 receptions and the clock pulse CK in 1/4 cycle of input pulse IN1 phase shift imports as it.Input pulse IN2 is corresponding to output pulse at the corresponding levels in the shift-register circuit 10.
NOR circuit 41 logic OR input pulse IN1 and input pulse IN2.Switching circuit 42 is by comprising that the nmos pass transistor n31 that is connected in parallel with each other and the cmos switch of PMOS transistor p31 form, and its input is connected to the output of NOR circuit 41.In switching circuit 42, be applied directly to the grid of nmos pass transistor n31 by the reset pulse " rest " of reset terminal 49 inputs.Simultaneously, reset pulse " rest " at it by the anti-phase after-applied grid of inverter circuit 43A to PMOS transistor p31.Reset pulse " rest " is low effective impulse signal.
The output pulse of inverter circuit 43B phase-veversal switch circuit 42 is with the control impuls NSW of generation positive and by output 47 output control pulse NSW.In addition, the output pulse of switching circuit 42 when its when the output by and as the control impuls PSW output of positive.Figure 61 illustrates the sequential relationship of input pulse IN1 and IN2 and control impuls NSW and PSW.
In having the control impuls generation part 40 of said structure, if reset pulse " rest " places low state (supply voltage VSS), the nmos pass transistor n31 of switching circuit 42 and PMOS transistor p31 both place off state so, and simultaneously to place conducting state be supply voltage VDD with the fixing input of inverter circuit 43B to the PMOS transistor p32 of reset circuit 44.Therefore, the control impuls NSW of control impuls generation part 40 output effective statuses and PSW are to place disarmed state with level shift part 20.When reset pulse " rest " has high level (supply voltage VDD), switching circuit 42 conductings and reset circuit 44 turn-off, and therefore, the control impuls NSW of control impuls generation part 40 output effective statuses and PSW are to place effective status with level shift part 20.
Figure 62 illustrates an embodiment of the structure of the third and fourth shift circuit 11-3 and 11-4.
With reference to Figure 62, according to the third and fourth shift circuit 11-3 and the 11-4 structure like this respectively of present embodiment, it comprises level shift part 50, control impuls generation part 40, and inverter circuit INV.Control impuls generation part 40 is grouped into by the control impuls generation part 40 identical control impuls generating units of structure and the first and second shift circuit 11-1 and 11-2.Yet in the third and fourth shift circuit 11-3 and 11-4 according to present embodiment, the output pulse OUT of level shift part 50 is anti-phase and draw as the output pulse of the corresponding levels then by inverter INV.
The difference of the third and fourth shift circuit 11-3 and 11-4 and shift circuit 11-1 and 11-2 is following point.Particularly, as mentioned above, when control impuls IN is in effective status, effective low level of shift circuit 11-1 and 11-2 extraction and level shift clock pulse CK1/CK2.On the contrary, effective high level of the third and fourth shift circuit 11-3 and 11-4 extraction and level shift clock pulse CK1/CK2.
Figure 63 illustrates an embodiment of the structure of level shift part 50 (LS2).In Figure 63, owing to level shift part 50 comprises and level shift part 20 components identical, so components identical uses the Reference numeral identical with Figure 58 to represent.
Particularly, with reference to Figure 63, comprise complementary circuit 21, first to the 5th switch 22 to 26, capacity cell Cap and buffer 27 according to the level shift part 50 of present embodiment.In addition, level shift part 50 has clock end 28, control end 29 and 30, voltage end 31 and output 32.In addition, level shift part 50 is configured to it and adopts the 3rd supply voltage VDD2 except that the first and second supply voltage VSS and VDD, so that carry out the process different with level shift part 20.
The 3rd supply voltage VDD2 is set at VDD-Vin when the amplitude of clock pulse CK (CK1/CK2) is set at VSS-Vin.In addition, second switch circuit 23 is connected between the grid of supply voltage VDD2 and PMOS transistor p11, and the 3rd switching circuit 24 is connected between the grid of supply voltage VSS and nmos pass transistor n11.In addition, fixed voltage Vref2 (for example, supply voltage VSS) is applied to voltage end 31.
The circuit operation of the level shift part 50 with said structure is described with reference to Figure 64 now.
At first, when control impuls NSW and PSW were in disarmed state, the first and the 4th switch 22 and 25 was in off state, and second, third and the 5th switch 23,24 and 26 are in conducting state.Therefore, no matter the logic state of clock pulse CK (CK1/CK2), voltage VA on the node A (grid of PMOS transistor p11) equals supply voltage VDD2 (VDD-Vin), and the voltage VB on another Node B (grid of nmos pass transistor n11) equals supply voltage VSS.Therefore, PMOS transistor p11 shows conducting state and nmos pass transistor n11 shows off state, and therefore, output pulse OUT equals supply voltage VDD.
When control impuls NSW and PSW are in effective status, that is, when level shift part 50 was in driving condition, the first and the 4th switch 22 and 25 was in conducting state, and the second, the three and the 5th switch 23,24 and 26 is in off state simultaneously.Therefore, node A is in the influence of floating dummy status and being subjected to clock pulse CK coupling by capacity cell Cap.Clock pulse CK is applied on the Node B by first switching circuit 22.
In the effective period of control impuls NSW and PSW, carry out to extract the process of clock pulse CK (CK1/CK2) high-voltage side pulse (promptly extracting effective high impulse) and with clock pulse CK another process from VSS-Vin amplitude level displacement (level conversion) to the VSS-VDD amplitude.
In addition, the clock amplitude on the Node B in the effective period of control impuls NSW and PSW is VSS/Vin, and the clock amplitude on the node A is VDD-Vin/VDD simultaneously, and is applied to node A in addition and has identical phase place with clock on the B.Therefore, in the moment that PMOS transistor p11 and nmos pass transistor n11 will turn-off, according to voltage VA on node A and the B and the relation of VB, their are guaranteed to place off state.Therefore, in the complementary circuit 21 that forms by PMOS transistor p11 and nmos pass transistor n11, can guarantee to prevent the leakage when MOS transistor p11 and n11 turn-off.
As mentioned above, level shift part 50 (it is with the clock pulse CK level shift of the VSS-Vin amplitude output pulse OUT to the VSS-VDD amplitude) adopts the complementary circuit of being made up of nmos pass transistor n11 and PMOS transistor p11 21 as basic circuit.Then, when level shift part 50 is driven for level shift, clock pulse CK is applied to the grid of nmos pass transistor n11, simultaneously by capacity cell Cap coupling relatively the clock pulse that obtains to supply voltage VDD side of shift clock pulse CK be applied to the grid of PMOS transistor p11.Therefore, in the moment that nmos pass transistor n11 and PMOS transistor p11 will turn-off, guarantee that they place off state.Therefore, there is not leakage current to flow to complementary circuit 21.
Owing to do not have leakage current to flow to level shift part 50 by this way, can reckon with that so the power consumption of shift-register circuit 10 reduces.In addition, because the complementary circuit 21 that is formed by the transistor of conductivity type opposite is as basic circuit, so there is not leakage current to flow through complementary circuit 21 and in transistorized saturation region, complementary circuit 21 is driven always.Therefore, level shift part 50 can be resisted the diffusion of transistor characteristic (threshold level Vth, drain-source current Ids, or the like) effectively, and this characteristic is diffused in the level shift circuit of available technology adopting current mirror circuit as basic circuit and occurs.In other words, the circuit performance of level shift part 50 is not subjected to too big influence of transistor characteristic diffusion.In addition, owing between supply voltage VDD and clock pulse CK, do not have leakage current, so the load on the clock pulse CK can reduce.Level shift part 50 shows other action and the advantage identical with level shift part 20.
[the 5th embodiment]
Figure 65 illustrates the structure according to the shift-register circuit of fifth embodiment of the invention.Shift-register circuit 60 according to present embodiment is constructed like this, promptly first to the 4th shift circuit 61-1 to the 61-4 cascade connect as shift register cell (shifting level/shift stages) and, a plurality of this first to the 4th shift circuit 61-1 repeat to be provided with and cascade connects to 61-4 group, and are similar with shift-register circuit 10 according to the 4th embodiment.
As following detailed, the first shift circuit 61-1 has identical circuit structure with the second shift circuit 61-2, and the 3rd displacement electric power 61-3 has another identical circuit structure with the 4th shift circuit 61-4.The first clock pulse CK1 is applied to the first and the 3rd shift circuit 61-1 and 61-3, simultaneously second clock pulse CK2 is applied to the second and the 4th shift circuit 61-2 and 61-4, second clock pulse CK2 is identical with the first clock pulse CK1 frequency, and has the phase shift of 1/4 cycle with the first clock pulse CK1.
Low effective inceptive impulse ST is applied to the first shift circuit 61-1 as control impuls IN.When control impuls IN is in effective status (low-voltage), shift circuit 61-1 extracts the low voltage side pulse (effectively low) of the first clock pulse CK1, this low voltage side pulse is displaced to second amplitude from first amplitude level, and the low voltage side pulse of output level displacement.The low effectively output pulse OUT of the first shift circuit 61-1 is applied to partial shift circuit 61-2 as control impuls IN.
When control impuls IN is in effective status, shift circuit 61-2 on the second level extracts the low voltage side pulse of second clock pulse CK2, this low voltage side pulse is displaced to second amplitude from first amplitude level, and exports the low voltage side pulse of this level shift.The low effectively output pulse OUT of shift circuit 61-2 is applied to shift circuit 61-3 on the third level as control impuls IN.
When control impuls IN is in effective status, shift circuit 61-3 on the third level extracts the high-voltage side pulse (effectively high) of the first clock pulse CK1, this high-voltage side pulse is displaced to second amplitude from first amplitude level, and exports the high-voltage side pulse of this level shift.The low effectively output pulse OUT of shift circuit 61-3 is applied to shift circuit 61-4 on the fourth stage as control impuls IN.
When control impuls IN is in effective status, shift circuit 61-4 on the fourth stage extracts the high-voltage side pulse of second clock pulse CK2, this high-voltage side pulse is displaced to second amplitude from first amplitude level, and exports the high-voltage side pulse of this level shift.The low effectively output pulse OUT of the 4th shift circuit 61-4 is applied to shift circuit 61-5 on the level V as control impuls IN.
After this, repeat the circuit operation of first to the 4th shift circuit 61-1 to the level Four group of 61-4.
At shift circuit (shifting level) 61-1,61-2 ... in, input pulse IN (control impuls) at the corresponding levels and output pulse OUT at the corresponding levels import OR-NOT circuit 62-1,62-2 as three ... two inputs.Pulsewidth is applied to OR-NOT circuit 62-1,62-2 less than the effective enabling pulse EN of the height of clock pulse CK1 and CK2 ... a remaining input.Then, OR-NOT circuit 62-1,62-2 ... high effectively output pulse as transfer pulse o1, the o2 of each transfer ... draw.
Figure 66 illustrates clock pulse CK1 and CK2, enabling pulse EN, inceptive impulse ST, first and second grades output pulse SR_out, and shift pulse o1, o2, o3 ... sequential relationship.Obviously find out from the sequential chart of Figure 66, shift circuit 61-1,61-2 ... extract the clock pulse CK1 of first amplitude (VSS-Vin) and CK2 and level shift (level conversion) clock pulse CK1 and CK2 to the transfer pulse o1 of second amplitude (VSS-VDD), o2, o3,
As mentioned above, same in shift-register circuit 60 according to the 5th embodiment, shift circuit 61-1,61-2 each other in to and cascade connect, and the 3rd shift circuit 61-3 and the 4th shift circuit 61-4 each other in to and cascade be connected.In addition, two groups of shift circuits connect cascade, and have the clock pulse CK1 of 1/4 cycle phase shift each other and clock pulse CK2 alternately is applied on the repeated arrangement of this shift register cell (shifting level).Therefore, can realize the driving of shift-register circuit 60, the frequency of its clock pulse CK1 and CK2 is reduced to shift register adopted in the prior art clock pulse CK and half of xCK.In the prior art, the shift register cell with same circuits structure can repeat to be provided with, and therefore, the load that produces the clock generating circuit of clock pulse CK1 and CK2 can be reduced to half, and driving frequency can be seen half.The result is to reckon with that shift-register circuit 60 power consumptions own reduce.
Now, the ad hoc structure of first to the 4th shift circuit (shift register cell) 61-2 to 61-4 described.
Figure 67 illustrates an embodiment of the structure of shift circuit 61-1 and 61-2.With reference to Figure 67, comprise level shift part 20, control impuls generation part 70, and inverter circuit INV according to the shift circuit 61-1 and the 61-2 of present embodiment.Level shift part 20 is identical with the level shift part of describing in the above in conjunction with the shift-register circuit 10 of the 4th embodiment 20, and has same specific circuit architecture (Figure 58).
At this, the specific circuit architecture of description control pulse generation part 70.Figure 68 illustrates an embodiment of the structure of control impuls generation part 70.
With reference to Figure 68, comprise NAND circuit 71,72, two inverter circuit 73A of switching circuit and 73B, and reset circuit 74 according to the control impuls generation part 70 of present embodiment.In addition, control impuls generation part 70 has two inputs 75 and 76, two outputs 77 and 78, and reset terminal 79.
The input pulse IN1 that input 75 reception pulsewidths equal clock pulse CK (CK1/CK2) imports as it.Input pulse IN1 is corresponding to the input pulse of shift-register circuit 60 corresponding levels.Input 76 receives another input pulse IN2 and imports as it.Input pulse IN2 and input pulse IN1 have the phase shift of 1/4 cycle clock pulse CK.Input pulse IN2 is corresponding to the output pulse of shift-register circuit 60 corresponding levels.
The control impuls PSW of the output pulse of inverter circuit 73B phase-veversal switch circuit 72 to produce anti-phase control impuls PSW and to be produced by output 78 outputs.In addition, the output pulse of switching circuit 72 when its when the output 77 by and as the control impuls NSW output of positive.Figure 69 illustrates the sequential relationship between input pulse IN1 and IN2 and control impuls NSW and the PSW.
In having the control impuls generation part 70 of said structure, if " rest places high level (supply voltage VDD) to reset pulse; the nmos pass transistor n41 of switching circuit 72 and PMOS transistor p41 both place off state so, and simultaneously to place conducting state be supply voltage VSS with the fixing input of inverter circuit 73B to the nmos pass transistor n42 of reset circuit 74.Therefore, the control impuls NSW of control impuls generation part 70 output disarmed states and PSW are to place disarmed state with level shift part 20.When reset pulse " rest " had low level (supply voltage VSS), switching circuit 72 conductings and reset circuit 74 turn-offed.Therefore, the control impuls NSW of effective status and PSW export so that level shift part 20 is placed effective status from control impuls generation part 70.
As mentioned above, although the first and second shift circuit 61-1 and 61-2 comprise according to the control impuls generation part 70 of present embodiment and the combination of level shift part 20, but the third and fourth shift circuit 61-3 and 61-4 comprise the combination according to the control impuls generation part 70 and the level shift part 50 (Figure 63) of present embodiment, shown in Figure 70.
Now, describe with according to the shift-register circuit 10 of the 4th and the 5th embodiment and the specific circuit architecture of the 60 various circuit blocks that use.
At first, describe use with reference to Figure 71 and import AND circuit 12-1 according to three in the shift-register circuit 10 of the 4th embodiment, 12-2 ...Three input AND circuit comprise the nmos pass transistor n51 that is connected in series between node N11 and the supply voltage VSS, n52 and n53, and be connected in PMOS transistor p51 between supply voltage VDD and the node N11 in parallel, p52, and p53.Three input AND circuit are constructed like this, make as three input IN1, and the voltage when IN2 and IN3 are applied to the grid of transistor n51 to n53 and p51 to p53 on the node N11 is anti-phase and as logical AND output and export by inverter circuit INV.
For above-mentioned inverter circuit INV and use according to the inverter circuit on all places of the shift-register circuit 10 of the 4th and the 5th embodiment and 60, use the CMOS inverter, it comprises the nmos pass transistor and PMOS transistor and grid and public each other connection of drain electrode that is connected in series between supply voltage VDD and the supply voltage VSS, shown in Figure 72.
Now, be described in employed two input OR-NOT circuit 41 in the control impuls generation part 40 according to the shift-register circuit 10 of the 4th embodiment with reference to Figure 73.Nmos pass transistor n55 and n56 that two input OR-NOT circuit are included in the PMOS transistor p55 that is connected in series between supply voltage VDD and the node N12 and p56 and are connected in parallel between node N12 and supply voltage VSS.Two input OR-NOT circuit are constructed like this, make when two import IN1 and IN2 and are applied to the grid of PMOS transistor p55 and p56 and nmos pass transistor n55 and n56 respectively the voltage on the node N12 as logic OR non-output draw.
Now, be described in according to employed NOR circuit 62-1 in the shift-register circuit 60 of the 5th embodiment with reference to Figure 74,62-2 ...Shown three input NOR circuit are included in the nmos pass transistor n61 that is connected in parallel between node N13 and the supply voltage VSS, n62, and n63, and be connected in series in PMOS transistor p61 between supply voltage VDD and the node N13, p62, and p63.Three input NOR circuit are constructed like this, make as three input IN1, IN2 and IN3 be applied to transistor n61 to n63 and p61 during to p63 the voltage on the node N13 as logic OR non-output draw.
At last, with reference to employed two input NAND circuit 71 in the control impuls generation part 70 of Figure 75 description according to the shift-register circuit 60 of the 5th embodiment.Nmos pass transistor n65 and n66 that shown two input NAND circuit are included in the PMOS transistor p65 that is connected in parallel between supply voltage VDD and the node N14 and p66 and are connected in series between node N14 and supply voltage VSS.Two input NAND circuit are constructed like this, make that the voltage on the node N14 is exported as NAND when two input IN1 and IN2 are applied to the grid of PMOS transistor p65 and p66 and nmos pass transistor n65 and n66 respectively to draw.Logical circuit shown in Figure 71 to 75 only is embodiment and needs only its class of operation like being replaced by arbitrary other logical circuit.
Shift-register circuit 10 and 60 according to the 4th and the 5th embodiment can be used as the general bit shifting register circuit with level shift function.Shift-register circuit 10 and 60 also can be used as the shift-register circuit of the scanner of vertical driver in the display device that is formed on the drive circuit integrated-type or horizontal driver.In display device, the peripheral drive circuit that drives pixel array portion forms onboard, and wherein each pixel that comprises photoelectric cell is provided with pixel array portion onboard with the row and column two-dimensional arrangements.
[Application Example 3]
Figure 54 illustrates the embodiment of the display device structure of Application Example according to the present invention.Display device shown in Figure 54 forms the active array type liquid crystal display, and liquid crystal cells is as the photoelectric cell of pixel.
With reference to Figure 54, according to should comprising pixel array portion 81 with the active array type liquid crystal display 80 of embodiment, vertical driver 82, horizontal driver 83, or the like.Comprise peripheral drive circuit whole formation on liquid crystal board 84 of vertical driver 82 and horizontal driver 83, on liquid crystal board 84, form pixel array portion 81.Liquid crystal board 84 comprises two insulating bases (for example glass plate) that are provided with relativeness, reserve the fixed interval (FI) therebetween, and liquid crystal material is sealed in the gap.
Pixel array portion 81 has the capable and n row two dimension pixel 90 disposed thereon with m.In addition, on the matrix of pixel 90,, and be that every row arrange that holding wire 86-1 is to 86-n for every row is arranged scan line 85-1 to 85-m.Each pixel 90 comprises TFT (thin-film transistor) 91, and pixel electrode is connected to the liquid crystal cells 92 in the drain electrode of TFT 91, and one electrode is connected to the maintenance capacitor 93 in TFT 91 drain electrodes.
In above-mentioned dot structure, TFT 61 grids of each pixel 90 are connected to scan line 85 (85-1 is to 85-m) and source electrode is connected to holding wire 86 (86-1 is to 86-n).Simultaneously, another electrode of the comparative electrode of liquid crystal cells 92 and maintenance capacitor 93 is connected on the common wire 87 that has applied common electric voltage VCOM.
Vertical driver 82 is formed by shift register etc., and selects the pixel 90 of pixel array portion 81 with behavior unit.Horizontal driver 83 is by shift register, formation such as sampling switch, and be unit sequence ground (according to dot sequency) with the pixel or with behavior unit's (according to line order) vision signal from the outer part input of panel be written to the pixel 90 by vertical driver 82 selected row simultaneously.
In having the active array type liquid crystal display 80 of said structure, according to above-mentioned first or the shift-register circuit 10 of second embodiment or 60 as at least one the shift-register circuit that forms in vertical driver 82 and the horizontal driver 83.
Should be noted that in above-mentioned Application Example, wherein liquid crystal cells is as the liquid crystal display of the photoelectric cell of pixel although the present invention is applied to, application of the present invention is not limited to liquid crystal display, and the present invention also may be used on various display devices.The embodiment of various display devices can be the EL display device, and it adopts the photoelectric cell of EL (electroluminescence) element as pixel, perhaps comprises other device of the scanner that adopts shift-register circuit formation.In the EL display device, adopt formed vertical driver of shift-register circuit or horizontal driver to be formed on the plate that forms pixel array portion.
Although the preferred embodiments of the present invention have adopted particular term to describe, this description is illustrative purpose only, and should be appreciated that, under the situation of the spirit or scope that do not break away from claims, can form various changes and distortion.
Claims (62)
1. level shifting circuit comprises:
Be connected in series between first supply voltage and the second source voltage and reciprocal first and second transistors of conduction type;
Clock end, clock signal are input to described clock end;
Be connected between the grid of described clock end and described the first transistor and first switching device that when circuit operation control signal is in effective status, has conducting state;
Be connected between the grid of described second source voltage and described transistor seconds and when circuit operation control signal is in effective status, have the second switch device of off state; And
Be connected the capacity cell between the grid of described clock end and described transistor seconds.
2. according to the level shifting circuit of claim 1, also comprise the one-way circuit between the grid that is connected described second source voltage and described transistor seconds.
3. according to the level shifting circuit of claim 1, wherein when the clock signal placed high level, circuit operation control signal became effective status from disarmed state.
4. according to the level shifting circuit of claim 1, also comprise the resetting means that is used for periodically the grid voltage of described transistor seconds being set at described second source voltage, wherein said resetting means is connected between the grid of described second source voltage and described transistor seconds.
5. according to the level shifting circuit of claim 4, wherein when the clock signal had high level, described resetting means had conducting state.
6. supply voltage generation circuit comprises:
Be used for the clock pulse level conversion of first amplitude level converter to the clock pulse of second amplitude;
The clock pulse that is used for second amplitude that will be obtained by described level converter level conversion converts the buffer unit of the clock pulse that phase place is opposite each other to; And
Be used for moving to produce the circuit part of predetermined power source voltage in response to the opposite clock pulse of exporting from described buffer unit of phase place;
Described level converter comprises:
Be connected in series between first supply voltage and the second source voltage and reciprocal first and second transistors of conduction type;
Clock end, clock signal are input to described clock end;
Be connected between the grid of described clock end and described the first transistor and first switching device that when circuit operation control signal is in effective status, has conducting state;
Be connected between the grid of described second source voltage and described transistor seconds and when circuit operation control signal is in effective status, have the second switch device of off state; And
Be connected the capacity cell between the grid of described clock end and described transistor seconds.
7. according to the supply voltage generation circuit of claim 6, wherein said level converter also comprises the one-way circuit between the grid that is connected described second source voltage and described transistor seconds.
8. according to the supply voltage generation circuit of claim 6, wherein when clock pulse placed high level, circuit operation control signal became effective status from disarmed state.
9. according to the supply voltage generation circuit of claim 6, wherein said level converter also comprises the resetting means that is used for periodically the grid voltage of described transistor seconds being set at described second source voltage, and wherein said resetting means is connected between the grid of described second source voltage and described transistor seconds.
10. according to the supply voltage generation circuit of claim 9, wherein when the clock signal had high level, described resetting means had conducting state.
11. supply voltage generation circuit according to claim 10, wherein said buffer unit comprises the odd number inverter circuit level that cascade connects, and described supply voltage generation circuit also comprises reseting signal generator, is used for adopting the output of one of described inverter circuit on the described buffer unit one-level in office to produce being used to the reset signal of the driving of controlling described resetting means.
12. a display device comprises:
Supply voltage generation circuit, described supply voltage generation circuit comprises:
Be used for the clock pulse level conversion of first amplitude level converter to the clock pulse of second amplitude;
The clock pulse that is used for second amplitude that will be obtained by described level converter level conversion converts the buffer unit of the reciprocal clock pulse of phase place to; And
Be used for moving to produce the circuit part of predetermined power source voltage in response to the opposite clock pulse of exporting from described buffer unit of phase place;
Pixel array portion, a plurality of pixels that wherein include photoelectric cell are according to two-dimensional arrangements; And
Be formed with the circuit board of described supply voltage generation circuit and described pixel array portion on it;
Described level converter comprises:
Be connected in series between first supply voltage and the second source voltage and reciprocal first and second transistors of conduction type;
Clock end, clock signal are input to described clock end;
Be connected between the grid of described clock end and described the first transistor and first switching device that when circuit operation control signal is in effective status, has conducting state;
Be connected between the grid of described second source voltage and described transistor seconds and when circuit operation control signal is in effective status, have the second switch device of off state; And
Be connected the capacity cell between the grid of described clock end and described transistor seconds.
13. according to the display device of claim 12, wherein said level converter also comprises the one-way circuit between the grid that is connected described second source voltage and described transistor seconds.
14. according to the display device of claim 12, wherein when the clock signal placed high level, circuit operation control signal became effective status from disarmed state.
15. display device according to claim 12, wherein said level converter also comprises the resetting means that is used for periodically the grid voltage of described transistor seconds being set at described second source voltage, and wherein said resetting means is connected between the grid of described second source voltage and described transistor seconds.
16. according to the display device of claim 15, wherein when the clock signal had high level, described resetting means had conducting state.
17. display device according to claim 16, wherein said buffer unit comprises the odd number inverter circuit level that cascade connects, and described display device also comprises reseting signal generator, is used for adopting the output of one of described inverter circuit on the described buffer unit one-level in office to produce being used to the reset signal of the driving of controlling described resetting means.
18. a shift circuit comprises:
Level shifting apparatus is used for when control impuls is in effective status clock pulse is displaced to second amplitude and the output clock pulse through level shift from first amplitude level; And
Be used to produce the control impuls generating means of control impuls;
Described level shifting apparatus comprises:
Be connected in series between first supply voltage and the second source voltage and reciprocal first and second transistors of conduction type;
Clock end, clock pulse are input to described clock end;
Be connected between the grid of described clock end and described the first transistor and first switching device that when control impuls is in effective status, has conducting state;
Be connected between the grid of described second source voltage and described transistor seconds and when control impuls is in effective status, have the second switch device of off state; And
Be connected the capacity cell between the grid of described clock end and described transistor seconds.
19. according to the shift circuit of claim 18, wherein said level shifting apparatus also comprises the 3rd switching device that has off state between the grid that is connected described second source voltage and described the first transistor and when control impuls is in effective status.
20. according to the shift circuit of claim 18, wherein said level shifting apparatus also comprises and is connected the 4th switching device that is used for interrupting the electrical connection between described clock end and the described capacity cell between described clock end and the described capacity cell when control impuls is in disarmed state.
21. according to the shift circuit of claim 20, wherein said level shifting apparatus also comprises the fixture that is used for when control impuls is in disarmed state the voltage on the tie point between described the 4th switching device and the described capacity cell being remained on fixed voltage.
22. according to the shift circuit of claim 18, wherein control impuls only has effective status in a period of time of the one-period of clock pulse.
23. a shift-register circuit comprises:
A plurality of shift circuit levels that cascade connects, and each shift circuit level comprises:
Level shifting apparatus is used for when control impuls is in effective status clock pulse is displaced to second amplitude and the output clock pulse through level shift from first amplitude level; And
Be used to produce the control impuls generating means of control impuls;
Described level shifting apparatus comprises:
Be connected in series between first supply voltage and the second source voltage and reciprocal first and second transistors of conduction type;
Clock end, clock pulse are input to described clock end;
Be connected between the grid of described clock end and described the first transistor and first switching device that when control impuls is in effective status, has conducting state;
Be connected between the grid of described second source voltage and described transistor seconds and when control impuls is in effective status, have the second switch device of off state; And
Be connected the capacity cell between the grid of described clock end and described transistor seconds.
24. according to the shift-register circuit of claim 23, wherein said level shifting apparatus also comprises the 3rd switching device that has off state between the grid that is connected described second source voltage and described the first transistor and when control impuls is in effective status.
25. according to the shift-register circuit of claim 23, wherein said level shifting apparatus also comprises and is connected the 4th switching device that is used for interrupting the electrical connection between described clock end and the described capacity cell between described clock end and the described capacity cell when control impuls is in disarmed state.
26. according to the shift-register circuit of claim 25, wherein said level shifting apparatus also comprises the fixture that is used for when control impuls is in disarmed state the voltage on the tie point between described the 4th switching device and the described capacity cell being remained on fixed voltage.
27. according to the shift-register circuit of claim 23, wherein said control impuls generating means is in response to the output of the input of the shift circuit under the described control impuls generating means and the shift circuit under the described control impuls generating means and produce control impuls.
28. according to the shift-register circuit of claim 23, wherein said control impuls generating means is in response to the output of the input of the shift circuit under the described control impuls generating means and the shift circuit on the next stage under the described control impuls generating means and produce control impuls.
29. shift-register circuit according to claim 23, wherein from multistage first each control impuls generating means to the shift circuit of penultimate stage in response to the output of the input of the shift circuit under the control impuls generating means and the shift circuit on the next stage under the control impuls generating means and produce control impuls, and
Described control impuls generating means in the shift circuit on the afterbody is in response to the output of the input of the shift circuit under the described control impuls generating means and the shift circuit under the described control impuls generating means and produce control impuls.
30. according to the shift-register circuit of claim 28, wherein supply voltage is as the output of the shift circuit on the next stage and be input to the described control impuls generating means of the shift circuit on the afterbody in multistage, and
Described shift-register circuit also comprises feedway, be used for when the output of the shift circuit on the penultimate stage has effective status, providing supply voltage to the shift circuit on the penultimate stage, and the shift circuit on the penultimate stage exported to of shift circuit on the afterbody is provided when the output device of the shift circuit on the penultimate stage has disarmed state.
31. shift-register circuit according to claim 26, wherein each shift circuit is opposite each other and have the clock pulse of the fixed voltage that equals high-side voltage and carry out shifting function in response to phase place, and described shift-register circuit also comprises the fixed voltage generation device, is used for producing fixed voltage in response to the reciprocal clock pulse of phase place.
32. a display device comprises:
Pixel array portion, a plurality of pixels that wherein include photoelectric cell are provided with the row and column two dimension;
Be used for selecting the vertical drive of described pixel array section with behavior unit; And
Be used for vision signal is write horizontal drive apparatus by the pixel of the selected row of described vertical drive;
In described vertical drive and the described horizontal drive apparatus at least one comprises shift-register circuit;
Described shift-register circuit comprises a plurality of shift circuit levels that cascade connects, and each shift circuit level comprises:
Level shifting apparatus is used for when control impuls is in effective status clock pulse is displaced to second amplitude and the output clock pulse through level shift from first amplitude level; And
Be used to produce the control impuls generating means of control impuls;
Described level shifting apparatus comprises:
Be connected in series between first supply voltage and the second source voltage and reciprocal first and second transistors of conduction type;
Clock end, clock pulse are input to described clock end;
Be connected between the grid of described clock end and described the first transistor and first switching device that when control impuls is in effective status, has conducting state;
Be connected between the grid of described second source voltage and described transistor seconds and when control impuls is in effective status, have the second switch device of off state; And
Be connected the capacity cell between the grid of described clock end and described transistor seconds.
33. according to the display device of claim 32, wherein said level shifting apparatus also comprises the 3rd switching device that has off state between the grid that is connected described second source voltage and described the first transistor and when control impuls is in effective status.
34. according to the display device of claim 32, wherein said level shifting apparatus also comprises and is connected the 4th switching device that is used for interrupting the electrical connection between described clock end and the described capacity cell between described clock end and the described capacity cell when control impuls is in disarmed state.
35. according to the display device of claim 34, wherein said level shifting apparatus also comprises the fixture that is used for when control impuls is in disarmed state the voltage on the tie point between described the 4th switching device and the described capacity cell being remained on fixed voltage.
36. according to the display device of claim 32, wherein said control impuls generating means is in response to the output of the input of the shift circuit under the described control impuls generating means and the shift circuit under the described control impuls generating means and produce control impuls.
37. according to the display device of claim 32, wherein said control impuls generating means is in response to the output of the input of the shift circuit under the described control impuls generating means and the shift circuit on the next stage under the described control impuls generating means and produce control impuls.
38. display device according to claim 32, from multistage first each control impuls generating means to the shift circuit of penultimate stage in response to the output of the input of the shift circuit under the control impuls generating means and the shift circuit on the next stage under the control impuls generating means and produce control impuls, and
Described control impuls generating means in the shift circuit on the afterbody is in response to the output of the input of the shift circuit under the described control impuls generating means and the shift circuit under the described control impuls generating means and produce control impuls.
39. according to the display device of claim 37, wherein supply voltage is as the output of the shift circuit on the next stage and be input to the described control impuls generating means of the shift circuit on the afterbody in multistage, and
Described display device also comprises feedway, be used for when the output of the shift circuit on the penultimate stage has effective status, providing supply voltage to the shift circuit on the penultimate stage, and the shift circuit on the penultimate stage exported to of shift circuit on the afterbody is provided when the output device of the shift circuit on the penultimate stage has disarmed state.
40. according to the display device of claim 35, wherein each shift circuit is opposite each other and have the clock pulse of the fixed voltage that equals high-side voltage and carry out shifting function in response to phase place, and
Described display device also comprises the fixed voltage generating means, is used for producing fixed voltage in response to the reciprocal clock pulse of phase place.
41. a shift-register circuit comprises:
Alternately a plurality of first shift circuits of cascade connection are to right with a plurality of second shift circuits;
Each of the described first shift circuit centering to first shift circuit that comprises cascade and connect with second shift circuit and each the 3rd shift circuit and the 4th shift circuit of the described second shift circuit centering to comprising that cascade is connected;
When first control impuls has effective status, the low level lateral vein that described first shift circuit can be operated to extract first clock pulse dashes, the low level lateral vein dashed be displaced to second amplitude, and output is dashed through the low level lateral vein of level shift from first amplitude level;
When first control impuls has effective status, the low level lateral vein that described second shift circuit can be operated to extract the second clock pulse dashes, the low level lateral vein dashed be displaced to second amplitude from first amplitude level, and output is dashed through the low level lateral vein of level shift, wherein the frequency of second clock pulse equals the frequency of first clock pulse, still has the phase shift in 1/4 cycle with first clock pulse;
When second control impuls has effective status, described the 3rd shift circuit can be operated to extract the high-side pulse of first clock pulse, the high-side pulse is displaced to second amplitude from first amplitude level, and output is through the high-side pulse of level shift; And
When second control impuls has effective status, described the 4th shift circuit can be operated to extract the high-side pulse of second clock pulse, the high-side pulse is displaced to second amplitude from first amplitude level, and output is through the high-side pulse of level shift.
42. according to the shift-register circuit of claim 41, each in wherein said first and second shift circuits comprises:
Be connected in series between first supply voltage and the second source voltage and reciprocal first and second transistors of conduction type;
First clock end, first and second clock pulse are input to first clock end;
Be connected between the grid of described first clock end and described the first transistor and first switching device that when first control impuls is in effective status, has conducting state;
Be connected between the grid of described second source voltage and described transistor seconds and when first control impuls is in effective status, have the second switch device of off state; And
Be connected first capacity cell between the grid of described first clock end and described transistor seconds.
43. according to the shift-register circuit of claim 42, each in wherein said first and second shift circuits also comprises the 3rd switching device that has off state between the grid that is connected described second source voltage and described the first transistor and when first control impuls is in effective status.
44. according to the shift-register circuit of claim 42, each in wherein said first and second shift circuits also comprises and is connected the 4th switching device that is used for interrupting the electrical connection between described first clock end and described first capacity cell between described first clock end and described first capacity cell when first control impuls is in disarmed state.
45. according to the shift-register circuit of claim 44, each in wherein said first and second shift circuits also comprises the fixture that is used for when first control impuls is in disarmed state the voltage on the tie point between described the 4th switching device and described first capacity cell being remained on fixed voltage.
46. according to the shift-register circuit of claim 41, each in wherein said third and fourth shift circuit comprises:
Be connected in series between described first supply voltage and the described second source voltage and reciprocal third and fourth transistor of conduction type;
Second clock end, first and second clock pulse are input to described second clock end;
Be connected between described second clock end and the described the 3rd transistorized grid and the 5th switching device that when second control impuls is in effective status, has conducting state;
Be connected between the 3rd supply voltage and the described the 4th transistorized grid and have the 6th switching device of off state when second control impuls is in effective status, wherein the 3rd supply voltage hangs down the amplitude voltage of first and second clock pulse than described second source voltage; And
Be connected second capacity cell between described second clock end and the described the 4th transistorized grid.
47. according to the shift-register circuit of claim 46, each in wherein said third and fourth shift circuit also comprises between the grid that is connected described first supply voltage and described the first transistor and have the minion pass device of off state when second control impuls is in effective status.
48. according to the shift-register circuit of claim 46, each in wherein said third and fourth shift circuit also comprises being connected and is used for interrupting described second clock end between described second clock end and described second capacity cell closes device with the octavo that is electrically connected between described second capacity cell when second control impuls is in disarmed state.
49. according to the shift-register circuit of claim 48, each in wherein said third and fourth shift circuit also comprises the fixture that is used for when second control impuls is in disarmed state the voltage on the tie point between described octavo pass device and described second capacity cell being remained on fixed voltage.
50. according to the shift-register circuit of claim 41, each in wherein said first and second shift circuits produces first control impuls in response to the input and output of level under the shift circuit.
51. according to the shift-register circuit of claim 41, each in wherein said third and fourth shift circuit produces second control impuls in response to the input and output of level under the shift circuit.
52. a display device comprises:
Pixel array portion, a plurality of pixels that wherein include photoelectric cell are provided with the row and column two dimension;
Be used for selecting the vertical drive of described pixel array section with behavior unit; And
Be used for vision signal is write horizontal drive apparatus by the pixel of the selected row of described vertical drive;
In described vertical drive and the described horizontal drive apparatus at least one comprises shift-register circuit;
Described shift-register circuit comprises that a plurality of first shift circuits of alternately cascade connection are to right with a plurality of second shift circuits;
First shift circuit and second shift circuit of each of the described first shift circuit centering to comprising that cascade connects, and each the 3rd shift circuit and the 4th shift circuit of the described second shift circuit centering to comprising that cascade connects;
When first control impuls has effective status, the low level lateral vein that described first shift circuit can be operated to extract first clock pulse dashes, the low level lateral vein dashed be displaced to second amplitude, and output is dashed through the low level lateral vein of level shift from first amplitude level;
When first control impuls has effective status, the low level lateral vein that described second shift circuit can be operated to extract the second clock pulse dashes, the low level lateral vein is displaced to second amplitude from first amplitude level, and output is dashed through the low level lateral vein of level shift, wherein the frequency of second clock pulse equals the frequency of first clock pulse, still has the phase shift in 1/4 cycle with first clock pulse;
When second control impuls has effective status, described the 3rd shift circuit can be operated to extract the high-side pulse of first clock pulse, the high-side pulse is displaced to second amplitude from first amplitude level, and output is through the high-side pulse of level shift; And
When second control impuls has effective status, described the 4th shift circuit can be operated to extract the high-side pulse of second clock pulse, the high-side pulse is displaced to second amplitude from first amplitude level, and output is through the high-side pulse of level shift.
53. according to the display device of claim 52, each in described first and second shift circuits comprises:
Be connected in series between first supply voltage and the second source voltage and reciprocal first and second transistors of conduction type;
First clock end, first and second clock pulse are input to first clock end;
Be connected between the grid of described first clock end and described the first transistor and first switching device that when first control impuls is in effective status, has conducting state;
Be connected between the grid of described second source voltage and described transistor seconds and when first control impuls is in effective status, have the second switch device of off state; And
Be connected first capacity cell between the grid of described first clock end and described transistor seconds.
54. according to the display device of claim 53, each in wherein said first and second shift circuits also comprises the 3rd switching device that has off state between the grid that is connected described second source voltage and described the first transistor and when first control impuls is in effective status.
55. according to the display device of claim 53, each in wherein said first and second shift circuits also comprises and is connected the 4th switching device that is used for interrupting the electrical connection between described first clock end and described first capacity cell between described first clock end and described first capacity cell when first control impuls is in disarmed state.
56. according to the display device of claim 55, each in wherein said first and second shift circuits also comprises: the fixture that is used for when first control impuls is in disarmed state, the voltage on the tie point between described the 4th switching device and described first capacity cell being remained on fixed voltage.
57. according to the display device of claim 52, each in wherein said third and fourth shift circuit comprises:
Be connected in series between described first supply voltage and the described second source voltage and reciprocal third and fourth transistor of conduction type;
The second clock end, first and second clock pulse are input to the second clock end;
Be connected between described second clock end and the described the 3rd transistorized grid and the 5th switching device that when second control impuls is in effective status, has conducting state;
Be connected between the 3rd supply voltage and the described the 4th transistorized grid and have the 6th switching device of off state when second control impuls is in effective status, wherein the 3rd supply voltage hangs down the amplitude voltage of first and second clock pulse than described second source voltage; And
Be connected second capacity cell between described second clock end and the described the 4th transistorized grid.
58. according to the display device of claim 57, each in wherein said third and fourth shift circuit also comprises: be connected between the grid of described first supply voltage and described the first transistor and the minion that has off state when second control impuls is in effective status is closed device.
59. according to the display device of claim 57, each in wherein said third and fourth shift circuit also comprises: be connected and be used for when second control impuls is in disarmed state, interrupting described second clock end between described second clock end and described second capacity cell and close device with the octavo that is electrically connected between described second capacity cell.
60. according to the display device of claim 59, each in wherein said third and fourth shift circuit also comprises: the fixture that is used for when second control impuls is in disarmed state, the voltage on the tie point between described octavo pass device and described second capacity cell being remained on fixed voltage.
61. according to the display device of claim 52, each in wherein said first and second shift circuits produces first control impuls in response to the input and output of level under the shift circuit.
62. according to the display device of claim 52, each in wherein said third and fourth shift circuit produces second control impuls in response to the input and output of level under the shift circuit.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP228948/04 | 2004-08-05 | ||
| JP2004228947A JP4453476B2 (en) | 2004-08-05 | 2004-08-05 | Shift circuit, shift register circuit, and display device |
| JP228947/04 | 2004-08-05 | ||
| JP2004228948A JP4305317B2 (en) | 2004-08-05 | 2004-08-05 | Shift register circuit and display device |
| JP2004228946A JP4453475B2 (en) | 2004-08-05 | 2004-08-05 | Level conversion circuit, power supply voltage generation circuit, and display device |
| JP228946/04 | 2004-08-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1744440A CN1744440A (en) | 2006-03-08 |
| CN1744440B true CN1744440B (en) | 2011-10-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200510106735 Active CN1744440B (en) | 2004-08-05 | 2005-08-05 | Level conversion circuit, power supply voltage generation circuit, shift circuit, shift register circuit, and display apparatus |
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| Country | Link |
|---|---|
| JP (1) | JP4453476B2 (en) |
| CN (1) | CN1744440B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101205543B1 (en) * | 2006-02-20 | 2012-11-27 | 삼성디스플레이 주식회사 | Display device and method of driving the same |
| KR100805538B1 (en) | 2006-09-12 | 2008-02-20 | 삼성에스디아이 주식회사 | Shift register and organic light emitting display device using the same |
| JP4582216B2 (en) * | 2008-07-12 | 2010-11-17 | ソニー株式会社 | Semiconductor device, display panel and electronic equipment |
| JP5188382B2 (en) * | 2008-12-25 | 2013-04-24 | 三菱電機株式会社 | Shift register circuit |
| KR20110011988A (en) | 2009-07-29 | 2011-02-09 | 삼성전자주식회사 | Level shifter and display apparatus using the same |
| CN103280176B (en) * | 2012-10-26 | 2016-04-27 | 厦门天马微电子有限公司 | A kind of vertical transfer register and control method, IC chip and TFT panel |
| KR101452071B1 (en) * | 2012-12-21 | 2014-10-16 | 삼성전기주식회사 | Driving circuit, driving module and driving apparatus for motor |
| CN105741749B (en) * | 2014-12-08 | 2019-03-12 | 上海和辉光电有限公司 | A kind of LED control signal driving circuit and active matrix type display panel |
| CN106160726B (en) * | 2015-04-17 | 2021-02-09 | 恩智浦美国有限公司 | Voltage level shifter |
| US9912335B2 (en) * | 2015-07-08 | 2018-03-06 | Nxp B.V. | Configurable power domain and method |
| CN106023931A (en) * | 2016-07-21 | 2016-10-12 | 青岛海信电器股份有限公司 | LCD screen and energy-saving control method thereof |
| CN106531117B (en) * | 2017-01-05 | 2019-03-15 | 京东方科技集团股份有限公司 | Shift register, its driving method, grid integrated drive electronics and display device |
| US10110231B1 (en) * | 2017-06-28 | 2018-10-23 | Texas Instruments Incorporated | Level shifter for a wide low-voltage supply range |
| CN108615490B (en) * | 2018-03-16 | 2022-03-01 | 昆山龙腾光电股份有限公司 | Test circuit |
| US10622994B2 (en) * | 2018-06-07 | 2020-04-14 | Vishay-Siliconix, LLC | Devices and methods for driving a semiconductor switching device |
| CN108962119B (en) * | 2018-08-01 | 2021-11-02 | 京东方科技集团股份有限公司 | Level shift circuit, driving method thereof and display device |
| CN111477181B (en) | 2020-05-22 | 2021-08-27 | 京东方科技集团股份有限公司 | Gate driving circuit, display substrate, display device and gate driving method |
| CN114566110A (en) * | 2020-11-27 | 2022-05-31 | 福州京东方光电科技有限公司 | Level conversion circuit, driving circuit of display panel and display device |
| JP2022143791A (en) * | 2021-03-18 | 2022-10-03 | 株式会社ジャパンディスプレイ | Level shift circuit, display panel, and electronic apparatus |
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| US6590423B1 (en) * | 1994-10-11 | 2003-07-08 | Derek Wong | Digital circuits exhibiting reduced power consumption |
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| US6590423B1 (en) * | 1994-10-11 | 2003-07-08 | Derek Wong | Digital circuits exhibiting reduced power consumption |
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| Publication number | Publication date |
|---|---|
| JP2006050288A (en) | 2006-02-16 |
| JP4453476B2 (en) | 2010-04-21 |
| CN1744440A (en) | 2006-03-08 |
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