JP4305317B2 - Shift register circuit and display device - Google Patents

Description

  The present invention relates to a shift register circuit and a display device, and more particularly to a shift register circuit with a level shift function and a display device using the shift register circuit as a part of a drive circuit.

  As a shift register circuit, there is known a shift register circuit having a level shift function for level-shifting (level conversion) a clock pulse serving as a reference for operation from a first amplitude to a second amplitude (see, for example, Patent Document 1). ). This type of shift register circuit is used as a shift register circuit constituting a scanner used in a display device or an imaging device.

  FIG. 23 is a circuit diagram showing an example of the configuration of one transfer stage (shift circuit) of a shift register circuit with a level shift function. As shown in FIG. 23, the shift circuit (transfer stage) 100 according to this example is configured with a current mirror circuit 101 as a basic circuit. The current mirror circuit 101 includes NchMOS transistors (hereinafter abbreviated as “NMOS transistors”) n101 and n102 whose gates are connected to each other, and one NMOS transistor n101 has a diode connection in which the gate and drain are connected in common. ing. Respective phase clocks CK and xCK having a low voltage amplitude (for example, 0 [V] to 3 [V]) are input to the sources of the NMOS transistors n101 and n102, respectively.

  In the current mirror circuit 101, the drain output of the NMOS transistor n102 has a high voltage amplitude of VSS-VDD (for example, 0 [V] -8 [V]), and is output as the transfer pulse OUT after being inverted by the inverter 102. PchMOS transistors (hereinafter abbreviated as “PMOS transistors”) p101 and p102 are connected between the drains of the NMOS transistors n101 and n102 and the power supply potential VDD, respectively.

  NMOS transistors n103 and n104 are connected in series between the drain of the NMOS transistor n101 and the power supply potential VSS. The transfer pulse IN is inverted by the inverter 103 and applied to the gate of the NMOS transistor n103. The drain output of the NMOS transistor n102 is directly given to the gate of the NMOS transistor n104.

  PMOS transistors p103 and p104 are connected in series between the gate of the PMOS transistor p101 and the power supply potential VDD. PMOS transistors p105 and p106 are connected in series between the gate of the PMOS transistor p102 and the power supply potential VDD. PMOS transistors p107 and p108 are connected in parallel between the drain of the NMOS transistor n102 (the drain of the PMOS transistor p102) and the power supply potential VDD.

  The drain output of the NMOS transistor n102 after being inverted by the inverter 102, that is, the transfer pulse OUT is applied to the gates of the PMOS transistors p103, p105, and p107. A transfer pulse IN is directly applied to the gates of the PMOS transistors p104, p106, and p108.

  A clock pulse xCK is applied to the gate of the PMOS transistor p101 via NMOS transistors n105 and n106 connected in parallel to each other. A clock pulse CK is applied to the gate of the PMOS transistor p102 via NMOS transistors n107 and n108 connected in parallel. The transfer pulse IN is directly applied to the gates of the NMOS transistors n105 and n107. A transfer pulse OUT is applied to the gates of the NMOS transistors n106 and n108.

  PMOS transistors p109 and p110 are connected between the gate of the NMOS transistor n103 and the power supply potential VDD, and between the drain of the NMOS transistor n102 (drain of the PMOS transistor p102) and the power supply potential VDD, respectively. A low active reset pulse rst is applied to the gates of the PMOS transistors p109 and p110.

  As is apparent from the circuit configuration described above, the shift circuit 100 of the shift register circuit according to the conventional example has a configuration in which a current mirror type level shift circuit using the current mirror circuit 101 and a shift circuit without clock are combined. The level shift circuit operates when the transfer pulse IN is High or the transfer pulse OUT is High.

JP 2002-287711 A

  The shift circuit 100 with a level shift function according to the conventional example having the above configuration has a circuit configuration based on the current mirror circuit 101, and therefore between the power supply potential VDD and the clock pulses CK and XCK (dotted line arrows in the figure). The leakage current (through current) always flows through the level shift circuit when driving the level shift circuit, and this leakage current increases the power consumption of the shift register circuit.

  Further, since there is a leak between VDD-CK and XCK, the clock pulse CK and xCK require an output capability to absorb the leak, so that the burden of the clock pulse CK and xCK is large, and further the current Since the characteristics of the pair of NMOS transistors n101 and n102 constituting the mirror circuit 101 need to be the same, there is a problem that they are vulnerable to variations in transistor characteristics.

  In particular, in the conventional shift register circuit, the shift circuit 100 with the level shift function having the above-described configuration is simply connected in a plurality of stages and is driven to transfer by clock pulses CK and xCK having opposite phases. There is also a problem that it is difficult to reduce the frequency of the pulses CK and xCK, and thus it is difficult to reduce the burden on the clock generation circuit that generates the clock pulses CK and xCK.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a shift register circuit capable of reducing the burden on the clock generation circuit and the shift register circuit as a part of the drive circuit. The object is to provide an on-board display device.

  Another object of the present invention is to provide a shift register circuit that can reduce power consumption and is resistant to variations in transistor characteristics, and a display device in which the shift register circuit is mounted as part of a driver circuit.

The shift register circuit according to the present invention includes:
When the input control pulse is in an active state and the first clock pulse having the first amplitude is at a low level, a first transfer pulse having a second amplitude larger than the first amplitude is output. A first shift circuit;
When the first transfer pulse is in the active state, and the second of said first of said first amplitude phase-shifted by 1/4 period with respect to the clock pulses with the same frequency a and the first clock pulse a second shift circuit for outputting a second transfer pulse of the second amplitude when the clock pulse is at low level,
A third shift circuit second transfer pulses for outputting a third transfer pulses of said second amplitude when when in the active state, and said first clock pulse is at high level,
When the third transfer pulse is active, and a fourth shift circuit said second clock pulse to output a fourth transfer pulse of the second amplitude at a high level,
The first shift circuit and the second shift circuit are connected in cascade to form a first shift circuit pair, and the third shift circuit and the fourth shift circuit are connected in cascade to form a second shift circuit. A circuit pair, wherein the first shift circuit pair and the second shift circuit pair are alternately connected in cascade,
The first, second, third, and fourth shift circuits include first and second transistors of opposite conductivity type connected in series between a first power supply potential and a second power supply potential. comprising complementarity includes a circuit, given the first of said amplitude to a gate of the first transistor when the level shift driving to the second amplitude first clock pulse or said second clock pulse, the The first clock pulse or the clock pulse obtained by relatively shifting the second clock pulse toward the first power supply potential is applied to the gate of the second transistor.

In the shift register circuit having the above-described configuration, the first shift circuit pair and the second shift circuit pair are alternately connected in cascade, which means that the first, second, third, and fourth shift circuits are connected in cascade. At the same time, it means that the set of four shift circuits is repeatedly arranged and connected in cascade. Then, with respect to the repeated arrangement of the first, second, third and fourth shift circuits, the first clock pulse and the second clock pulse whose phases are shifted from each other by ¼ cycle are alternately given. By doing so, it is possible to realize driving by reducing the frequency of these clock pulses to ½ of the frequency of clock pulses used in a conventional shift register circuit in which shift circuits having the same circuit configuration are repeatedly arranged. In the first and second shift circuits, when the input control pulse and the first transfer pulse are in the active state, and the first and second clock pulses having the first amplitude are low level (hereinafter referred to as “Low potential”). ”) , The second and third transfer pulses having the second amplitude are output. In the third and fourth shift circuits, when the second and third transfer pulses are in an active state and the first and second clock pulses are at a high level (hereinafter referred to as “High potential”) . The third and fourth transfer pulses having the second amplitude are output. That is, in the first to fourth shift circuits, level shift (level conversion) from the first amplitude to the second amplitude is performed.

  In the shift register circuit having the above-described configuration, the first and second shift circuits are connected in series between the first power supply potential and the second power supply potential and have the first and second conductivity types opposite to each other. A first clock terminal to which the first and second clock pulses are input, and the first control terminal is connected between the first clock terminal and the gate of the first transistor. First switch means that is turned on when a pulse is in an active state, and is connected between the second power supply potential and the gate of the second transistor, and is turned off when the control pulse is in an active state. Second switch means, and a first capacitive element connected between the first clock terminal and the gate of the second transistor, and third and fourth shift circuits, The first power supply potential and the first The third and fourth transistors of opposite conductivity type connected in series with each other, the second clock terminal to which the first and second clock pulses are input, and the second A fifth switch means connected between a clock terminal and the gate of the third transistor and turned on when the second control pulse is in an active state; and the second switch potential above the second power supply potential. A sixth power supply connected between a third power supply potential lower by the amplitude voltage of the second clock pulse and the gate of the fourth transistor, and is turned off when the second control pulse is in an active state. Switch means, and a second capacitor element connected between the second clock terminal and the gate of the fourth transistor.

  In the first and second shift circuits having the above-described configuration, when the first control pulse is in the active state, the first switch means is turned on so that the first clock terminal is passed through the first switch means. To the gate of the first transistor is supplied with a clock pulse (first clock pulse in the first shift circuit, second clock pulse in the second shift circuit) and at the same time the second switch means is turned off. Thus, the supply of the second power supply potential to the gate of the second transistor is cut off, the gate of the second transistor is in a floating state, and the gate of the second transistor is connected to the first capacitor element. A clock pulse is transmitted by coupling.

  At this time, the clock pulses applied to the gates of the first and second transistors have the same phase, but the high-level potential of the clock pulse applied to the gate of the second transistor becomes the second power supply potential. The potential on the high level side of the clock pulse applied to the gate of the first transistor is relatively shifted. The amplitude of the clock pulse is larger than the threshold value Vth of the first and second transistors. As a result, the first and second transistors are surely turned off from the relationship of the gate potential at the timing to be turned off. Therefore, in the complementary circuit composed of the first and second transistors, leakage when these transistors are off can be reliably prevented. In the third and fourth shift circuits, basically the same operations as those in the first and second shift circuits are performed.

  According to the present invention, it is possible to drive with a clock pulse having a frequency ½ that of a conventional shift register circuit in which a shift circuit having the same configuration is repeatedly arranged in a plurality of stages. The burden on the circuit can be reduced to ½, and the driving frequency can be reduced to ½, so that power consumption can be reduced.

  In addition, since it is possible to reliably prevent leakage at the time of the level shift portion, it is possible to reduce power consumption and to provide a shift register circuit that is resistant to variations in transistor characteristics because it employs a circuit configuration that does not use a current mirror circuit. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a shift register circuit according to the first embodiment of the present invention. In the shift register circuit 10 according to the present embodiment, the first shift circuit 11-1 and the second shift circuit 11-2 are connected in cascade, and the third shift circuit 11-3 and the fourth shift circuit are connected. 11-4 is connected in cascade, and the two shift circuit pairs are alternately connected in cascade. In other words, the shift circuits 11-1 to 11-4 are connected in cascade as shift register units (transfer stages / shift stages), and a set of these four shift circuits 11-1 to 11-4 is repeatedly arranged. The configuration is cascaded.

  As will be described in detail later, the first shift circuit 11-1 and the second shift circuit 11-2 have the same circuit configuration, and the third shift circuit 11-3 and the fourth shift circuit 11-4 has the same circuit configuration. The first clock pulse CK1 is supplied to the first and third shift circuits 11-1 and 11-3, and the first clock is supplied to the second and fourth shift circuits 11-2 and 11-4. A second clock pulse CK2 having the same frequency as that of the pulse CK1 and having a phase shifted by ¼ period with respect to the clock pulse CK1 is provided.

  A high active start pulse ST is supplied as a control pulse IN to the first-stage shift circuit 11-1. When the control pulse IN is in the active state (high potential), the shift circuit 11-1 extracts the low potential side pulse (active low) of the first clock pulse CK1, and extracts the low potential side pulse from the first amplitude. The level is shifted to the second amplitude and output. The high active output pulse OUT of the shift circuit 11-1 is given as the control pulse IN to the second stage shift circuit 11-2.

  When the control pulse IN is in the active state, the second-stage shift circuit 11-2 extracts the low potential side pulse of the second clock pulse CK2 and converts the low potential side pulse from the first amplitude to the second amplitude. Level shift to output. The high active output pulse OUT of the shift circuit 11-2 is given to the third-stage shift circuit 11-3 as its control pulse IN.

  When the control pulse IN is in an active state, the third-stage shift circuit 11-3 extracts the High potential side pulse (active High) of the first clock pulse CK1, and extracts the High potential side pulse from the first amplitude. The level is shifted to the second amplitude and output. The high active output pulse OUT of the shift circuit 11-3 is given as the control pulse IN to the fourth-stage shift circuit 11-4.

  When the control pulse IN is in an active state, the fourth-stage shift circuit 11-4 extracts the High potential side pulse of the second clock pulse CK2 and converts the High potential side pulse from the first amplitude to the second amplitude. Level shift to output. The high active output pulse OUT of the shift circuit 11-4 is given to the fifth-stage shift circuit 11-5 as its control pulse IN.

  Thereafter, each circuit operation in the group of these four stages of shift circuits 11-1 to 11-4 is repeated.

  In the shift circuits (transfer stages) 11-1, 11-2,..., The input pulse (control pulse) IN of the own stage and the output pulse OUT of the own stage are the outputs of the 3-input AND circuits 12-1, 12-2,. 2 inputs. The AND circuits 12-1, 12-2,... Are supplied with a low active enable pulse EN having a very narrow pulse width as compared with the pulse widths of the clock pulses CK1 and CK2, as the remaining one input. The high active output pulses of the AND circuits 12-1, 12-2,... Are derived as transfer pulses o1, o2,. The enable pulse EN may be used only when it is desired to provide a blanking period between the transfer pulses.

FIG. 2 shows the timing relationship between the first and second clock pulses CK1 and CK2, the enable pulse EN, the start pulse ST, the first stage, the second stage output pulse SR_out, and the transfer pulses o1, o2, o3,. . As is apparent from this timing chart, in the shift circuits 11-1, 11-2,..., The clock pulses CK1 and CK2 having the first amplitude (VSS−Vin) are extracted and the second amplitude (VSS−). (VDD) transfer pulses o1, o2, o3,... Here, extracting the pulse referred to in this specification means that the shift circuits 11-1, 11-2,... Are controlled by the start pulse ST and the output pulse SR_out of each stage, and the clock pulse having the first amplitude. This means that transfer pulses o1, o2, o3,... Having the second amplitude are output based on CK1 and CK2.

  As described above, in the shift register circuit 10 according to the first embodiment, the first shift circuit 11-1 and the second shift circuit 11-2 are connected in cascade, and the third shift circuit 11-3 is connected. And the fourth shift circuit 11-4 are cascade-connected as a pair, and these two shift circuit pairs are alternately cascade-connected, and the phase is mutually different with respect to the repeated arrangement of the shift register units (transfer stages). A clock pulse CK1 and a clock pulse CK2 that are shifted by a quarter cycle are alternately applied to each other, so that the frequency of these clock pulses CK1 and CK2 is repeatedly arranged with shift register units having the same circuit configuration. Thus, it is possible to realize driving with the frequency lowered to half the frequency of the clock pulses CK and xCK used in the shift register circuit.

  As a result, the burden on the clock generation circuit (not shown) for generating the clock pulses CK1 and CK2 can be reduced to 1/2, and the drive frequency can be reduced to 1/2, thereby reducing the power consumption of the shift register circuit 10 itself. Electricity can be achieved.

  Next, specific configurations of the first to fourth shift circuits (shift register units) 11-1 to 11-4 will be described.

  FIG. 3 is a block diagram showing an example of the configuration of the first and second shift circuits 11-1 and 11-2. As shown in FIG. 3, the shift circuits 11-1 and 11-2 according to this example are configured to include a level shift unit 20 and a control pulse generation unit 40.

  The level shift unit 20 changes the clock pulse CK from VSS-Vin amplitude (for example, 0 [V] -3 [V] amplitude) to VSS-VDD when the control pulse NSW supplied from the control pulse generator 40 is in an active state. The level is shifted to an amplitude (for example, 0 [V] -8 [V] amplitude), and output as an output pulse OUT. The control pulse generator 40 uses the input pulse of its own stage as one input IN1, the output pulse OUT of its own stage as the other input, and controls the driving state of the level shift unit 20 based on these input pulses IN1 and IN2. Therefore, control pulses NSW and PSW having opposite phases are generated.

  Here, specific circuit configurations of the level shift unit 20 and the control pulse generation unit 40 will be described. First, the circuit configuration of the level shift unit 20 will be described.

  FIG. 4 is a circuit diagram showing an example of the configuration of the level shift unit (LS1) 20. As shown in FIG. 4, the level shift unit 20 according to this example includes a complementary circuit 21, first to fifth switch circuits 22 to 26, a capacitive element Cap and a buffer 27, a clock terminal 28, and a control terminal. 29, 30, a voltage terminal 31, and an output terminal 32.

  The complementary circuit 21 includes first and second transistors of opposite conductivity types connected in series between the power supply potential VSS and the power supply potential VDD, that is, an NMOS transistor n11 and a PMOS transistor p11. The drains of the NMOS transistor n11 and the PMOS transistor p11 are connected to the circuit output terminal 28 via the buffer 27.

  The first switch circuit 22 includes a CMOS switch including an NMOS transistor n21 and a PMOS transistor p21 connected in parallel to each other. One end of the CMOS switch is connected to the clock terminal 28 and the other end is a gate of the NMOS transistor n11. The gates are connected to the control terminals 29 and 30, respectively.

  The clock terminal 28 has a clock pulse CK1 / CK2 having an amplitude of VSS-Vin (for example, 0 [V] -3 [V] amplitude) (in the first shift circuit 11-1, the clock pulse CK1 and the second shift circuit 11). -2 gives the clock pulse CK2). Note that the high potential Vin of the clock pulse CK1 / CK2 needs to be larger than the threshold value Vth of the transistor (VDD> Vin> Vth).

  The control terminals 29 and 30 are supplied with control pulses NSW and PSW having opposite phases generated by the control pulse generator 40, respectively. The control pulse NSW is a high active pulse signal, and the control pulse PSW is a low active pulse signal. The voltage terminal 31 is supplied with a constant potential Vref1 (for example, the High potential Vin of the clock pulses CK1 / CK2).

  The second switch circuit 23 is constituted by a CMOS switch including an NMOS transistor n22 and a PMOS transistor p22 connected in parallel to each other. One end of the CMOS switch is at the power supply potential VDD and the other end is the gate of the PMOS transistor p11. The gates are connected to the control terminals 29 and 30, respectively. The second switch circuit 23 is turned off when the control pulses NSW and PSW are in the active state, thereby cutting off the electrical connection between the power supply potential VDD and the gate of the PMOS transistor p11, and the PMOS transistor p11. Float the gate.

  The third switch circuit 24 is constituted by a CMOS switch including an NMOS transistor n23 and a PMOS transistor p23 connected in parallel to each other. One end of the CMOS switch is at the power supply potential VDD and the other end is the gate of the NMOS transistor n11. The gates are connected to the control terminals 29 and 30, respectively. The third switch circuit 24 is turned off when the control pulses NSW and PSW are in the active state, thereby cutting off the electrical connection between the power supply potential VDD and the gate of the NMOS transistor n11.

  The fourth switch circuit 25 is configured by a CMOS switch including an NMOS transistor n24 and a PMOS transistor p24 connected in parallel to each other. One end of the CMOS switch is connected to the clock terminal 28 and the other end is connected to one end of the capacitive element Cap. The gates are connected to the control terminals 29 and 30, respectively. The fourth switch circuit 25 is turned on when the control pulses NSW and PSW are in the active state and supplies the clock pulse CK to one end of the capacitor Cap, and is turned off when the control pulses NSW and PSW are in the inactive state. As a result, the electrical connection between the clock terminal 28 and one end of the capacitive element Cap is cut off.

  The fifth switch circuit 26 includes a CMOS switch including an NMOS transistor n25 and a PMOS transistor p25 connected in parallel to each other. One end of the CMOS switch is connected to the voltage terminal 31 and the other end is connected to one end of the capacitive element Cap. Thus, a negative-phase control pulse PSW is applied to the gate of the NMOS transistor n25, and a positive-phase control pulse NSW is applied to the gate of the PMOS transistor p25. The fifth switch circuit 26 is turned off when the control pulses NSW and PSW are in an active state, and disconnects the electrical connection between the voltage terminal 31 and one end of the capacitive element Cap. When the PSW is in an inactive state, it is turned on to electrically connect the voltage terminal 31 and one end of the capacitive element Cap.

  The capacitive element Cap is connected between the other ends of the fourth and fifth switch circuits 25 and 26 and the gate of the NMOS transistor n11. Thus, when the fourth switch circuit 25 is in the ON state, the clock pulse CK is applied to one end of the capacitive element Cap through the switch circuit 25, and is transmitted to the gate of the PMOS transistor p11 by the coupling by the capacitive element Cap. Will be.

  The buffer 27 is composed of, for example, an inverter buffer circuit. However, the buffer 27 is not essential and is arranged as necessary.

Next, the circuit operation of the level shift unit 20 configured as described above will be described with reference to the timing chart of FIG .

First, when the control pulses NSW and PSW are inactive, the first and fourth switch circuits 22 and 25 are turned off, and the second, third and fifth switch circuits 23, 24 and 26 are turned on. Therefore, regardless of the logic state of the clock pulse CK (CK1 / CK2), the potential VA of the node A (the gate of the PMOS transistor p11 ) and the potential VB of the node B ( the gate of the NMOS transistor n11 ) are the power supply potential VDD. Accordingly, the PMOS transistor p11 is turned off and the NMOS transistor n11 is turned on, so that the output pulse OUT becomes the power supply potential VSS.

  When the control pulses NSW and PSW are in the active state, that is, in the driving state of the level shift unit 20, the first and fourth switch circuits 22 and 25 are in the on state, and the second, third, and fifth switch circuits 23, Since 24 and 26 are turned off, the node A enters a floating state, and receives the coupling of the clock pulse CK through the capacitive element Cap. A clock pulse CK is supplied to the node B through the first switch circuit 22.

  In the active period of the control pulses NSW and PSW, the low potential side pulse of the clock pulse CK (CK1 / CK2), that is, the extraction of the active low pulse and the level shift (level conversion) from the VSS-Vin amplitude to the VSS-VDD amplitude are performed. Each process will be performed.

  Further, the clock amplitude of the node B during the active period of the control pulses NSW and PSW is VSS / Vin, the clock amplitude of the node A is VDD−Vin / VDD, and the clocks applied to the nodes A and B are in phase. Thereby, the PMOS transistor p11 and the NMOS transistor n11 are surely turned off from the relationship between the potentials VA and VB of the nodes A and B at the timing to be turned off. Therefore, in the complementary circuit 21 composed of the PMOS transistor p11 and the NMOS transistor n11, it is possible to reliably prevent leakage when the MOS transistors p11 and n11 are turned off.

  As described above, a clock pulse CK having an amplitude of VSS-Vin (for example, 0 [V] -3 [V]) is leveled to an output pulse OUT having an amplitude of VSS-VDD (for example, 0 [V] -8 [V]). In the level shift unit 20 to be shifted, the complementary circuit 21 including the NMOS transistor n11 and the PMOS transistor p11 is a basic circuit, and the clock pulse CK is given to the gate of the NMOS transistor n11 during the level shift driving, while the gate of the PMOS transistor p11 is given. Provides a clock pulse obtained by relatively shifting the clock pulse CK to the power supply potential VDD side by coupling with the cap element Cap, so that the NMOS transistor n11 and the PMOS transistor p11 are surely turned off at the timing to be turned off. ,phase Leakage current does not flow through the sex circuit 21.

  As described above, since the leakage current does not flow through the level shift unit 20, the power consumption of the shift register circuit 10 can be reduced. Further, since the complementary circuit 21 composed of a reverse conductivity type transistor is used as a basic circuit, there is no leakage current and the transistor is always driven in the saturation region of the transistor. Therefore, the current mirror circuit is used as a basic circuit. A level shift unit 20 that is resistant to variations in transistor characteristics (threshold Vth, drain-source current Ids, etc.) as seen in such a level shift circuit, that is, circuit performance due to variations in transistor characteristics, can be realized. In addition, since there is no leakage between the power supply potential VDD and the clock pulse CK, the burden on the clock pulse CK can be reduced.

  In addition, when the control pulses NSW and PSW are in an inactive state, the fourth switch circuit 25 is turned off and the electrical connection between the clock terminal 26 and the node C (one end of the capacitive element Cap) is cut off. In addition, the influence of the clock pulse CK does not reach the node A, and the fifth switch circuit 26 is turned on to electrically connect the voltage terminal 31 and the node C, and the potential of the node C By fixing VC to a constant potential Vref1 (= Vin), it is possible to prevent the coupling of the clock pulse CK through the capacitive element Cap from reaching the node A. Therefore, beard-like noise caused by the fluctuation of the potential VA of the node A Can be prevented from appearing in the output pulse OUT.

  In addition, since the first and fourth switch circuits 22 and 25 are configured using CMOS switches, there is a concern about the on-resistance of the NMOS transistor when the switch circuits 22 and 25 are configured by the NMOS transistor alone, that is, the on-state. The concern that the on-resistance becomes higher when the high-side potential Vin of the clock pulse CK (CK1 / CK2) is higher than the gate voltage VDD at that time can be eliminated by the action of the PMOS transistors p21 and p24.

  In addition, since the second, third, and fifth switch circuits 23, 24, and 26 are formed of CMOS switches, the gate-drain or gate in the case where the switch circuits 23, 24, and 26 are formed of an NMOS transistor alone. The concern caused by the coupling between the sources, that is, the concern that the circuit malfunctions due to the jump due to the coupling can be eliminated by the action of the PMOS transistors p22, p23, and p25.

  In this example, the first to fifth switch circuits 22 to 26 are configured by CMOS switches to solve the above concerns. However, this solution is not always necessary, and circuit constants and driving are not necessarily required. Depending on the conditions (various voltage setting values), it is possible to examine the necessity of countermeasures for each of the above-mentioned concerns and to select the presence or absence of countermeasures.

  Next, the circuit configuration of the control pulse generator 40 will be described. FIG. 6 is a block diagram illustrating an example of the configuration of the control pulse generator 40.

  As shown in FIG. 6, the control pulse generator 40 according to this example includes a NOR circuit 41, a switch circuit 42, two inverter circuits 43A and 43B, and a reset circuit 44, and two input terminals 45, 46, 2 The configuration includes two output terminals 47 and 48 and a reset terminal 49.

  The input terminal 45 receives an input pulse IN1 having the same pulse width as the clock pulse CK (CK1 / CK2). This input pulse IN1 corresponds to the input pulse of its own stage in the shift register circuit 10. The input terminal 46 receives as input an input pulse IN2 whose phase is shifted by a quarter period of the clock pulse CK with respect to the input pulse IN1. This input pulse IN2 corresponds to the output pulse of its own stage in the shift register circuit 10.

  The NOR circuit 41 takes a negative OR of the input pulse IN1 and the input pulse IN2. The switch circuit 42 is configured by a CMOS switch including an NMOS transistor n31 and a PMOS transistor p31 connected in parallel to each other, and an input terminal is connected to an output terminal of the NOR circuit 41. In the switch circuit 42, the reset pulse rst input via the reset terminal 49 is directly given to the gate of the NMOS transistor n31, and the reset pulse rst is inverted and given by the inverter circuit 43A to the gate of the PMOS transistor p31. . The reset pulse rst is a low active pulse signal.

  The reset circuit 44 is connected between the power supply potential VDD and the output terminal of the switch circuit 42, and includes a PMOS transistor p32 having a reset pulse rst as a gate input. In the reset circuit 44, when the reset pulse rst becomes the low potential, the PMOS transistor p32 is turned on, and the reset operation for setting the output terminal potential of the switch circuit 42 to the power supply potential VDD is performed.

  The inverter circuit 43B inverts the output pulse of the switch circuit 42 to generate a positive-phase control pulse NSW and outputs it through the output terminal 47. Further, the output pulse of the switch circuit 42 is outputted as it is as a control pulse PSW having a reverse phase through the output terminal 48. FIG. 7 shows the timing relationship between the input pulses IN1, IN2 and the control pulses NSW, PSW.

  In the control pulse generator 40 having the above configuration, the reset pulse rst is set to Low (power supply potential VSS), whereby both the NMOS transistor n31 and the PMOS transistor p31 of the switch circuit 42 are turned off, and the PMOS transistor of the reset circuit 44 p32 is turned on to fix the input terminal of the inverter circuit 43B to the power supply potential VDD. As a result, the control pulse generator 40 outputs the control pulses NSW and PSW in the inactive state, and makes the level shift unit 20 inactive. When the reset pulse rst is High (power supply potential VDD), the switch circuit 42 is turned on and the reset circuit 44 is turned off. Therefore, the control pulse generator 40 outputs the control pulses NSW and PSW in the active state, and the level shift The unit 20 enters an operating state.

  FIG. 8 is a block diagram showing an example of the configuration of the third and fourth shift circuits 11-3 and 11-4. In FIG. 8, the same parts as those in FIG.

  As shown in FIG. 8, the shift circuits 11-3 and 11-4 according to this example are configured to include a level shift unit 50, a control pulse generation unit 40, and an inverter circuit INV. As the control pulse generator 40, one having the same configuration as the control pulse generator 40 of the first and second shift circuits 11-1 and 11-2 is used. However, in the shift circuits 11-3 and 11-4 according to this example, the output pulse OUT of the level shift unit 50 is inverted by the inverter circuit INV and derived as an output pulse of its own stage.

  The third and fourth shift circuits 11-3 and 11-4 are different from the first and second shift circuits 11-1 and 11-2 in the following points. That is, as described above, when the control pulse IN is in the active state, the first and second shift circuits 11-1 / 11-2 extract the active low of the clock pulses CK1 / CK2 and perform level shift. On the other hand, the third and fourth shift circuits 11-3 / 11-4 extract the active high of the clock pulses CK1 / CK2 and perform level shift.

  The level shift units 20 and 50 execute these different processes. The level shift circuit 50 is basically the same as the level shift unit 20 in configuration because the basic processing is the same as that of the level shift unit 20.

  FIG. 9 is a circuit diagram showing an example of the configuration of the level shift unit (LS2) 50. As shown in FIG. Since the level shift circuit 50 has the same components as the level shift unit 20, in FIG. 9, the same parts as those in FIG.

  That is, as shown in FIG. 9, the level shift unit 50 according to this example includes a complementary circuit 21, first to fifth switch circuits 22 to 26, a capacitive element Cap and a buffer 27, and a clock terminal 28, In addition to the provision of the control terminals 29 and 30, the voltage terminal 31 and the output terminal 32, in order to execute processing different from the level shift unit 20, a third power supply potential VSS and VDD are added to the third power supply potential VSS and VDD. The power supply potential VDD2 is used.

  Here, the third power supply potential VDD2 is set to (VDD−Vin) when the amplitude of the clock pulse CK (CK1 / CK2) is VSS−Vin. The second switch circuit 23 is connected between the power supply potential VDD2 and the gate of the PMOS transistor p11, and the third switch circuit 24 is connected between the power supply potential VSS and the gate of the NMOS transistor n11. Become. The voltage terminal 31 is supplied with a constant potential Vref2 (for example, the power supply potential VSS).

  Next, the circuit operation of the level shift unit 50 configured as described above will be described with reference to the timing chart of FIG.

  First, when the control pulses NSW and PSW are inactive, the first and fourth switch circuits 22 and 25 are turned off, and the second, third and fifth switch circuits 23, 24 and 26 are turned on. Therefore, regardless of the logic state of the clock pulse CK (CK1 / CK2), the potential VA of the node A (the gate of the PMOS transistor p11) is the power supply potential VDD2 (VDD-Vin), and the node B (the NMOS transistor n11) gate. The potential VB is the power supply potential VSS. Accordingly, the PMOS transistor p11 is turned on and the NMOS transistor n11 is turned off, so that the output pulse OUT becomes the power supply potential VDD.

  When the control pulses NSW and PSW are in the active state, that is, in the driving state of the level shift unit 50, the first and fourth switch circuits 22 and 25 are in the on state, and the second, third, and fifth switch circuits 23, Since 24 and 26 are turned off, the node A enters a floating state, and receives the coupling of the clock pulse CK through the capacitive element Cap. A clock pulse CK is supplied to the node B through the first switch circuit 22.

  In the active period of the control pulses NSW and PSW, the high potential side pulse of the clock pulse CK (CK1 / CK2), that is, the extraction of the active high pulse and the level shift (level conversion) from the VSS-Vin amplitude to the VSS-VDD amplitude are performed. Each process will be performed.

  Further, the clock amplitude of the node B during the active period of the control pulses NSW and PSW is VSS / Vin, the clock amplitude of the node A is VDD−Vin / VDD, and the clocks applied to the nodes A and B are in phase. Thereby, the PMOS transistor p11 and the NMOS transistor n11 are surely turned off from the relationship between the potentials VA and VB of the nodes A and B at the timing to be turned off. Therefore, in the complementary circuit 21 composed of the PMOS transistor p11 and the NMOS transistor n11, it is possible to reliably prevent leakage when the MOS transistors p11 and n11 are turned off.

As described above, in the level shift unit 50 that level-shifts the clock pulse CK having the VSS-Vin amplitude to the output pulse OUT having the VSS-VDD amplitude, the complementary circuit 21 including the NMOS transistor n11 and the PMOS transistor p11 is used as a basic circuit. At the time of level shift driving, a clock pulse CK is applied to the gate of the NMOS transistor n11, while a clock pulse obtained by relatively shifting the clock pulse CK to the power supply potential VDD side by coupling by the capacitive element Cap is applied to the gate of the PMOS transistor p11. As a result, the NMOS transistor n11 and the PMOS transistor p11 are surely turned off at the timing when they should be turned off, so that no leak current flows through the complementary circuit 21.

  As described above, the leakage current does not flow in the level shift unit 50, so that the power consumption of the shift register circuit 10 can be reduced. Further, since the complementary circuit 21 composed of a reverse conductivity type transistor is used as a basic circuit, there is no leakage current and the transistor is always driven in the saturation region of the transistor. Therefore, the current mirror circuit is used as a basic circuit. It is possible to realize a level shift unit 50 that is resistant to variations in transistor characteristics (threshold Vth, drain-source current Ids, etc.) as seen in such a level shift circuit, that is, circuit performance is not greatly affected by variations in transistor characteristics. In addition, since there is no leakage between the power supply potential VDD and the clock pulse CK, the burden on the clock pulse CK can be reduced. Other functions and effects are the same as those of the level shift unit 20.

[Second Embodiment]
FIG. 11 is a block diagram showing a configuration of a shift register circuit according to the second embodiment of the present invention. Similarly to the shift register 10 circuit according to the first embodiment, the shift register circuit 60 according to the present embodiment includes the first to fourth shift circuits 61-1 to 61-4 as shift register units (transfer stages / shift stages). ), And a group of the four shift circuits 61-1 to 61-4 is repeatedly arranged and connected in cascade.

  As will be described in detail later, the first shift circuit 61-1 and the second shift circuit 61-2 have the same circuit configuration, and the third shift circuit 61-3 and the fourth shift circuit. 61-4 has the same circuit configuration. The first clock pulse CK1 is supplied to the first and third shift circuits 61-1 and 61-3, and the first clock is supplied to the second and fourth shift circuits 61-2 and 61-4. A second clock pulse CK2 having the same frequency as that of the pulse CK1 and having a phase shifted by ¼ period with respect to the clock pulse CK1 is provided.

  A low active start pulse ST is supplied as a control pulse IN to the first-stage shift circuit 61-1. When the control pulse IN is in the active state (low potential), the shift circuit 61-1 extracts the low potential side pulse (active low) of the first clock pulse CK1 and extracts the low potential side pulse from the first amplitude. The level is shifted to the second amplitude and output. The Low active output pulse OUT of the shift circuit 61-1 is given to the second-stage shift circuit 61-2 as its control pulse IN.

  When the control pulse IN is in the active state, the second-stage shift circuit 61-2 extracts the low potential side pulse of the second clock pulse CK2 and converts the low potential side pulse from the first amplitude to the second amplitude. Level shift to output. The output Low active pulse OUT of the shift circuit 61-2 is given to the third-stage shift circuit 61-3 as its control pulse IN.

  When the control pulse IN is in the active state, the third-stage shift circuit 61-3 extracts the High potential side pulse (active High) of the first clock pulse CK1, and extracts the High potential side pulse from the first amplitude. The level is shifted to the second amplitude and output. The Low active output pulse OUT of the shift circuit 61-3 is given to the fourth-stage shift circuit 61-4 as its control pulse IN.

  When the control pulse IN is in an active state, the fourth-stage shift circuit 61-4 extracts the High potential side pulse of the second clock pulse CK2 and converts the High potential side pulse from the first amplitude to the second amplitude. Level shift to output. The Low active output pulse OUT of the shift circuit 61-4 is given to the fifth shift circuit 61-5 as its control pulse IN.

  Thereafter, each circuit operation in the group of these four stages of shift circuits 61-1 to 61-4 is repeated.

  In the shift circuits (transfer stages) 61-1, 61-2,..., The input pulse (control pulse) IN of the own stage and the output pulse OUT of the own stage of the three-input NOR circuits 62-1, 62-2,. 2 inputs. The NOR circuit 62-1, 62-2,... Is supplied with a high active enable pulse EN having a very narrow pulse width as compared with the pulse widths of the clock pulses CK1 and CK2, as the remaining one input. The high active output pulses of the NOR circuits 62-1, 62-2,... Are derived as transfer pulses o1, o2,.

  FIG. 12 shows the timing relationship between the first and second clock pulses CK1 and CK2, the enable pulse EN, the start pulse ST, the first stage, the second stage output pulse SR_out, and the transfer pulses o1, o2, o3,. . As is apparent from this timing chart, in the shift circuits 61-1, 61-2,..., The clock pulses CK1 and CK2 having the first amplitude (VSS−Vin) are extracted and the second amplitude (VSS−). (VDD) transfer pulses o1, o2, o3,...

  As described above, also in the shift register circuit 60 according to the second embodiment, the first shift circuit 61-1 and the second shift circuit 61-2 are connected in cascade, and the third shift circuit 61- 3 and the fourth shift circuit 61-4 are cascade-connected as a pair, and these two shift circuit pairs are alternately cascade-connected, and the phase is different from the repetitive arrangement of these shift register units (transfer stages). By alternately supplying the clock pulse CK1 and the clock pulse CK2 that are shifted from each other by ¼ period, the frequency of the clock pulses CK1 and CK2 is repeatedly arranged by shift register units having the same circuit configuration. Since it is possible to realize driving with a frequency reduced to ½ of the frequency of the clock pulses CK and xCK used in the conventional shift register circuit, the clock pulse C 1, with the burden of CK2 to a clock generating circuit for generating a can be reduced to 1/2, the driving frequency can reduce the power consumption of the shift register circuit 60 itself by being able to reduce to 1/2.

  Next, a specific configuration of the first to fourth shift circuits (shift register units) 61-1 to 61-4 will be described.

  FIG. 13 is a block diagram showing an example of the configuration of the first and second shift circuits 61-1 and 61-2. In FIG. 13, the same parts as those in FIG. As shown in FIG. 13, the shift circuits 61-1 and 61-2 according to the present example are configured to include a level shift unit 20, a control pulse generation unit 70, and an inverter circuit INV. That is, the level shift unit 20 is the same as the level shift unit 20 described in the shift register circuit 10 according to the first embodiment, and the specific circuit configuration (FIG. 4) is also the same.

  Here, a specific circuit configuration of the control pulse generator 70 will be described. FIG. 14 is a block diagram illustrating an example of the configuration of the control pulse generator 70.

  As shown in FIG. 14, the control pulse generator 70 according to this example includes a NAND circuit 71, a switch circuit 72, two inverter circuits 73A and 73B, and a reset circuit 74, and two input terminals 75, 76, 2 The configuration includes two output terminals 77 and 78 and a reset terminal 79.

  The input terminal 75 receives an input pulse IN1 having the same pulse width as the clock pulse CK (CK1 / CK2). This input pulse IN1 corresponds to the input pulse of its own stage in the shift register circuit 60. The input terminal 76 receives an input pulse IN2 that is out of phase by a quarter of the clock pulse CK with respect to the input pulse IN1. This input pulse IN2 corresponds to the output pulse of its own stage in the shift register circuit 60.

  The NAND circuit 71 takes a negative logical product of the input pulse IN1 and the input pulse IN2. The switch circuit 72 is constituted by a CMOS switch composed of an NMOS transistor n41 and a PMOS transistor p41 connected in parallel to each other, and an input terminal is connected to an output terminal of the NAND circuit 71. In the switch circuit 72, the reset pulse rst input through the reset terminal 79 is inverted and applied to the gate of the NMOS transistor n41 by the inverter circuit 73A, and the reset pulse rst is directly applied to the gate of the PMOS transistor p41. . The reset pulse rst is a high active pulse signal.

  The reset circuit 74 is connected between the output terminal of the switch circuit 72 and the power supply potential VSS, and includes an NMOS transistor n42 that receives the reset pulse rst as a gate input. In the reset circuit 74, when the reset pulse rst becomes a high potential, the NMOS transistor n42 is turned on, and a reset operation for setting the output terminal potential of the switch circuit 72 to the power supply potential VSS is performed.

  The inverter circuit 73B inverts the output pulse of the switch circuit 72 to generate a reverse-phase control pulse PSW and outputs it through the output terminal 78. Further, the output pulse of the switch circuit 72 is outputted as a positive-phase control pulse NSW through the output terminal 77 as it is. FIG. 15 shows the timing relationship between the input pulses IN1 and IN2 and the control pulses NSW and PSW.

  In the control pulse generator 70 having the above configuration, the reset pulse rst is set to High (power supply potential VDD), so that both the NMOS transistor n41 and the PMOS transistor p41 of the switch circuit 72 are turned off and the NMOS transistor of the reset circuit 74 is turned off. n42 is turned on to fix the input terminal of the inverter circuit 73B to the power supply potential VSS. As a result, the control pulse generation unit 70 outputs the control pulses NSW and PSW in the inactive state, and makes the level shift unit 20 inactive. When the reset pulse rst is Low (power supply potential VSS), the switch circuit 72 is turned on and the reset circuit 74 is turned off. Therefore, the control pulse generator 70 outputs the control pulses NSW and PSW in the active state, and level shift The unit 20 enters an operating state.

  As described above, the first and second shift circuits 61-1 and 61-2 are a combination of the control pulse generator 70 and the level converter 20 according to this example. In the case of the shift circuits 61-3 and 61-4, as shown in FIG. 16, the control pulse generator 70 and the level converter 50 (FIG. 9) according to this example are combined.

  Next, specific circuit configurations of various circuit blocks used in the shift register circuits 10 and 60 according to the first and second embodiments will be described.

  First, the 3-input AND circuits 12-1, 12-2,... Used in the shift register circuit 10 according to the first embodiment will be described with reference to FIG. As shown in FIG. 17, the 3-input AND circuit is connected in parallel between the NMOS transistor n51, n52, n53 connected in series between the node N11 and the power supply potential VSS, and between the power supply potential VDD and the node N11. PMOS transistors p51, p52, and p53, and the potential of the node N11 is inverted by the inverter INV when three inputs IN1, IN2, and IN3 are given to the gates of the transistors n51 to n53 and p51 to p53, respectively. Thus, the configuration is derived as a logical product output.

  As shown in FIG. 18, the inverter circuit INV and the inverter circuits used in the shift register circuits 10 and 60 according to the first and second embodiments are provided between a power supply potential VDD and a power supply potential VSS. A CMOS inverter is used which is connected in series and has a gate and a drain connected in common.

  Next, a two-input NOR circuit 41 used in the control pulse generator 40 of the shift register circuit 10 according to the first embodiment will be described with reference to FIG. As shown in FIG. 19, the 2-input NOR circuit is connected in parallel between the PMOS transistors p55 and p56 connected in series between the power supply potential VDD and the node N12, and between the node N12 and the power supply potential VSS. NMOS transistors n55 and n56 are provided, and the potential of node N12 when two inputs IN1 and IN2 are given to the gates of these transistors p55, p56, n55 and n56 is derived as a negative OR output. ing.

  Next, three-input NOR circuits 62-1, 62-2,... Used in the shift register circuit 60 according to the second embodiment will be described with reference to FIG. As shown in FIG. 20, the three-input NOR circuit is connected in series between the NMOS transistors n61, n62, and n63 connected in parallel between the node N13 and the power supply potential VSS, and between the power supply potential VDD and the node N13. PMOS transistors p61, p62, and p63, and outputs the potential of the node N13 when the three inputs IN1, IN2, and IN3 are given to the gates of the transistors n61 to n63 and p61 to p63, respectively. It is the structure derived as.

  Finally, a two-input NAND circuit 71 used in the control pulse generator 70 of the shift register circuit 60 according to the second embodiment will be described with reference to FIG. As shown in FIG. 21, the 2-input NAND circuit is connected in series between PMOS transistors p65 and p66 connected in parallel between the power supply potential VDD and the node N14, and between the node N14 and the power supply potential VSS. And a configuration for deriving the potential of the node N14 as a negative AND output when two inputs IN1 and IN2 are given to the gates of the transistors p65, p66, n65, and n66, respectively. It has become. The logic circuits in FIGS. 17 to 21 are examples, and can be replaced as long as they operate in the same manner.

  The shift register circuits 10 and 60 according to the first and second embodiments described above can be used as a general shift register circuit with a level shift function. As an example, pixels including electro-optical elements are arranged in a matrix. A shift register constituting a scanner for a vertical driver or a horizontal driver in a display device integrated with a drive circuit in which a peripheral drive circuit for driving a pixel array unit arranged two-dimensionally is formed on the same substrate as the pixel array unit It can be used as a circuit.

(Application example)
FIG. 22 is a block diagram illustrating an example of a configuration of a display device according to an application example of the present invention. Here, an active matrix liquid crystal display device using a liquid crystal cell as an electro-optic element of a pixel will be described as an example of the display device.

  As shown in FIG. 22, an active matrix liquid crystal display device 80 according to this application example includes a pixel array unit 81, a vertical driver 82, a horizontal driver 83, and the like, and peripheral drive circuits such as the vertical driver 82 and the horizontal driver 83. Are integrally formed on the same liquid crystal panel 84 as the pixel array portion 81. The liquid crystal panel 84 has a configuration in which two insulating substrates, for example, glass substrates are arranged to face each other with a certain gap, and a liquid crystal material is sealed in the gap.

  In the pixel array unit 81, the pixels 90 are two-dimensionally arranged in m rows and n columns. Further, scanning lines 85-1 to 85 -m are wired for each row and signal lines 86-1 to 86 -n are wired for each column in the matrix-like arrangement of the pixels 90. The pixel 90 includes a TFT (Thin Film Transistor) 91 which is a pixel transistor, a liquid crystal cell 92 having a pixel electrode connected to the drain electrode of the TFT 91, and a storage capacitor having one electrode connected to the drain electrode of the TFT 91. 93.

  In this pixel structure, the TFT 91 of each pixel 90 has its gate electrode connected to the scanning line 85 (85-1 to 85-m) and its source electrode connected to the signal line 86 (86-1 to 86-n). Has been. The counter electrode of the liquid crystal cell 92 and the other electrode of the storage capacitor 93 are connected to a common line 87 to which a common voltage VCOM is applied.

  The vertical driver 82 includes a shift register circuit and the like, and selects each pixel 90 of the pixel array unit 81 in units of rows. The horizontal driver 83 includes a shift register circuit, a sampling switch, and the like, and sequentially applies video signals input from the outside of the panel to each pixel 90 in the row selected by the vertical driver 82 in units of pixels (dot sequential). Or, write in units of lines all at once (line sequential).

  In the active matrix liquid crystal display device 80 configured as described above, the shift register circuits 10 and 60 according to the first and second history modes described above are used as the shift register circuit constituting at least one of the vertical driver 82 and the horizontal driver 83. .

  As described above, by using the shift register circuits 10 and 60 as the shift register circuits constituting the vertical driver 82 and the horizontal driver 83, the shift register circuits 10 and 60 have a leakage current as each shift register unit (transfer stage). And the shift circuits 11-1, 11-2,... / 61-1, 61-2,... Including the level shift units 20 and 50 with low current consumption are used. Therefore, the power consumption of the liquid crystal display device 80 can be reduced.

  In the application example described above, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as an electro-optical element of the pixel has been described as an example. For example, an EL display device using an EL (electro luminescence) element as an optical element, such as a vertical driver or a horizontal driver configured using a shift register circuit on the same substrate as the pixel array unit, Furthermore, the present invention is applicable to all devices equipped with a scanner configured using a shift register circuit.

  A display device typified by the liquid crystal display device according to the application example described above can be mounted and used as a screen display unit of a mobile device such as a mobile phone, a PDA (Personal Digital Assistants), and a notebook PC (Personal Computer).

1 is a block diagram showing a configuration of a shift register circuit according to a first embodiment of the present invention. 3 is a timing chart for explaining the operation of the shift register circuit according to the first embodiment. It is a block diagram which shows an example of a structure of the 1st, 2nd shift circuit in 1st Embodiment. It is a circuit diagram which shows an example of a structure of a level shift part (LS1). It is a timing chart with which it uses for description of the circuit operation | movement of a level shift part (LS1). It is a block diagram which shows an example of a structure of the control pulse generation part in 1st Embodiment. It is a timing chart with which it uses for description of the circuit operation | movement of the control pulse generation part in 1st Embodiment. It is a block diagram which shows an example of a structure of the 3rd and 4th shift circuit in 1st Embodiment. It is a circuit diagram which shows an example of a structure of a level shift part (LS2). It is a timing chart with which it uses for description of the circuit operation | movement of a level shift part (LS2). is there. It is a block diagram which shows the structure of the shift register circuit which concerns on 2nd Embodiment of this invention. 6 is a timing chart for explaining the operation of the shift register circuit according to the second embodiment. It is a block diagram which shows an example of a structure of the 1st, 2nd shift circuit in 2nd Embodiment. It is a block diagram which shows an example of a structure of the control pulse generation part in 2nd Embodiment. It is a timing chart with which it uses for description of the circuit operation | movement of the control pulse generation part in 2nd Embodiment. It is a block diagram which shows an example of a structure of the 3rd and 4th shift circuit in 2nd Embodiment. It is a circuit diagram which shows an example of a structure of 3 input AND circuit. It is a circuit diagram which shows an example of a structure of an inverter circuit. It is a circuit diagram which shows an example of a structure of 2 input NOR circuit. It is a circuit diagram which shows an example of a structure of 3 input NOR circuit. It is a circuit diagram which shows an example of a structure of 2 input NAND circuit. It is a block diagram which shows an example of a structure of the active matrix type liquid crystal display device which concerns on the example of application of this invention. It is a circuit diagram which shows the prior art example of the shift circuit with a level shift function.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,60 ... Shift register circuit, 11-1 to 11-7, 61-1 to 61-7 ... Shift circuit (shift register unit), 12-1 to 12-7 ... Three-input AND circuit, 20, 50 ... Level Shift unit, 40, 70 ... control pulse generation unit, 21 ... complementary circuit, 22 to 26, 42, 72 ... switch circuit, 41 ... NOR circuit, 44, 74 ... reset circuit, 71 ... NAND circuit

Claims (14)

When the input control pulse is in an active state and the first clock pulse having the first amplitude is at a low level, a first transfer pulse having a second amplitude larger than the first amplitude is output. A first shift circuit;
When the first transfer pulse is in the active state, and the second of said first of said first amplitude phase-shifted by 1/4 period with respect to the clock pulses with the same frequency a and the first clock pulse a second shift circuit for outputting a second transfer pulse of the second amplitude when the clock pulse is at low level,
A third shift circuit said second transfer pulses for outputting a third transfer pulses of said second amplitude when when in the active state, and said first clock pulse is at high level,
When the third transfer pulse is active, and a fourth shift circuit said second clock pulse to output a fourth transfer pulse of the second amplitude at a high level,
The first shift circuit and the second shift circuit are connected in cascade to form a first shift circuit pair, and the third shift circuit and the fourth shift circuit are connected in cascade to form a second shift circuit. A circuit pair, wherein the first shift circuit pair and the second shift circuit pair are alternately connected in cascade,
The first, second, third, and fourth shift circuits include first and second transistors of opposite conductivity type connected in series between a first power supply potential and a second power supply potential. comprising complementarity includes a circuit, given the first of said amplitude to a gate of the first transistor when the level shift driving to the second amplitude first clock pulse or said second clock pulse, the A shift register circuit that applies a clock pulse obtained by relatively shifting the first clock pulse or the second clock pulse to the first power supply potential side to a gate of a second transistor. The first and second shift circuits are
First and second transistors of opposite conductivity type connected in series between a first power supply potential and a second power supply potential;
A first clock terminal to which the first and second clock pulses are input;
A first switch means connected between the first clock terminal and the gate of the first transistor and turned on when the control pulse and the first transfer pulse are in an active state;
A second switch means connected between the second power supply potential and the gate of the second transistor and turned off when the control pulse and the first transfer pulse are in an active state;
A third switch means connected between the second power supply potential and the gate of the first transistor and turned off when the control pulse and the first transfer pulse are in an active state;
The shift register circuit according to claim 1, further comprising: a first capacitor connected between the first clock terminal and a gate of the second transistor. The first and second shift circuits are
The first clock terminal and the first capacitive element are connected between the first clock terminal and the first capacitive element, and the control pulse and the first transfer pulse are in an inactive state. a fourth switch means for interrupting the electrical connection between,
The control pulses, according to claim 2, further comprising a means wherein the first transfer pulse to be fixed to a constant potential the potential of the connection node between said fourth switch means and said first capacitive element when inactive The shift register circuit described. The third and fourth shift circuits are
Third and fourth transistors of opposite conductivity type connected in series between the first power supply potential and the second power supply potential;
A second clock terminal to which the first and second clock pulses are input;
Fifth switch means connected between the second clock terminal and the gate of the third transistor, and turned on when the second and third transfer pulses are in an active state;
The second and third transfers are connected between a third power supply potential lower than the second power supply potential by the amplitude voltage of the first and second clock pulses and the gate of the fourth transistor. Sixth switch means which is turned off when the pulse is in an active state;
A seventh switch means connected between the first power supply potential and the gate of the first transistor, and turned off when the second and third transfer pulses are in an active state;
The shift register circuit according to claim 1, further comprising: a second capacitor element connected between the second clock terminal and a gate of the fourth transistor. The third and fourth shift circuits are
The second clock terminal and the second capacitive element are connected between the second clock terminal and the second capacitive element, and when the second and third transfer pulses are in an inactive state. An eighth switch means for interrupting the electrical connection between ;
The second, according to claim 4, wherein the third transfer pulses further comprises a means for fixing at a constant potential the potential of the connection node between the eighth switching means and said second capacitive element when inactive Shift register circuit. 2. The shift register circuit according to claim 1, wherein each of the first and second shift circuits generates the first and second transfer pulses based on an input and an output of its own stage. 2. The shift register circuit according to claim 1, wherein each of the third and fourth shift circuits generates the third and fourth transfer pulses based on an input and an output of its own stage. A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix, a vertical driving unit that selects each pixel of the pixel array unit in units of rows, and an image in a row selected by the vertical driving unit A display device comprising a horizontal drive means for writing signals, wherein at least one of the vertical drive means and the horizontal drive means is constituted by a shift register circuit,
The shift register circuit includes:
When the input control pulse is in an active state and the first clock pulse having the first amplitude is at a low level, a first transfer pulse having a second amplitude larger than the first amplitude is output. A first shift circuit;
When the first transfer pulse is in the active state, and the second of said first of said first amplitude phase-shifted by 1/4 period with respect to the clock pulses with the same frequency a and the first clock pulse a second shift circuit for outputting a second transfer pulse of the second amplitude when the clock pulse is at low level,
A third shift circuit said second transfer pulses for outputting a third transfer pulses of said second amplitude when when in the active state, and said first clock pulse is at high level,
When the third transfer pulse is active, and a fourth shift circuit said second clock pulse to output a fourth transfer pulse of the second amplitude at a high level,
The first shift circuit and the second shift circuit are connected in cascade to form a first shift circuit pair, and the third shift circuit and the fourth shift circuit are connected in cascade to form a second shift circuit. A circuit pair, wherein the first shift circuit pair and the second shift circuit pair are alternately connected in cascade,
The first, second, third, and fourth shift circuits include first and second transistors of opposite conductivity type connected in series between a first power supply potential and a second power supply potential. comprising complementarity includes a circuit, given the first of said amplitude to a gate of the first transistor when the level shift driving to the second amplitude first clock pulse or said second clock pulse, the The display device, wherein a clock pulse obtained by relatively shifting the first clock pulse or the second clock pulse to the first power supply potential side is applied to a gate of a second transistor. The first and second shift circuits are
First and second transistors of opposite conductivity type connected in series between a first power supply potential and a second power supply potential;
A first clock terminal to which the first and second clock pulses are input;
A first switch means connected between the first clock terminal and the gate of the first transistor and turned on when the control pulse and the first transfer pulse are in an active state;
A second switch means connected between the second power supply potential and the gate of the second transistor and turned off when the control pulse and the first transfer pulse are in an active state;
A third switch means connected between the second power supply potential and the gate of the first transistor and turned off when the control pulse and the first transfer pulse are in an active state;
The display device according to claim 8 , further comprising a first capacitor connected between the first clock terminal and a gate of the second transistor. The first and second shift circuits are
The first clock terminal and the first capacitive element are connected between the first clock terminal and the first capacitive element, and the control pulse and the first transfer pulse are in an inactive state. a fourth switch means for interrupting the electrical connection between,
Said control pulse, the first claim transfer pulse further has a means for fixing at a constant potential the potential of the connection node between said fourth switch means and said first capacitive element when inactive 9 The display device described. The third and fourth shift circuits are
Third and fourth transistors of opposite conductivity type connected in series between the first power supply potential and the second power supply potential;
A second clock terminal to which the first and second clock pulses are input;
Fifth switch means connected between the second clock terminal and the gate of the third transistor, and turned on when the second and third transfer pulses are in an active state;
The second and third transfers are connected between a third power supply potential lower than the second power supply potential by the amplitude voltage of the first and second clock pulses and the gate of the fourth transistor. Sixth switch means which is turned off when the pulse is in an active state;
A seventh switch means connected between the first power supply potential and the gate of the first transistor, and turned off when the second and third transfer pulses are in an active state;
The display device according to claim 8 , further comprising: a second capacitor element connected between the second clock terminal and a gate of the fourth transistor. The third and fourth shift circuits are
The second clock terminal and the second capacitive element are connected between the second clock terminal and the second capacitive element, and when the second and third transfer pulses are in an inactive state. An eighth switch means for interrupting the electrical connection between ;
The second, third claim 11, wherein a transfer pulse further has a means for fixing at a constant potential the potential of the connection node between the eighth switching means and said second capacitive element when inactive Display device. The display device according to claim 8 , wherein each of the first and second shift circuits generates the first and second transfer pulses based on an input and an output of its own stage. The display device according to claim 8 , wherein each of the third and fourth shift circuits generates the third and fourth transfer pulses based on an input and an output of its own stage.

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