JP4608982B2 - Pulse signal generation method, shift circuit, and display device - Google Patents

Description

  The present invention relates to a method for generating a pulse signal, and a shift circuit and a display device using the method.

  When driving a display device such as a liquid crystal display device, a display drive circuit corresponding to the response speed of the device is used.

  For example, in a liquid crystal display driving circuit, an image signal sent every moment is not directly applied to each pixel, but an image signal voltage sampled corresponding to each pixel within one horizontal scanning period is displayed during the horizontal scanning period. Held at the beginning of the next horizontal scanning period or at an appropriate time in the middle of the next horizontal scanning period. When the output of the image signal voltage to each pixel is started, the output voltage (image signal voltage) is held for a time sufficiently exceeding the response time of the liquid crystal.

  For this purpose, a shift circuit that sequentially transfers pulse signals, a latch circuit that holds pulse signals for a certain period, a delay circuit that delays pulse signals as necessary, and the like are used (for example, Patent Documents 1 to 3). reference).

Japanese Patent Laid-Open No. 5-122021 Japanese Unexamined Patent Publication No. 7-13527 Japanese Patent Laid-Open No. 2002-164771

  FIG. 14 is a diagram illustrating a configuration example of a liquid crystal display device in which a conventional shift register circuit is applied to a drive circuit. As illustrated, the liquid crystal display device 1 includes a pixel display unit 10, a vertical drive circuit (V driver) 20, and a horizontal drive circuit (H driver) 30.

  The vertical drive circuit 20 includes a level shifter (L / S) 22, a shift register (S / R) 24, and a buffer 26. The horizontal drive circuit 30 includes a shift register (S / R) 33, a buffer 36, and a horizontal direction control switch (Hsw) 38.

  As can be seen, the conventional liquid crystal display device 1 uses a shift register circuit for both the vertical drive circuit 20 and the horizontal drive circuit 30. However, a horizontal shift register 33 having a level shift function is used.

  The liquid crystal display device 1 is supplied with a reset pulse rst, a clock pulse CK, and an enable pulse ENB as external input pulses for each of the vertical system and the horizontal system. Reference numerals H and V are attached before each signal. The liquid crystal display device 1 generates a reverse phase signal xCK of the clock pulse CK by a circuit in the panel.

  15 to 18 are diagrams illustrating a conventional shift register 24. FIG. 15 is a basic circuit diagram. Here, four stages of basic shift registers 42 of the shift register 24 constituting the vertical drive circuit 20 (reference numerals -1, -2, -3,- 4) The input pulse of xCK is generated by a circuit in the liquid crystal display device (panel).

  As shown in FIG. 15, the basic shift register 42 includes terminals CKin, xCKin, ENB, IN, OUT, and next, and requires three external input pulses CK, ENB, and ST.

  The enable pulse ENB is used to remove the overlap of the transfer pulse. In order to remove this overlap, a NAND circuit is used.

  Further, as the basic shift register 42 for the vertical drive circuit 20, two types of vsr1 and vsr2 are required due to the relationship of the external input pulse at the time of upside down.

  FIG. 16 shows a detailed configuration of the first basic shift register 42 (vsr1), and FIG. 17 shows a detailed configuration of the second basic shift register 42 (vsr2). The operation of the first and second basic shift registers is represented by the timing chart shown in FIG.

  Each of them includes a shift register circuit (S / R), a reset circuit (rst), an output circuit, and a NAND circuit.

  As shown in FIG. 16, the first basic shift register 42 (vsr1) requires eight Nch MOS transistors and nine Pch MOS transistors. As shown in FIG. 17, the second basic shift register 42 (vsr2) requires 12 Nch MOS transistors and 11 Pch MOS transistors.

  Further, as can be seen from the figure, each of them has Nch transistors n6, n7, and n8 and Pch transistors p6, p7, and p8, and is controlled by an enable pulse ENB in order to remove the overlap of the transfer pulse. NAND circuit is provided.

  As described above, the vertical driving circuit of the conventional liquid crystal display device includes a level shifter, a shift register, a gate buffer, and the like, and the horizontal driving circuit includes a horizontal direction control switch, a buffer, a shift register with a level shift function, and the like. There has been a limit to reducing the circuit layout area, which has hindered the narrowing of the panel frame. In particular, many elements are required for the configuration for removing the overlap of the transfer pulse.

  The present invention has been made in view of the above circumstances, and provides a mechanism capable of narrowing the frame by proposing a basic shift register capable of reducing the number of transistors used in a circuit compared to a current circuit. The purpose is to do.

  A pulse signal generation method according to the present invention is a method for generating a drive clock corresponding to an input pulse signal, and a part of a clock pulse for driving a shift circuit for generating a drive clock is transmitted during an active period of the drive clock. It was decided to use it as a signal.

  A shift circuit according to the present invention is a shift circuit using the pulse signal generation method according to the present invention, wherein a part of a clock pulse for driving the shift circuit is used as a signal of an active period of the drive clock. did.

  For example, by using an input pulse signal and a first clock pulse and a second clock pulse having different phases, a part of either the first clock pulse or the second clock pulse is used as the drive clock. Used as an active period signal.

  In addition, a transfer gate circuit that controls input / output of an input pulse signal, a latch circuit that holds a pulse signal input via the transfer gate circuit for a certain period, and a pulse signal output from the latch circuit is output as a drive clock. The output circuit is formed by using complementary circuit technology, and the first clock pulse having a phase different from that of the clock pulse for driving the output circuit is input to the input side of the transfer gate circuit, so that the active period of the drive clock It is advisable to generate the signal.

  In this case, the output circuit is provided with a transfer gate circuit for controlling input / output of the input pulse signal, and the second clock pulse for driving the output circuit is input to the input side of the transfer gate circuit, so that the drive clock It is preferable to generate a signal during the active period.

  In this case, the output side of the output circuit may be held at a predetermined potential to generate a signal during an inactive period of the drive clock.

  When such shift circuits are connected in cascade, the pulse signal output from the latch circuit is output directly or via a predetermined number of buffers as an input pulse signal for the next stage. It is good to do so.

  In addition, a delay circuit that delays the pulse signal output from the latch circuit by a predetermined time is provided between the latch circuit and the output circuit, so that the time margin for transfer and output is shifted backward. . This facilitates application as a shift circuit for a circuit that operates at a relatively high speed, such as a horizontal drive circuit.

  Such a shift circuit is not limited to the one for driving pulses, and is used only when the clock circuits corresponding to the input pulse signals are sequentially output to the subsequent stage by cascading the shift circuits. May be. In this case, a transfer gate circuit that controls input / output of the input pulse signal and a latch circuit that holds a pulse signal input via the transfer gate circuit for a certain period may be formed using complementary circuit technology. .

  The display device according to the present invention is a display device using the pulse signal generation method according to the present invention, and includes a shift circuit that outputs a drive clock corresponding to an input pulse signal to the drive circuit. A part of the clock pulse for driving the shift circuit is used as a signal for the active period of the drive clock.

  Note that various modified configurations of the above-described shift circuit according to the present invention can be similarly applied to the shift circuit included in the display device.

  According to the present invention, a part of the clock pulse for driving the shift circuit that generates the drive clock is used as a signal of the active period of the drive clock. For this reason, the number of transistor elements constituting the shift circuit can be reduced as compared with the conventional configuration. As a result, when the shift circuit is applied to a display device, the area of the drive circuit occupying the panel can be reduced, and as a result, the frame can be narrowed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<< Overview of Liquid Crystal Display >>
FIG. 1 is a diagram showing an outline of an embodiment of a liquid crystal display device in which an embodiment of a shift register circuit according to the present invention is applied to a drive circuit.

  As illustrated, the liquid crystal display device 1 includes a pixel display unit 10, a vertical drive circuit (V driver) 20, and a horizontal drive circuit (H driver) 30.

  The vertical drive circuit 20 includes a level shifter (L / S) 22, a shift register (S / R) 24, and a buffer 26. The horizontal drive circuit 30 includes a level shifter (L / S) 32, a shift register (S / R) 34, a buffer 36, and a horizontal direction control switch (Hsw) 38. All circuits are composed of CMOS (Complementary Metal-Oxide Semiconductor) on an insulating substrate such as a glass substrate by using complementary circuit technology. Each transistor constituting the CMOS has a TFT (Thin Film Transistor) element structure.

  As can be seen, the liquid crystal display device 1 can use the novel shift register circuit according to the present invention for both the vertical drive circuit 20 and the horizontal drive circuit 30. Details of the novel shift register circuit according to the present invention will be described later. Unlike the conventional liquid crystal display device 1, the horizontal system is characterized in that a level shifter 32 and a shift register 34 are used instead of the shift register 33 with a level shift function.

  The liquid crystal display device 1 receives a start pulse ST, a first clock pulse CK1, and a second clock pulse CK2 as external input pulses for each of a vertical system and a horizontal system. Reference numerals H and V are attached before each signal.

  The liquid crystal display device 1 generates reverse-phase clock pulses xCK1 and xCK2 of the clock pulses CK1 and CK2 by a circuit in the panel.

  Both the first clock pulse CK1 and the second clock pulse CK2 use pulses having a duty of 50% or less, for example, the high period is about 1/3 of the entire period. Further, the first clock pulse CK1 and the second clock pulse CK2 are used so that their phases are shifted so that one high period falls within the other low period (details will be described later).

<< Configuration Example of Shift Register; First Embodiment >>
FIG. 2 is a circuit block diagram showing a first embodiment of the shift register circuit 40 (shift register 24, shift register 34) according to the present invention. In the illustrated example, the basic elements of the shift register (hereinafter also referred to as the basic shift register 42) are shown for four stages (respectively indicated by reference numerals -1, -2, -3, and -4).

As shown in FIG. 2, each basic shift register 42 has, on the input side, a shift pulse input terminal IN that takes in the output signal next from the previous stage, and three clock input terminals CKinA, xCKinA, and CKinB. The start pulse ST is input as the input pulse i1 to the input terminal IN at the first stage.

  The shift register circuit 40 alternately inputs two clock pulses CK1 and CK2 to the clock input terminals CKinA and CKinB of each basic shift register 42 with respect to the basic shift registers 42 connected in multiple stages.

  The clock pulses CK1 and CK2 are alternately selected and output as shift pulses OUT (respectively denoted by reference numerals 1, 2, 3, and 4). For example, when next = CK2 = High, OUT1 = High.

  FIG. 3 is a timing chart for explaining the operation of the shift register circuit 40 shown in FIG. For reference, the shift register circuit 40 shown in FIG. 2 is also shown.

  As shown in the figure, the shift pulses are output to the output terminal OUT of the basic shift register 42 at each stage based on the clock pulses CK1 and CK2 and the output signal next from the previous stage at appropriate time intervals.

  When the clock pulse CK2 = High and next1 = High, High, that is, a shift pulse is output to the output terminal OUT1 of the first-stage basic shift register 42-1.

  Next, when the clock pulse CK1 = High and next2 = High, a High shift pulse is output to the output terminal OUT2 of the second-stage basic shift register 42-2.

  Similarly, when the clock pulse CK2 = High and next3 = High, a High shift pulse is output to the output terminal OUT3 of the third-stage basic shift register 42-3, and the clock pulses CK1 = High and next4 = High. At this time, a high shift pulse is output to the output terminal OUT4 of the fourth-stage basic shift register 42-4.

<Detailed Circuit Diagram of Basic Shift Register of First Embodiment; First Example>
FIG. 4 is a circuit diagram (FIG. 4A) of the first example showing details of the basic shift register 42 used in the shift register circuit 40 of the first embodiment, and a timing chart (FIG. B)).

  As shown in FIG. 4A, the basic shift register 42 includes a transfer gate circuit 50, a latch circuit 60, an output circuit 70, and other peripheral elements. An output buffer circuit 80 is also provided for the output signal next to the shift pulse input terminal IN at the subsequent stage.

  All circuit elements are constructed using CMOS technology. Also, the purpose is to reduce the number of elements and the circuit area, and the input clock pulses CK1 and CK2 are level-shifted in advance to the power supply voltage so that the clock pulses CK1 and CK2 themselves can be used as shift pulses. deep. Using the blanking period of the first and second clock pulses CK1 and CK2 for driving the shift register circuit 40 having different phases, a part of these clock pulses is transferred to the next transfer clock or the pulse signal for driving. By controlling the circuit so that it is used as a signal during the active period of (gate pulse), the number of NAND circuits for removing the overlap of the transfer pulse is reduced. This will be specifically described below.

  As shown in FIG. 4B, as the first clock pulse CK1 and the second clock pulse CK2, for example, a pulse having a high period of about 1/3 of the total period and having a duty of 50% or less is used. The one whose phase is shifted so that the period falls within the other low period is used. At this time, a predetermined margin period is provided between the falling edge (t16) of the clock pulse CK2 and the rising edge (t20) of the clock pulse CK1.

  By doing so, the conventional circuit eliminates the need for a NAND circuit that operates based on the enable pulse ENB in order to eliminate the overlap of the transfer pulse. Such a configuration is highly effective in reducing the number of elements of the basic shift register 42.

  The basic shift register 42 shown in FIG. 4A is shown as corresponding to the odd (1, 3,...) Stage of the shift register circuit 40 shown in FIG. 2, and the clock input terminal of the transfer gate circuit 50 is shown. The clock pulse CK1 is input to CKinA, the opposite phase clock pulse xCK1 is input to the clock input terminal xCKinA, and the clock pulse CK2 is input to the clock input terminal CKinB of the output circuit 70.

  In order to correspond to the even (2, 4,...) Stage of the shift register circuit 40 shown in FIG. 2, the clock pulse CK2 is input to the clock input terminal CKinA of the transfer gate circuit 50, and the clock input terminal xCKinA is input to the clock input terminal xCKinA. The opposite phase clock pulse xCK2 is input, and the clock pulse CK1 may be input to the clock input terminal CKinB of the output circuit 70.

  The transfer gate circuit 50 includes a CMOS switch including an Nch (ch) channel n1 and a Pch transistor p1. The gate (control input terminal) of the transistor n1 corresponds to the clock input terminal CKinA, and the gate of the transistor p1 corresponds to the clock input terminal xCKinA. The transfer pulse next from the previous stage is given as the input pulse IN to the input of the CMOS switch composed of the transistors n1 and p1.

  The CMOS switch composed of the transistors n1 and p1 is turned on when CKinA = High and xCKinA = Low, thereby capturing the state of the input pulse IN in the latch circuit 60. This CMOS switch may be a switch composed of only one of the transistors n1 and p1, or an Nch MOS transistor or a Pch MOS transistor. In this case, however, there is a problem of the threshold voltage Vth. A CMOS switch using both p1 was adopted.

  The output terminal (hereinafter referred to as gate output point) A of the transfer gate circuit 50 is connected to the drain of an Nch transistor n6 as a reset switch. The source of the transistor n6 is connected to the reference power supply VSS, and the reset pulse rst is input to the gate. The reset pulse rst is set to Low during normal driving.

  The latch circuit 60 includes Nch transistors n2 and n3 and Pch transistors p2 and p3. The connection configuration of the transistors p2 and n2 and the connection configuration of the transistors p3 and n3 are symmetric. Specifically, the sources of the transistors p2 and p3 are connected to the power supply VDD, and the sources of the transistors n2 and n3 are connected to the reference power supply VSS.

  The transistor p2 and the transistor n2 form a first CMOS inverter by connecting the gates and drains to each other, and the transistor p3 and the transistor n3 have gates and drains connected to each other. Thus, the second CMOS inverter is configured.

  The input terminal of the first CMOS inverter, that is, the gates of the transistors p2 and n2, and the output terminal of the second CMOS inverter, that is, the drains of the transistors p3 and n3 are connected. It is connected to the gate output point A. The input terminal of the second CMOS inverter, that is, the gates of the transistors p3 and n3, and the output terminal of the first CMOS inverter, that is, the drains of the transistors p2 and n2, are connected. The negative phase output terminal (hereinafter referred to as latch negative phase output point) B.

  The connection point of the latch circuit 60 with the gate output point A also functions as a positive phase output terminal C (hereinafter referred to as a latch positive phase output point) C of the latch circuit 60.

  The latch circuit 60 having such a configuration is configured to apply positive feedback. When the transfer gate circuit 50 is turned on, the state of the input pulse IN is applied to the gates of the transistors p2 and n2 on the input side of the latch circuit 60. When the transfer gate circuit 50 is turned off, the state of the input pulse IN at that time is maintained even if the transfer gate circuit 50 is turned off. That is, a latch operation is performed.

  Further, by providing the transfer gate circuit 50 on the input side of the latch circuit 60, the influence on the input side can be almost completely cut off during the period in which the latch circuit 60 holds the pulse signal, and the voltage holding performance is improved. it can.

  Since the transfer gate circuit 50 is turned on when the clock input terminal CKinA / xCKinA is High / Low, if the state of the input pulse IN does not change during the period when the clock input terminal CKinA / xCKinA is High / Low, the result is as follows. The state of the input pulse IN is taken in synchronization with the rising edge / falling edge of the clock input terminal CKinA / xCKinA, the same polarity state as the input pulse IN is at the latch normal phase output point C, and the opposite polarity. The state is held at the latch reverse phase output point B.

  The output circuit 70 includes a CMOS switch including an Nch transistor n4 and a Pch transistor p4, and an Nch transistor n5. In the CMOS switch composed of the transistors n4 and p4, the clock pulse CK2 is input to the input side, and the output side is used as the output terminal OUT of the basic shift register 42.

  The transistor n5 has a gate connected to the gate of the transistor p4, that is, the latch antiphase output point B, a source connected to the reference power supply VSS, and a drain connected to the output of the CMOS switch. The transistor n5 functions as a switching circuit that generates a signal in an inactive period of the drive clock output from the output circuit 70 by holding the output side of the output circuit 70 at a predetermined potential.

The CMOS switch including the transistors n4 and p4 functions as a transfer gate circuit. In this CMOS switch, the clock pulse CK2 is input to the input side, and the clock pulse CK2 is output to the output terminal OUT under the output state of the latch circuit 60. Specifically, when the gate output point A = High, that is, the latch positive phase output point C = High and the latch negative phase output point B = Low, the state of the clock pulse CK2 is output to the output terminal OUT.

  That is, the latch anti-phase output point B is turned on while the latch anti-phase output point B is Low, and the state of the clock pulse CK2 is output to the output terminal OUT. n5 is turned on, and the output terminal OUT is fixed to Low which is an inactive state.

  Note that the CMOS switch may be a switch composed of only one of the transistors n4 and p4, which is an Nch type MOS transistor or a Pch type MOS transistor. In this case, however, there is a problem of the threshold voltage Vth. , P4 CMOS switch is used.

  The output buffer circuit 80 has inverters 82 and 84 of even stages (two stages in the figure), and outputs the state of the gate output point A, that is, the latch positive phase output point C, to the next stage as the transfer pulse next. ing. The reason why the inverters are even stages is that the state of the latch positive phase output point C is used for the transfer pulse next to the basic shift register 42 of the next stage.

  The output buffer circuit 80 is not an essential component for the basic shift register 42 in the first embodiment, but is removed to reduce the number of elements, and the state of the latch positive phase output point C is directly transferred to the transfer pulse next. May be output to the next stage.

  In addition, the state of the latch antiphase output point B can be used as a transfer pulse next for the basic shift register 42 in the next stage. In this case, the inverter before the next terminal may be set to an odd number. (See FIG. 6 described later).

  According to the basic shift register 42 of the first example of the first embodiment, as will be described later (see FIG. 13), the number of transistors can be greatly reduced as compared with the conventional shift register 24 shown in FIG. A narrow frame is possible.

  As shown in FIG. 4B, the basic shift register 42 having the configuration of the first example has the transfer gate circuit 50 when the clock pulse CK1 is High and the input pulse IN from the previous stage is High. The potential of the gate output point A becomes High, and when the next clock pulse CK1 is High and the input pulse IN from the previous stage becomes Low, the potential of the gate output point A becomes Low.

  That is, the potential at the gate output point A is given in the form that the input pulse IN from the previous stage is shifted in time. When the latch at the gate output point A is latched by the latch circuit 60, the potential at the latch reverse-phase output point B of the latch circuit 60 becomes a reverse-phase pulse waveform at the same timing as the gate output point A.

  Pulses at both gate output points A and B are applied to corresponding gates of the CMOS switch of the output circuit 70. Specifically, the gate output point A is connected to the gate of the Nch transistor n4, and the latch reverse phase output point B is connected to the gate of the Pch transistor p4.

  Therefore, when the gate output point A is Low, that is, when the latch reversed-phase output point B is High, the transistor n5 of the output circuit 70 is turned on, so that the reference voltage Vss is output to the output terminal OUT. When the gate output point A is High, the transistors n4 and p4 are turned on, the transistor n5 is turned off, and one clock pulse CK2 is output to the output terminal OUT.

  As can be understood from the above description of the configuration and operation, the basic shift register 42 shown in FIG. 4 has the following characteristic points. That is, first, by the transfer gate circuit 50 configured as a switch with CMOS transistors p1 and n1, the A and B potentials that give the ON period of the CMOS switch configured with the transistors p4 and n4 of the output circuit 70, that is, the latch circuit 60 The potentials of the latch negative phase output point B and the latch positive phase output point C are controlled.

The latch circuit 60 latches the output of the transfer gate circuit 50 and holds the state, and determines the A and B potentials, that is , the potentials of the latch negative phase output point B and the latch positive phase output point C. Then, the output of the latch circuit 60 is used to open and close the CMOS switch constituted by the transistors p4 and n4 of the output circuit 70, thereby outputting the clock pulse CK2 to the output terminal OUT.

  The A potential, that is, the potential at the latch positive phase output point C is also used for the transfer pulse next to the basic shift register 42 in the next stage. In this case, the inverter buffer before the next is set to an even number of stages.

  Further, as shown by a thick solid line in FIG. 4B, only one pulse of the clock pulse CK2 is selected and output by the CMOS switch including the transistors n4 and p4 of the output circuit 70 as shown by a thick solid line. To do. The selected pulse is used as a gate waveform for the buffer 26 of the vertical drive circuit 20 and the buffer 36 of the horizontal drive circuit 30 in the liquid crystal display device 1.

<Detailed Circuit Diagram of Basic Shift Register of First Embodiment; Second Example>
FIG. 5 is a circuit diagram (FIG. 5A) of a second example showing details of the basic shift register 42 used in the shift register circuit 40 of the first embodiment, and a timing chart (FIG. B)).

  This second example is characterized by the configuration of the latch circuit 60A. That is, in the latch circuit 60A according to the present example, the gates of the transistors p2 and n2 (gate output point A of the transfer gate circuit 50) constituting the first CMOS inverter and the transistors p3 and p3 constituting the second CMOS inverter. The switch circuit SW is connected between the n3 drain (latch positive phase output point C).

  The switch circuit SW is configured by a CMOS switch in which an Nch transistor n7 and a Pch transistor p7 are connected in parallel. The clock pulse CK1 is used as the gate input of the transistor p7, and the reverse-phase clock pulse xCK1 is used as the gate input of the transistor n7. Yes.

  Note that the switch circuit SW may be a switch circuit using only one of the transistors n7 and p7, but in this case, there is a problem of the threshold voltage Vth. , A CMOS switch using both n7 and p7 is employed. Hereinafter, the switch circuit SW is referred to as a CMOS switch SW.

  In the case where there is no CMOS switch SW, that is, in the case of the latch circuit 60 of the first example, in the operation in which the potential of the gate output point A of the transfer gate circuit 50 is switched from Low → High (or High → Low), And the output voltage from the second CMOS inverter (p3, n3) collide at the gate output point A.

  At this time, the transistor size is adjusted so that the output voltage of the transfer gate circuit 50 becomes stronger. However, if there are variations in transistor characteristics such as threshold voltage Vth and mobility μ, there is a concern that the balance of each circuit portion is lost and the overall operation becomes unstable.

The it is because in order to solve the problem caused by the variation in the transistor characteristic is latch circuit 60A of the second example. In the latch circuit 60A, when the transfer gate circuit 50 is on, the CMOS switch SW is turned off, so that the input terminal (gates of p2 and n2) of the first CMOS inverter and the output terminal of the second CMOS inverter. The electrical connection to (drains of p3 and n3) is disconnected.

  This prevents the output voltage from the transfer gate circuit 50 and the output voltage from the second CMOS inverter (p3, n3) from colliding at the gate output point A, so that the gate output point of the transfer gate circuit 50 can be prevented. A and the potential of the latch antiphase output point B of the latch circuit 60A can be switched smoothly.

  Further, when the transfer gate circuit 50 is off, the CMOS switch SW is turned on, so that the input terminal (p2, n2 gate) of the first CMOS inverter and the output terminal (p3, n3) of the second CMOS inverter. Between the first and second drains). As a result, the latch circuit 60A operates and can hold the potential. In other words, stable circuit operation can be obtained by eliminating collision of output voltages.

  As described above, in the latch circuit 60A, the CMOS switch SW is connected between the input terminal (gates of p2 and n2) of the first CMOS inverter and the output terminal (drains of p3 and n3) of the second CMOS inverter. Since the CMOS switch SW is turned off when the transfer gate circuit 50 is turned on, a portion where the output voltage from the transfer gate circuit 50 collides with the output voltage from the second CMOS inverter can be eliminated. The stability of the circuit operation can be realized.

  In addition, the wiring between the input end of the first CMOS inverter (gates of p2 and n2) and the output end of the second CMOS inverter (drains of p3 and n3) is electrically separated by the CMOS switch SW. As a result, the capacitance seen from the input IN is reduced, and the load on the input pulse IN can be reduced. Therefore, the reduction in the capacitance also contributes to stable operation.

<Detailed Circuit Diagram of Basic Shift Register of First Embodiment; Third Example>
FIG. 6 is a circuit diagram (FIG. 6 (A)) showing the details of the basic shift register 42 used in the shift register circuit 40 of the first embodiment, and a timing chart (FIG. B)).

  This third example is characterized in that the state of the latch antiphase output point B is used as a transfer pulse next for the basic shift register 42 in the next stage.

  Also in the configuration of the third example, the basic shift register 42 includes a transfer gate circuit 50, a latch circuit 60, an output circuit 70, and other peripheral elements as shown in FIG. Note that the output buffer circuit 80 is also provided for the output signal next to the shift pulse input terminal IN at the subsequent stage, but the inverter before the next terminal is set to an odd number and the signal from the latch reverse-phase output point B is next. It communicates to the stage.

  In the basic shift register 42 of the third example of the first embodiment, the number of transistors can be greatly reduced and the frame can be narrowed as compared with the conventional shift register 24 shown in FIG.

  The operation of the basic shift register 42 having the configuration of the third example is the same as that of the first example since the transfer gate circuit 50, the latch circuit 60, and the output circuit 70 are as shown in FIG. 6B. The same operation as in the first example is performed. That is, first, by the transfer gate circuit 50 configured as a switch with CMOS transistors p1 and n1, the A and B potentials that give the ON period of the CMOS switch configured with the transistors p4 and n4 of the output circuit 70, that is, the latch circuit 60 The potentials of the latch negative phase output point B and the latch positive phase output point C are controlled.

The latch circuit 60 latches the output of the transfer gate circuit 50 and holds the state, and determines the A and B potentials, that is , the potentials of the latch reverse phase output point B and the latch normal phase output point C. Then, the output of the latch circuit 60 is used to open and close the CMOS switch constituted by the transistors p4 and n4 of the output circuit 70, thereby outputting the clock pulse CK2 to the output terminal OUT.

The potential of the latch antiphase output point B is the transfer pulse n to the basic shift register 42 in the next stage.
It is also used for ext. When the B potential is used for the transfer in this way, unlike the first example shown in FIG. 4, the inverter buffer before the next is set to an odd number of stages.

  Further, as shown by a thick solid line in FIG. 6B, only one pulse of the clock pulse CK2 is selected and output by the CMOS switch including the transistors n4 and p4 of the output circuit 70 as shown by a thick solid line. To do. The selected pulse is used as a gate waveform for the buffer 26 of the vertical drive circuit 20 and the buffer 36 of the horizontal drive circuit 30 in the liquid crystal display device 1.

<Delay measures>
Incidentally, in the basic shift register 42 used in the shift register circuit 40 of the first embodiment shown in FIGS. 4, 5, and 6, as shown in the timing chart, only when the potential of the gate output point A is High. A clock pulse is output to the output terminal OUT of the output circuit 70, but a time margin behind the clock pulse becomes a problem.

  FIG. 7 is a timing chart for explaining the problem of the delay margin. In the timing chart shown in FIG. 7, the time margin on the front side is long and the time margin on the rear side is short, as shown in the pulse waveform (A / next) at the gate output point A that is the output to the next stage. For this reason, this margin may be a problem.

  When used for the vertical drive circuit 20, the enable period is long, and thus the short time margin is not so problematic, but when used for the horizontal drive circuit 30, the output terminal OUT of the output circuit 70 is used. The pulse itself is only about 130 ns, for example, and the rear enable period is as short as 20 ns. Therefore, if the frequency is high, for example, there is a clock delay or a pulse delay in the circuit, the time margin on the rear side becomes more severe.

  Accordingly, the basic shift register 42 can be applied to both the vertical drive circuit 20 and the horizontal drive circuit 30, but in particular, when applied to a high-frequency circuit such as the horizontal drive circuit 30, some measure against delay is taken. It is better to use it. Hereinafter, this countermeasure against delay will be described as a second embodiment.

  In the third example, the latch circuit 60A according to the second example can be used instead of the latch circuit 60 according to the first example.

<< Configuration Example of Shift Register; Second Embodiment >>
FIG. 8 is a circuit block diagram showing a second embodiment of the shift register circuit 40 (shift register 24, shift register 34) according to the present invention, and a timing chart for explaining the operation thereof. In the illustrated example, four stages of basic shift registers 42 are shown (respectively denoted by reference numerals -1, -2, -3, and -4).

  As shown in FIG. 8, each basic shift register 40 and its connection relationship are the same as those of the first embodiment shown in FIG. 2, but the operation timing is different from that of the first embodiment shown in FIG. . Specifically, it is characterized in that the margin before the next pulse is shortened by using a delay, the subsequent period is lengthened, and the margins before and after are made equal.

<Detailed Circuit Diagram of Basic Shift Register of Second Embodiment; First Example>
FIG. 9 is a circuit diagram (FIG. 9A) of the first example showing details of the basic shift register 42 used in the shift register circuit 40 of the second embodiment, and a timing chart (FIG. B)). The delay circuit 90 is provided between the latch circuit 60 and the output circuit 70 to solve the problem of the time margin on the rear side shown in FIG. .

  Specifically, as shown in FIG. 9A, an odd number of inverter buffers are provided between the latch circuit 60 and the output circuit 70 so that the front and rear margins are equal (in the figure, inverter buffers 92, A delay circuit 90 having 96 stages is provided.

  The inverter buffer 92 is provided between the latch positive phase output point C on the latch circuit 60 side and the gate connection point B ′ of the transistors p4 and n5. The inverter buffer 96 is provided between the latch reverse phase output point B on the latch circuit 60 side and the gate input point A ′ of the transistor n4.

  The state of the gate input point A ′ is substantially the same as the state of the gate output point A and the latch positive phase output point C. The state of the gate connection point B ′ is substantially the same as the state of the latch reverse phase output point B. Here, “substantially the same” means that the gate delay is ignored.

  Similarly to the first embodiment, the output buffer circuit 80 has even-numbered (two-staged) inverters 82 and 84 and outputs the state of the gate input point A ′ to the next stage as the transfer pulse next. I have to. The reason why the even number of inverters is used is that the state of the latch positive phase output point C is substantially used for the transfer pulse next to the basic shift register 42 of the next stage.

  As in the first embodiment, the output buffer circuit 80 is not an essential component for the basic shift register 42 in the second embodiment, and is removed to reduce the number of elements, and the latch positive-phase output point C This state may be directly output to the next stage as a transfer pulse next.

  The state of the gate connection point B ′ substantially equal to the latch antiphase output point B can also be used as a transfer pulse next for the basic shift register 42 of the next stage. What is necessary is just to make an odd number of inverters in front.

  Further, the inverter buffer 92 and the inverter buffer 94 in the delay circuit 90 are connected in an even number of stages, and the state on the output side of the inverter buffer substantially equal to the gate output point A is set to the basic shift register 42 of the next stage. Can also be used as a transfer pulse next (see FIG. 10 described later).

  In the basic shift register 42 of the first example of the second embodiment, the number of transistors can be reduced and the frame can be narrowed as compared with the conventional shift register 24 shown in FIG.

  Further, according to the basic shift register 42 of the first example of the second embodiment, the timing is slightly delayed by inserting the delay circuit 90 before entering the CMOS switch (p4 / n4) of the output circuit 70. Can do.

  For example, as shown in FIG. 9B, the reverse-phase pulse at the gate connection point B ′ also has the same timing as the gate input point A ′. In the pulse at the gate input point A ′ and the gate connection point B ′, the time margin on the front side is reduced, but the time margin on the rear side is increased by that amount, and a substantially uniform margin can be provided before and after. As a result, when applied to the horizontal drive circuit 30, unlike the first embodiment, the frequency is fast, for example, even when there is a clock delay or a pulse delay in the circuit, the time margin on the rear side thereof is reduced. Can afford. The basic shift register 42 of the second embodiment can be applied to the horizontal drive circuit 30 without any inconvenience.

  As the operation of the basic shift register 42 having the configuration of the first example of the second embodiment, the transfer gate circuit 50, the latch circuit 60, and the output circuit 70 are the same as those in the first embodiment. As shown in B), the same operation as the first embodiment is performed except for the time margin.

  That is, first, the A ′ and B ′ potentials that give the on-period of the CMOS switch constituted by the transistors p4 and n4 of the output circuit 70 by the transfer gate circuit 50 constituted as a switch by the CMOS transistors p1 and n1, that is, a latch circuit 60 potentials of the latch negative phase output point B and the latch positive phase output point C are controlled.

The latch circuit 60 latches the output of the transfer gate circuit 50 and holds the state, and determines the A and B potentials, that is , the potentials of the latch negative phase output point B and the latch positive phase output point C. Then, the output of the latch circuit 60 is used to open and close the CMOS switch constituted by the transistors p4 and n4 of the output circuit 70, thereby outputting the clock pulse CK2 to the output terminal OUT.

  The potential at the gate input point A ′ is also used for the transfer pulse next to the basic shift register 42 in the next stage. In this way, when the potential at the gate input point A ′ is used for transfer, the inverter buffer before the next is set to an even number stage. Note that the potential at the gate connection point B ′ can be used for the transfer pulse next to the basic shift register 42 in the next stage, but in this case, the inverter buffer before next is set to an odd number.

  Further, as shown by a thick solid line in FIG. 6B, only one pulse of the clock pulse CK2 is selected and output by the CMOS switch including the transistors n4 and p4 of the output circuit 70 as shown by a thick solid line. To do. The selected pulse is used as a gate waveform for the buffer 26 of the vertical drive circuit 20 and the buffer 36 of the horizontal drive circuit 30 in the liquid crystal display device 1.

  Here, in the second embodiment, the delay circuit 90 is used to increase the time margin after the next pulse with respect to the clock. Depending on the buffer capability of the delay circuit 90, the buffer immediately before next may be removed.

<Detailed Circuit Diagram of Basic Shift Register of Second Embodiment; Second Example>
FIG. 10 is a circuit diagram (FIG. 10A) of the second example showing details of the basic shift register 42 used in the shift register circuit 40 of the second embodiment, and a timing chart (FIG. B)).

  In this second example, the inverter buffer in the delay circuit 90 is configured to be connected in an even number of stages, and the state on the output side of the inverter buffer substantially equal to the gate output point A is set to the basic shift register 42 in the next stage. It is characterized in that it is used as a transfer pulse next.

  In the figure, inverter buffers 92 and 94 are cascaded between the latch positive phase output point C on the latch circuit 60 side and the gate input point A ′ of the transistor n4. Further, cascade connection of inverter buffers 96 and 98 is provided between the latch anti-phase output point B on the latch circuit 60 side and the gate connection point B ′ of the transistors p4 and n5.

  The state of the output point A ′ of the cascaded inverter buffers 92 and 94 is substantially the same as the state of the gate output point A and the latch positive phase output point C. The state of the output point B ′ of the cascade-connected inverter buffers 96 and 98 is substantially the same as the state of the latch reverse phase output point B. Here, “substantially the same” means that the gate delay is ignored.

  Also in the configuration of the second example, the basic shift register 42 includes a transfer gate circuit 50, a latch circuit 60, an output circuit 70, and other peripheral elements as shown in FIG. Although the output buffer circuit 80 is also provided for the output signal next to the shift pulse input terminal IN at the subsequent stage, the inverter before the next terminal is set to an even number and the signal from the gate input point A ′ is sent to the next stage. To communicate to.

  Also in the basic shift register 42 of the second example of the second embodiment, the number of transistors can be reduced and the frame can be narrowed as compared with the conventional shift register 24 shown in FIG.

  The operation of the basic shift register 42 configured as described above can be easily guessed by combining the description of the second example of the first embodiment and the first example of the second embodiment. So I will omit the explanation.

<Detailed Circuit Diagram of Basic Shift Register of Second Embodiment; Third Example>
FIG. 11 is a circuit diagram (FIG. 11A) of a third example showing details of the basic shift register 42 used in the shift register circuit 40 of the second embodiment, and a timing chart (FIG. B)).

  The third example is characterized in that the logic polarity of the clock pulse output from the output circuit 70 is reversed with respect to the basic shift register 42 of the first example of the second embodiment. Specifically, in order to reverse the logic polarity, first, the inversion pulse xCK2 is used instead of the clock pulse CK2.

  Further, at the gate output point A of the transfer gate circuit 50, a Pch transistor p6 as a reset switch is provided in place of the Nch transistor n6 as a reset switch. The transistor p6 has a drain connected to the gate output point A, a source connected to the power supply VDD, and a reset pulse rst input to the gate. The reset pulse rst is set to High during normal driving.

  As described above, the output buffer circuit 80 is not an indispensable component for the basic shift register 42 in the second embodiment. In this third example, the output buffer circuit 80 is removed to reduce the number of elements, and the gate output point The state of the gate input point A ′ equivalent to A and the latch positive phase output point C is directly output to the next stage as the transfer pulse next.

  The output circuit 70 includes a CMOS switch including an Nch transistor n5 and a Pch transistor p5, and a Pch transistor p4. The CMOS switch including the transistors n5 and p5 receives the inverted clock pulse xCK2 on the input side, and the output is used as the output terminal OUT of the basic shift register 42.

  The transistor p4 has a gate connected to the gate of the transistor n5, that is, a gate input point B ′ substantially equal to the latch antiphase output point B, a source connected to the power supply VDD, and a drain connected to the output of the CMOS switch. .

  The CMOS switch including the transistors n5 and p5 receives the inverted clock pulse xCK2, and outputs the inverted clock pulse xCK2 to the output terminal OUT under the output state of the latch circuit 60. Specifically, the CMOS switch is turned on when the gate input point A ′ = Low and the gate connection point B ′ = High, thereby outputting the state of the inverted clock pulse xCK2 to the output terminal OUT. Further, using the transistor p4, the transistor n4 is turned on and the output terminal OUT is fixed to High in an inactive state while the latch reverse phase output point B at which the CMOS switch is turned off is Low. ing.

  Note that the CMOS switch may be a switch using only one of the transistors n5 and p5, or an Nch type MOS transistor or a Pch type MOS transistor. In this case, however, there is a problem of the threshold voltage Vth. , P5 CMOS switch is used.

<Detailed Circuit Diagram of Basic Shift Register of Second Embodiment; Fourth Example>
FIG. 12 is a circuit diagram (FIG. 12A) of a fourth example showing details of the basic shift register 42 used in the shift register circuit 40 of the second embodiment, and a timing chart (FIG. B)).

  The fourth example is characterized in that the logic polarity of the clock pulse output from the output circuit 70 is reversed with respect to the basic shift register 42 of the second example of the second embodiment. The delay circuit 90 requires an even number of inverter buffers, and the potential at the gate input point B ′ is used as the gate of the transistors p4 and n5, and the potential at the gate input point A ′ is used as the next pulse.

  The operation of the basic shift register 42 having the configuration of the fourth example can be easily guessed by combining the description of the second example and the third example of the second embodiment described above. Omit.

  In the first to fourth examples of the second embodiment, the latch circuit 60A according to the second example of the first embodiment can be used instead of the latch circuit 60.

<Comparison with conventional example>
FIG. 13 illustrates a comparison between the basic shift register 42 of the first embodiment shown in FIG. 4 and the basic shift register 42 of the second embodiment shown in FIG. 9 and the conventional shift register 24 shown in FIG. It is a figure to do. The structure of the shift register is shown below each table.

  13A shows the case of the configuration of the conventional shift register 24, and FIG. 13B shows the configuration of the basic shift register 42 shown in FIG. 4 and the basic shift register 44 shown in FIG. Show the case. The total number of transistors for each two stages and their channel types are shown.

  Note that the number of elements corresponding to the output buffer circuit 80 in FIG. 9 is omitted. The conventional shift register and the shift register shown in the above embodiment both have a reset input terminal. However, the reset operation is not essential in the shift operation, and there is a difference in each reset operation. Since it is not, it is omitted in FIG.

  In the conventional shift register 24 shown in FIG. 13A, there are 20 NMOS (Nch MOS transistors) and PMOS (Pch MOS transistors), for a total of 40. On the other hand, in the basic shift register 42 of the first embodiment shown in FIG. 13B, the number of NMOS is 16 and the number of PMOS is 12, which is 28 in total. It can be seen that it has been reduced by 30%.

  Further, in the case of the basic shift register 44 using the delay shown in FIG. 9, the number of elements is similarly reduced by about 30% with 16 NMOSs and 12 PMOSs, for a total of 28 elements.

  One conventional shift register has terminals CKin, xCKin, ENB, IN, OUT, and next, and requires three external input pulses CK, ENB, and ST. xCKin was generated by a circuit in the panel.

  On the other hand, in the shift register according to the above-described embodiment, both the first and second embodiments have IN, CKinA, xCKinA, CKinB, next, and OUT terminals, and three terminals CK1, CK2, and ST are provided. An external input pulse is required. xCK1 and xCK2 are generated inside the panel.

  In both the first and second embodiments, all circuits are composed of CMOS. Using the blanking period of the first and second clock pulses CK1 and CK2 for driving the shift circuits having different phases, a part of these clock pulses is transferred to the next transfer clock or the drive pulse signal (gate Since the circuit is controlled so as to be used as a signal in the active period of the pulse), it is not necessary to provide a NAND circuit controlled by the enable pulse ENB in order to remove the overlap of the transfer pulse, compared with the conventional type. The number of transistors can be reduced, and the frame can be narrowed.

  Further, since the number of required external input pulses is three, which is the same as in the conventional configuration, there is no hardware problem in applying the shift register circuit 40 of this embodiment to a liquid crystal display device.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, the shift register circuit 40 described in the above embodiment and the basic shift register 42 or the TFT element structure which is a basic element thereof are not limited to application to a liquid crystal display device, but include an organic EL (Electro luminescence), etc. It can also be used for other display devices. These display devices are installed in, for example, a PDA (Personal Digital Assistant), a mobile phone, or a notebook personal computer.

It is a figure which shows the outline | summary of one Embodiment of the liquid crystal display device which applied one Embodiment of the shift register circuit based on this invention to the drive circuit. 1 is a circuit block diagram showing a first embodiment of a shift register circuit according to the present invention. 3 is a timing chart for explaining the operation of the shift register circuit shown in FIG. 2. FIG. 3 is a circuit diagram of a first example showing details of a basic shift register used in the shift register circuit of the first embodiment, and a timing chart for explaining the operation thereof. FIG. 5 is a circuit diagram of a second example showing details of a basic shift register used in the shift register circuit of the first embodiment, and a timing chart explaining the operation thereof. FIG. 6 is a circuit diagram of a third example showing details of a basic shift register used in the shift register circuit of the first embodiment, and a timing chart explaining the operation thereof. It is a timing chart explaining the problem of a delay margin. FIG. 6 is a circuit block diagram showing a second embodiment of a shift register circuit according to the present invention and a timing chart for explaining the operation thereof. FIG. 6 is a circuit diagram of a first example showing details of a basic shift register used in the shift register circuit of the second embodiment, and a timing chart explaining its operation. It is a circuit diagram of the 2nd example showing details of a basic shift register used for a shift register circuit of a 2nd embodiment, and a timing chart explaining the operation. It is a circuit diagram of the 3rd example showing details of a basic shift register used for a shift register circuit of a 2nd embodiment, and a timing chart explaining the operation. It is a circuit diagram of the 4th example showing details of a basic shift register used for a shift register circuit of a 2nd embodiment, and a timing chart explaining the operation. It is a figure explaining the comparison with the basic shift register of 1st Embodiment, the basic shift register of 2nd Embodiment, and the conventional shift register. It is a figure which shows the example of 1 structure of the liquid crystal display device which applied the conventional shift register circuit to the drive circuit. It is a basic circuit diagram explaining a conventional shift register. It is a circuit diagram which shows the detailed structure of the 1st basic shift register which comprises the conventional shift register. It is a circuit diagram which shows the detailed structure of the 2nd basic shift register which comprises the conventional shift register. It is a timing chart which shows operation | movement of the 1st and 2nd basic shift register which comprises the conventional shift register.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 10 ... Pixel display part, 20 ... Vertical drive circuit, 22 ... Level shifter, 24 ... Shift register, 26 ... Buffer, 30 ... Horizontal drive circuit, 32 ... Level shifter, 33 ... Shift register, 34 ... Shift register , 36 ... buffer, 38 ... horizontal direction control switch, 40 ... shift register circuit, 42 ... basic shift register, 44 ... basic shift register, 50 ... transfer gate circuit, 60, 60A ... latch circuit, 70 ... output circuit, 80 ... Output buffer circuit, 82 ... inverter, 84 ... inverter, 90 ... delay circuit

Claims (6)

A shift circuit that outputs a drive clock corresponding to an input pulse signal,
A transfer gate circuit for controlling input / output of the input pulse signal under driving by one of two clock pulses having different phases;
A latch circuit for holding a pulse signal input via the transfer gate circuit for a certain period;
An output circuit for outputting a part of the other clock pulse of the two clock pulses as a signal of an active period of the drive clock according to an output state of the latch circuit;
With
The latch circuit is
A first inverter provided with a pulse signal input via the transfer gate circuit at an input end;
A second inverter having an output terminal connected to the input terminal of the first inverter and an input terminal connected to the output terminal of the first inverter;
A shift circuit including a switch circuit connected between an input terminal of the first inverter and an output terminal of the second inverter and turned off when the transfer gate circuit is on . The output circuit is
A switch circuit for controlling input / output of the other clock pulse;
Wherein the switch circuit by driving according to the state of the output of the latch circuit, the shift circuit according to 請 Motomeko 1 that generates a signal of an active period of the driving clock. By holding the output side of the output circuit to a predetermined potential, the shift circuit according to 請 Motomeko 1 or claim 2 including a switching circuit which generates a signal inactive period of the driving clock. Directly a pulse signal outputted from the latch circuit, or the pulse signal via the buffer of a predetermined number of stages, to any one of claims 1 to 3 you output as the next stage of the input pulse signal The shift circuit described. A transfer gate circuit that controls input / output of an input pulse signal under driving by one of two clock pulses having different phases;
A latch circuit for holding a pulse signal input via the transfer gate circuit for a certain period,
The latch circuit is
A first inverter provided with a pulse signal input via the transfer gate circuit at an input end;
A second inverter having an output terminal connected to the input terminal of the first inverter and an input terminal connected to the output terminal of the first inverter;
In a shift circuit having a switch circuit connected between an input terminal of the first inverter and an output terminal of the second inverter and turned off when the transfer gate circuit is on,
A pulse signal generation method for generating a drive clock corresponding to the input pulse signal,
A pulse signal generation method for outputting a part of the other clock pulse of the two clock pulses as a signal of an active period of the drive clock according to an output state of the latch circuit . A display device having a display unit having pixels arranged in a row and a drive circuit connected to each of the pixels, and driving the drive circuit by applying a scanning signal to a control terminal of the drive circuit. And
A shift circuit that outputs a drive clock corresponding to the input pulse signal to the drive circuit;
The shift circuit is
A transfer gate circuit for controlling input / output of the input pulse signal under driving by one of two clock pulses having different phases;
A latch circuit for holding a pulse signal input via the transfer gate circuit for a certain period;
An output circuit for outputting a part of the other clock pulse of the two clock pulses as a signal of an active period of the drive clock according to an output state of the latch circuit;
With
The latch circuit is
A first inverter provided with a pulse signal input via the transfer gate circuit at an input end;
A second inverter having an output terminal connected to the input terminal of the first inverter and an input terminal connected to the output terminal of the first inverter;
A display device comprising: a switch circuit connected between an input terminal of the first inverter and an output terminal of the second inverter and turned off when the transfer gate circuit is on .

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