JP4453476B2 - Shift circuit, shift register circuit, and display device - Google Patents

Description

  The present invention relates to a shift circuit, a shift register circuit, and a display device, and more particularly, to a shift circuit having a level shift function, a shift register circuit formed by cascading a plurality of shift circuits, and the shift register circuit as a part of a drive circuit. Related to the display device.

  As a shift circuit used as each transfer stage (shift stage) of a shift register circuit, a shift circuit with a level shift function for level-shifting (level conversion) a clock pulse serving as a reference of operation from a first amplitude to a second amplitude Is known (see, for example, Patent Document 1). This type of shift register circuit is used as a shift register circuit constituting a scanner used in a display device or an imaging device.

  FIG. 41 is a circuit diagram showing an example of the configuration of a shift circuit with a level shift function. As shown in FIG. 41, the shift circuit 100 according to this example has a configuration in which a current mirror circuit 101 is a basic circuit. The current mirror circuit 101 includes NchMOS transistors (hereinafter abbreviated as “NMOS transistors”) n101 and n102 whose gates are connected to each other, and one NMOS transistor n101 has a diode connection in which the gate and drain are commonly connected. ing. Respective phase clocks CK and xCK having a low voltage amplitude (for example, 0 [V] to 3 [V]) are input to the sources of the NMOS transistors n101 and n102, respectively.

  In the current mirror circuit 101, the drain output of the NMOS transistor n102 has a high voltage amplitude of VSS-VDD (for example, 0 [V] -8 [V]), and is output as the transfer pulse OUT after being inverted by the inverter 102. PchMOS transistors (hereinafter abbreviated as “PMOS transistors”) p101 and p102 are connected between the drains of the NMOS transistors n101 and n102 and the power supply potential VDD, respectively.

  NMOS transistors n103 and n104 are connected in series between the drain of the NMOS transistor n101 and the power supply potential VSS. The transfer pulse IN is inverted by the inverter 103 and applied to the gate of the NMOS transistor n103. The drain output of the NMOS transistor n102 is directly given to the gate of the NMOS transistor n104.

  PMOS transistors p103 and p104 are connected in series between the gate of the PMOS transistor p101 and the power supply potential VDD. PMOS transistors p105 and p106 are connected in series between the gate of the PMOS transistor p102 and the power supply potential VDD. PMOS transistors p107 and p108 are connected in parallel between the drain of the NMOS transistor n102 (the drain of the PMOS transistor p102) and the power supply potential VDD.

  The drain output of the NMOS transistor n102 after being inverted by the inverter 102, that is, the transfer pulse OUT is applied to the gates of the PMOS transistors p103, p105, and p107. A transfer pulse IN is directly applied to the gates of the PMOS transistors p104, p106, and p108.

  A clock pulse xCK is applied to the gate of the PMOS transistor p101 via NMOS transistors n105 and n106 connected in parallel to each other. A clock pulse CK is applied to the gate of the PMOS transistor p102 via NMOS transistors n107 and n108 connected in parallel. The transfer pulse IN is directly applied to the gates of the NMOS transistors n105 and n107. A transfer pulse OUT is applied to the gates of the NMOS transistors n106 and n108.

  PMOS transistors p109 and p110 are connected between the gate of the NMOS transistor n103 and the power supply potential VDD, and between the drain of the NMOS transistor n102 (drain of the PMOS transistor p102) and the power supply potential VDD, respectively. A low active reset pulse rst is applied to the gates of the PMOS transistors p109 and p110.

  As is clear from the circuit configuration described above, the shift circuit 100 according to this conventional example has a configuration in which a current mirror type level shift circuit using the current mirror circuit 101 and a clock-out shift circuit are combined, and the transfer pulse The level shift circuit operates when IN is High or the transfer pulse OUT is High.

JP 2002-287711 A

  The shift circuit 100 with a level shift function according to the conventional example having the above configuration has a circuit configuration based on the current mirror circuit 101, and therefore between the power supply potential VDD and the clock pulses CK and XCK (dotted line arrows in the figure). The leakage current (through current) always flows when the level shift circuit is driven, and this leakage current causes the power consumption of the shift circuit 100 to increase.

  Further, since there is a leak between VDD-CK and XCK, the clock pulse CK and xCK are required to have an output capability to absorb the leak. Since the characteristics of the pair of NMOS transistors n101 and n102 constituting the mirror circuit 101 need to be the same, there is a problem that they are vulnerable to variations in transistor characteristics.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a shift circuit that can reduce power consumption, is resistant to variations in transistor characteristics, and has a low burden on clock pulses. It is an object of the present invention to provide a shift register circuit formed by cascading a plurality of circuits and a display device in which the shift register circuit is mounted as a part of a drive circuit.

The shift circuit according to the present invention includes level shift means for level-shifting a clock pulse from a first amplitude to a second amplitude and outputting the control pulse when the control pulse is in an active state, and control pulse generation means for generating the control pulse And
The level shift means is
The first and second transistors of opposite conductivity type connected in series between the first power supply potential and the second power supply potential, a clock terminal to which the clock pulse is input, the clock terminal, A first switch means connected between the first transistor and being turned on when the control pulse is in an active state; and between the second power supply potential and the gate of the second transistor. And a second switch means that is turned off when the control pulse is in an active state, and a capacitor element connected between the clock terminal and the gate of the second transistor. ing.

  In the shift circuit with a level shift function configured as described above, when the control pulse is in the active state, the first switch means is turned on, so that the clock terminal passes through the first switch means to the gate of the first transistor. At the same time as the clock pulse is applied, the second switch means is turned off, so that the supply of the second power supply potential to the gate of the second transistor is cut off, and the gate of the second transistor is in a floating state. At the same time, a clock pulse is transmitted to the gate of the second transistor by coupling using a capacitive element.

  At this time, the clock pulses applied to the gates of the first and second transistors have the same phase, but the high-level potential of the clock pulse applied to the gate of the second transistor becomes the second power supply potential. The potential on the high level side of the clock pulse applied to the gate of the first transistor is relatively shifted. The amplitude of the clock pulse is larger than the threshold value Vth of the first and second transistors. As a result, the first and second transistors are surely turned off from the relationship of the gate potential at the timing to be turned off. Therefore, in the complementary circuit composed of the first and second transistors, leakage when these transistors are off can be reliably prevented.

  According to the present invention, it is possible to reliably prevent leakage when the level shift unit is turned off, so that power consumption can be reduced, and a circuit configuration that does not use a current mirror circuit is employed. Can provide.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram showing a circuit configuration of a shift circuit according to the first embodiment of the present invention. The shift circuit 10 according to the present embodiment has a configuration including a level shift unit 11 and a control pulse generation unit 12.

  The level shift unit 11 changes the clock pulse CK from VSS-Vin amplitude (for example, 0 [V] -3 [V] amplitude) to VSS-VDD when the control pulse NSW given from the control pulse generating unit 12 is in an active state. The level is shifted to an amplitude (for example, 0 [V] -8 [V] amplitude), and output as an output pulse OUT. Note that the high potential Vin of the clock pulse CK needs to be larger than the threshold value Vth of the transistor (VDD> Vin> Vth). The control pulse generator 12 generates a pulse that is in an active state for one cycle of the clock pulse CK, and supplies the pulse to the level shift unit 11 as a control pulse NSW.

  FIG. 2 shows the level relationship and timing relationship of the clock pulse CK, the input pulse IN of the control pulse generator 12, the control pulse NSW, the negative phase control pulse PSW of the control pulse NSW, and the output pulse OUT.

  Here, examples of specific circuit configurations of the level shift unit 11 and the control pulse generator 12 will be described. First, the level shift unit 11 will be described.

(Example 1 of the level shifter 11)
FIG. 3 is a circuit diagram illustrating a configuration of the level shift unit (LS1) 11A according to the first embodiment. As illustrated in FIG. 3, the level shift unit 11A according to the first embodiment includes a complementary circuit 21, first to third switch circuits 22 to 24, a capacitive element Cap, and a buffer 25, and a clock terminal 26, The control terminal 27 and the output terminal 28 are provided.

  The complementary circuit 21 includes first and second transistors of opposite conductivity types connected in series between the power supply potential VSS and the power supply potential VDD, that is, an NMOS transistor n11 and a PMOS transistor p11. The drains of the NMOS transistor n11 and the PMOS transistor p11 are connected to the circuit output terminal 28 via the buffer 25.

  The first switch circuit 22 is constituted by an NMOS transistor n12. The drain of the NMOS transistor n12 is connected to the clock terminal 26, the source is connected to the gate of the NMOS transistor n11, and the gate is connected to the control terminal 27. The clock terminal 26 receives a clock pulse CK having a VSS-Vin amplitude (for example, 0 [V] -3 [V] amplitude). The control terminal 27 receives a control pulse NSW that is generated by the control pulse generator 12 and is in an active state (High potential = power supply potential VDD) for one cycle of the clock pulse CK.

  The second switch circuit 23 is connected between the power supply potential VDD and the gate of the PMOS transistor p11, and is configured by a PMOS transistor p12 having the control pulse NSW as a gate input. The second switch circuit 23 is turned off when the control pulse NSW is in an active state (High potential), thereby cutting off the electrical connection between the power supply potential VDD and the gate of the PMOS transistor p11. The gate of p11 is brought into a floating state.

  The third switch circuit 24 is connected between the power supply potential VDD and the gate of the NMOS transistor n11, and is configured by a PMOS transistor p15 having the control pulse NSW as a gate input. The third switch circuit 24 is turned off when the control pulse NSW is in an active state, thereby cutting off the electrical connection between the power supply potential VDD and the gate of the NMOS transistor n11.

  The capacitive element Cap is connected between the clock terminal 26 and the gate of the NMOS transistor n11. As a result, the clock pulse CK is transmitted to the gate of the PMOS transistor p11 by the coupling by the capacitive element Cap.

  The buffer 25 is composed of, for example, an inverter buffer circuit. However, the buffer 25 is not essential and is arranged as necessary.

  Next, the circuit operation of the level shift unit 11A according to the first embodiment having the above configuration will be described with reference to the timing chart of FIG.

  First, when the control pulse NSW is at the low potential (power supply potential VSS), the NMOS transistor n12 is turned off and the PMOS transistors p12 and p13 are turned on, so that the node A (PMOS transistor) is turned on regardless of the logic state of the clock pulse CK. The potential VA of the gate of p11 and the potential VB of the node B (of the NMOS transistor n11) are the power supply potential VDD. Accordingly, the PMOS transistor p11 is turned off and the NMOS transistor n11 is turned on, so that the output pulse OUT becomes the power supply potential VSS.

  When the control pulse NSW is at a high potential (power supply potential VDD), that is, in the driving state of the level shift unit 11A, the NMOS transistor n12 is in the on state and the PMOS transistors p12 and p13 are in the off state. Thus, the clock pulse CK is coupled through the capacitive element Cap. A clock pulse CK is supplied to the node B through the NMOS transistor n12.

  Here, the control pulse NSW is in an active state (High potential) during a period of one cycle of the clock pulse CK, and the level shift unit 11A is driven by the one cycle. In this one cycle, the clock amplitude of the node B is VSS / Vin, the clock amplitude of the node A is VDD−Vin / VDD, and the clocks applied to the nodes A and B are in phase.

  Thereby, the PMOS transistor p11 and the NMOS transistor n11 are surely turned off from the relationship between the potentials VA and VB of the nodes A and B at the timing to be turned off. Therefore, in the complementary circuit 21 including the PMOS transistor p11 and the NMOS transistor n11, the clock pulse CK is level-shifted to the output pulse OUT with the amplitude of VSS-VDD while reliably preventing leakage when the MOS transistors p11 and n11 are turned off ( Level conversion).

  As described above, a clock pulse CK having an amplitude of VSS-Vin (for example, 0 [V] -3 [V]) is leveled to an output pulse OUT having an amplitude of VSS-VDD (for example, 0 [V] -8 [V]). In the shifting level shift unit 11A, the complementary circuit 21 including the NMOS transistor n11 and the PMOS transistor p11 is a basic circuit, and the clock pulse CK is applied to the gate of the NMOS transistor n11 during the level shift driving, while the gate of the PMOS transistor p11 is applied. Provides a clock pulse obtained by relatively shifting the clock pulse CK to the power supply potential VDD side by coupling with the cap element Cap, so that the NMOS transistor n11 and the PMOS transistor p11 are surely turned off at the timing to be turned off. , Never leak current flows to the auxiliary resistance circuit 21.

  As described above, the leakage current does not flow through the level shift unit 11A, so that the power consumption of the shift circuit 10 can be reduced. Further, since the complementary circuit 21 composed of a reverse conductivity type transistor is used as a basic circuit, there is no leakage current and the transistor is always driven in the saturation region of the transistor. Therefore, the current mirror circuit is used as a basic circuit. It is possible to realize a level shift unit 11A that is resistant to variations in transistor characteristics (threshold Vth, drain-source current Ids, etc.) as seen in such a level shift circuit, that is, circuit performance is not greatly affected by variations in transistor characteristics. In addition, since there is no leakage between the power supply potential VDD and the clock pulse CK, the burden on the clock pulse CK can be reduced.

  However, in the circuit configuration of the level shift unit 11A according to the first embodiment, even when the control pulse NSW is at the low potential and the node A is fixed at the power supply potential VDD, the coupling of the clock pulse CK through the capacitive element Cap is the node. There is concern about A. Due to the influence of this coupling, the potential VA of the node A may fluctuate, and the fluctuation of the potential may appear as, for example, beard-like noise in the output pulse OUT. A circuit configuration that improves this is the level shift unit 11B according to the second embodiment.

(Example 2 of the level shift unit 11)
FIG. 5 is a circuit diagram illustrating a configuration of the level shift unit (LS2) 11B according to the second embodiment, and the same components as those in FIG. 3 are denoted by the same reference numerals.

  The level shift unit 11B according to the second embodiment has a configuration including a fourth switch circuit 31 and a fifth switch circuit 32 in addition to the components of the level shift unit 11A according to the first embodiment. The fourth switch circuit 31 is connected between the clock terminal 26 and one end of the capacitive element Cap, and is configured by an NMOS transistor n13 having a control pulse NSW as a gate input. The fifth switch circuit 32 is connected between the voltage terminal 33 and one end of the capacitive element Cap, and includes a PMOS transistor p14 that receives the control pulse NSW as a gate input. The voltage terminal 33 receives a constant voltage Vin.

  Next, the circuit operation of the level shift unit 11B according to the second embodiment having the above configuration will be described with reference to the timing chart of FIG. Since the basic circuit operation is the same as the circuit operation of the level shift unit 11A according to the first embodiment, the description here focuses on the operations of the newly added fourth and fifth switch circuits 31 and 32. It shall be.

  In the fourth switch circuit 31, the NMOS transistor n13 is turned on when the control pulse NSW is in the active state (High potential = power supply potential VDD) and supplies the clock pulse CK to the node C (one end of the capacitor Cap). On the other hand, when the control pulse NSW is in an inactive state (Low potential = power supply potential VSS), the control pulse NSW is turned off, and the electrical connection between the clock terminal 26 and the capacitive element Cap is interrupted. Do not extend to node A.

  Further, in the fifth switch circuit 32, the PMOS transistor p14 is turned off when the control pulse NSW is in the active state and cuts off the electrical connection between the voltage terminal 33 and the node C, while the control pulse NSW When the NSW is in an inactive state, it is turned on, and the potential VC of the node C is fixed to the constant potential Vin by electrically connecting the voltage terminal 33 and the node C.

  As described above, in the level shift unit 11B according to the second embodiment, when the control pulse NSW is in an inactive state, the electrical connection between the clock terminal 26 and the node C is interrupted and the potential of the node C By fixing VC to a constant potential Vin, it is possible to prevent the coupling of the clock pulse CK through the capacitive element Cap from reaching the node A. Therefore, there is a beard-like noise caused by the fluctuation of the potential VA of the node A. It does not appear in the output pulse OUT.

  Here, the on-resistance of the NMOS transistors n12 and n13 will be considered. The NMOS transistors n12 and n13 are switches for supplying the clock pulse CK to the nodes B and C when the control pulse NSW is in an active state. Since the supply period of the clock pulse CK corresponds to one cycle of the clock pulse CK, the switch circuits 22 and 31 need to have an ability to sufficiently supply the high-side potential Vin and the low-side potential VSS of the clock pulse CK. is there. However, if the switch circuits 22 and 31 are composed of the NMOS transistors n12 and n13 alone, the on-resistance becomes higher at the high-side potential Vin of the clock pulse CK than the gate voltage VDD at the on-time.

  Next, gate-drain or gate-source coupling will be considered. When the control pulse NSW transitions from the active state (power supply potential VDD) to the inactive state (power supply potential VSS), there is a gate-drain coupling or a gate-source coupling. There is a concern that the circuit may malfunction due to jumping in due to this coupling.

  The level shift unit 11C according to the third embodiment is a circuit configuration in which such concerns regarding the on-resistance and gate-drain or gate-source coupling of the NMOS transistors n12 and n13 are improved.

  A configuration of the shift circuit 10 when the level shift unit 11B according to the second example is used as the level shift unit 11 is illustrated in FIG. 7 as a shift circuit 10A according to the first modification of the first embodiment.

(Example 3 of the level shift unit 11)
FIG. 8 is a circuit diagram illustrating a configuration of the level shift unit (LS3) 11C according to the third embodiment, and the same components as those in FIG. 5 are denoted by the same reference numerals.

  The level shift unit 11C according to the third embodiment is different from the level shift unit 11B according to the second embodiment in that the switch circuits 22, 23, 24, 31, and 32 are configured using CMOS switches. . That is, the switch circuit 22 includes an NMOS transistor n21 and a PMOS transistor p21 connected in parallel to each other, and a control pulse NSW input to the gate of the NMOS transistor n21 via the control terminal 27 is controlled to the gate of the PMOS transistor p21. A control pulse PSW having a phase opposite to that of the control pulse NSW input via the terminal 34 is applied.

  The switch circuit 23 includes an NMOS transistor n22 and a PMOS transistor p22 connected in parallel to each other, and a negative-phase control pulse PSW is applied to the gate of the NMOS transistor n22, and a positive-phase control pulse NSW is applied to the gate of the PMOS transistor p22. It has come to be. The switch circuit 24 includes an NMOS transistor n23 and a PMOS transistor p23 connected in parallel to each other. A negative-phase control pulse PSW is applied to the gate of the NMOS transistor n23, and a positive-phase control pulse NSW is applied to the gate of the PMOS transistor p23. It has come to be.

  The switch circuit 31 includes an NMOS transistor n24 and a PMOS transistor p24 connected in parallel to each other, and a normal-phase control pulse NSW is applied to the gate of the NMOS transistor n24, and a negative-phase control pulse PSW is applied to the gate of the PMOS transistor p24. It has come to be. The switch circuit 32 includes an NMOS transistor n25 and a PMOS transistor p25 connected in parallel to each other, and a negative-phase control pulse PSW is applied to the gate of the NMOS transistor n25, and a positive-phase control pulse NSW is applied to the gate of the PMOS transistor p25. It has come to be.

  FIG. 9 is a timing chart for explaining the circuit operation of the level shift unit 11C according to the third embodiment. In the case of the level shift unit 11C according to the third embodiment, a control pulse PSW having a phase opposite to that of the control pulse NSW is added.

  As described above, in the level shift unit 11C according to the third embodiment, since the switch circuits 22 and 31 are configured by using CMOS switches, the NMOS transistors in the case where the switch circuits 22 and 31 are configured by an NMOS transistor alone. The concern about the on-resistance, that is, the concern that the on-resistance becomes higher at the high-side potential Vin of the clock pulse CK than the gate voltage VDD at the time of turning on can be eliminated by the action of the PMOS transistors p21 and p24. .

  Further, since the switch circuits 23, 24, and 32 are constituted by CMOS switches, there is a concern due to gate-drain or gate-source coupling when the switch circuits 23, 24, and 32 are constituted by NMOS transistors alone. That is, the concern that the circuit malfunctions due to jumping in due to coupling can be eliminated by the action of the PMOS transistors p22, p23, and p25.

  In the third embodiment, the switch circuits 22, 23, 24, 31, and 32 are configured with CMOS switches to solve the above-mentioned concerns. However, this solution is not always necessary, and circuit constants are not necessary. It is also possible to examine the necessity of countermeasure points for each of the above concerns according to driving conditions (various voltage setting values) and to select the presence or absence of countermeasures.

  A configuration of the shift circuit 10 when the level shift unit 11C according to the third embodiment is used as the level shift unit 11 is illustrated in FIG. 10 as a shift circuit 10B according to the second modification of the first embodiment.

  Next, the control pulse generator 12 that generates the control pulse NSW (reverse phase control pulse PSW) will be described.

  The control pulse NSW is a pulse signal that becomes active (High potential) for one cycle of the clock pulse CK described above. As a method for generating such a control pulse NSW, the following two methods are conceivable.

  Here, description will be made on the assumption that the shift circuit 10 according to the present embodiment is used as each shift stage (transfer stage) of a shift register circuit, for example. The first method uses a self-stage input and a self-stage output in the shift register circuit, which will be described as a first embodiment. The second method uses a self-stage input and a next-stage output in the shift register circuit, and this will be described as Embodiments 2, 3, and 4.

(Example 1 of the control pulse generator 12)
FIG. 11 is a block diagram illustrating the configuration of the control pulse generator (APGa) 12A according to the first embodiment.

  As shown in FIG. 11, the control pulse generator 12A according to the first embodiment includes a NOR circuit 41, an inverter circuit 42, and a reset circuit 43, two input terminals 44 and 45, and two output terminals 46 and 47. The reset terminal 48 is provided. The input terminal 44 receives an input pulse IN1 having the same pulse width as the clock pulse CK. This input pulse IN1 corresponds to the input pulse of its own stage in the shift register circuit. The input terminal 45 receives as input an input pulse IN2 whose phase is shifted by a half cycle of the clock pulse CK with respect to the input pulse IN1. This input pulse IN2 corresponds to the output pulse of its own stage in the shift register circuit.

  The NOR circuit 41 takes a negative OR of the input pulse IN1 and the input pulse IN2. The inverter circuit 42 inverts the output pulse of the NOR circuit 41 to generate a positive-phase control pulse NSW and outputs it through the output terminal 46. Further, the output pulse of the NOR circuit 41 is output as it is as a negative-phase control pulse PSW through the output terminal 47. This anti-phase control pulse PSW is required when the level shift unit 11 is the level shift unit 11C according to the third embodiment. FIG. 12 shows the timing relationship between the input pulses IN1 and IN2 and the control pulses NSW and PSW.

  The reset circuit 43 is connected between the power supply potential VDD and the output terminal of the NOR circuit 41 (the input terminal of the inverter circuit 42), and has a PMOS transistor p30 having a reset pulse rst input through the reset terminal 48 as a gate input. It is constituted by. In the reset circuit 43, when the reset pulse rst becomes a low potential, the PMOS transistor p30 is turned on to reset the output terminal potential of the NOR circuit 41 (the input terminal potential of the inverter circuit 42) to the power supply potential VDD. Is done.

  FIG. 13 is a circuit diagram showing an example of the configuration of the NOR circuit 41. As shown in FIG. 13, the NOR circuit 41 according to this example is connected in series between a power supply potential VDD and an output node Nout, and has PMOS transistors p31 and p32 having input pulses IN1 and IN2 as gate inputs, and outputs. It is configured by NMOS transistors n31 and n32 connected in parallel between the node Nout and the power supply potential VSS and using the input pulses IN1 and IN2 as gate inputs. However, the NOR circuit 41 is not limited to this configuration.

  FIG. 14 is a circuit diagram showing an example of the configuration of the inverter circuit 42. As shown in FIG. 14, the inverter circuit 42 according to the present example includes a PMOS transistor p33 and an NMOS transistor that are connected in series between the power supply potential VDD and the power supply potential VSS, and whose gates and drains are connected in common. It has a CMOS inverter configuration consisting of n33. However, the inverter circuit 42 is not limited to this configuration.

  The control pulse generator 12A according to Example 1 includes a shift circuit 10 according to the first embodiment (FIG. 1), a shift circuit 10A according to Modification 1 (FIG. 7), and a shift circuit 10B according to Modification 2. In FIG. 10, the control pulse generator 12 is used.

(Example 2 of the control pulse generator 12)
FIG. 15 is a block diagram illustrating a configuration of a control pulse generator (APGb1) 12B1 according to the second embodiment.

  As shown in FIG. 15, the control pulse generator 12B1 according to the second embodiment includes a switching circuit 51, a latch circuit 52, and a reset circuit 53, two input terminals 54 and 55, and two output terminals 56 and 57. The reset terminal 58 is provided. The input terminal 54 receives an input pulse PRIN having the same pulse width as that of the clock pulse CK. This input pulse PRIN corresponds to the input pulse of its own stage in the shift register circuit. The input terminal 55 receives an input pulse NXIN whose phase is shifted by one cycle of the clock pulse CK with respect to the input pulse IN1 (PRIN). This input pulse NXIN corresponds to the output pulse of the next stage in the shift register circuit.

  The switching circuit 51 includes a PMOS transistor p41 and an NMOS transistor n41 connected in series between the power supply potential VDD and the power supply potential VSS, and an inverter circuit 511. The input pulse PRIN is inverted by the inverter circuit 511 and applied to the gate of the PMOS transistor p41. The input pulse NXIN is directly applied to the gate of the NMOS transistor n41. The switching circuit 51 switches between the low-side potential VSS and the high-side potential VDD of the control pulse NSW by the input pulse PRIN / NXIN.

  The latch circuit 52 includes an inverter circuit 521 having an input terminal connected to one output terminal 56 (an output terminal of the switching circuit 51) and an output terminal connected to the other output terminal 57, and a reverse direction with respect to the inverter circuit 521. And an inverter circuit 522 connected in parallel to each other. The latch circuit 52 latches the output terminal potential of the switching circuit 51 to maintain the Low side potential VSS / High side potential VDD.

  The output terminal potential of the switching circuit 51 is output as it is from the output terminal 56 as a normal-phase control pulse NSW, and is also output from the output terminal 57 via the latch circuit 52 as a negative-phase control pulse PSW. This anti-phase control pulse PSW is required when the level shift unit 11 is the level shift unit 11C according to the third embodiment. FIG. 16 shows the timing relationship between the input pulses PRIN and NXIN and the control pulses NSW and PSW.

  The reset circuit 53 is connected between the output terminal of the switching circuit 51 and the power supply potential VSS, and is configured by an NMOS transistor n42 having a reset pulse rst input through the reset terminal 58 as a gate input. In the reset circuit 53, when the reset pulse rst becomes a high potential, the NMOS transistor n42 is turned on, and a reset operation for setting the output terminal potential of the switching circuit 51 to the power supply potential VSS is performed.

  Since the control pulse generator 12B1 according to the second embodiment having the above configuration employs the configuration using the latch circuit 52, every time the control pulse NSW is switched between the low-side potential VSS and the high-side potential VDD, A collision occurs between the output of the switching circuit 51 and the output of the latch circuit 52 on the signal line between the output terminal of the switching circuit 51 and the output terminal 56. Therefore, in order to perform switching smoothly, the output of the switching circuit 51 needs to be larger than the output of the latch circuit 52. Therefore, in designing the control pulse generator 12B1, it is necessary to determine circuit constants while paying attention to this portion.

  In order to realize stable driving in the control pulse generator 12, it is preferable to avoid a collision between the output of the switching circuit 51 and the output of the latch circuit 52. Therefore, the circuit configuration that avoids the collision between the output of the switching circuit 51 and the output of the latch circuit 52 is the control pulse generators 12B2 and 12B3 according to the third and fourth embodiments.

(Example 3 of the control pulse generator 12)
FIG. 17 is a block diagram illustrating a configuration of a control pulse generation unit (APGb2) 12B2 according to the third embodiment. In the drawing, the same components as those in FIG. 15 are denoted by the same reference numerals.

  As shown in FIG. 17, in addition to the components of the control pulse generator 12B1 according to the second embodiment, the control pulse generator 12B2 according to the third embodiment includes an output terminal of the switching circuit 51 and an output terminal of the latch circuit 52. The switch circuit 59 is provided between the two.

  The switch circuit 59 includes a NOR circuit 591 having two inputs of the input pulses PRIN and NXIN, an inverter circuit 592 that inverts the output of the NOR circuit 591, and an output terminal of the switching circuit 51 and an output terminal of the latch circuit 52. The switch element 593 is connected. The switch element 593 is connected in parallel to each other, and has a CMOS switch configuration including an NMOS transistor n43 and a PMOS transistor p43 that have the outputs of the NOR circuit 591 and the inverter circuit 592 as gate inputs.

  In the control pulse generator 12B2 according to the third embodiment having the above-described configuration, the NOR circuit 591 takes the negative OR of the input pulses PRIN and NXIN, and the output terminal of the switching circuit 51 and the latch circuit 52 based on the result of the OR operation. By performing control to electrically connect / disconnect the output terminal of the control pulse NSW, the output of the switching circuit 51 and the output of the latch circuit 52 are switched when the control pulse NSW is switched between the low-side potential VSS and the high-side potential VDD. It is possible to avoid a collision between the two. FIG. 18 shows the timing relationship between the input pulses PRIN and NXIN, the potentials VA and VB of the nodes A and B, and the control pulses NSW and PSW.

(Embodiment 4 of the control pulse generator 12)
FIG. 19 is a block diagram illustrating a configuration of a control pulse generator (APGb3) 12B3 according to the fourth embodiment. In the figure, the same components as those in FIG. 17 are denoted by the same reference numerals.

  As illustrated in FIG. 19, the control pulse generator 12B3 according to the fourth embodiment replaces the switch circuit 59 of the control pulse generator 12B2 according to the third embodiment with two switch circuits 59A and 59B of the switching circuit 51. The output terminal and the output terminal of the latch circuit 52 are connected in series.

  The switch circuit 59A is configured by a CMOS switch including an NMOS transistor n43 and a PMOS transistor p43 connected in parallel to each other. The input pulse NXIN is inverted by the inverter circuit 592 and applied to the gate of the NMOS transistor n43. The pulse NXIN is directly applied to the gate of the PMOS transistor p43.

  The switch circuit 59B is configured by a CMOS switch including an NMOS transistor n44 and a PMOS transistor p44 connected in parallel to each other. The input pulse PXIN is inverted by the inverter circuit 511 and applied to the gate of the NMOS transistor n44. The pulse PXIN is directly applied to the gate of the PMOS transistor p44.

  In the control pulse generator 12B3 according to the fourth embodiment having the above-described configuration, two switch circuits 59A and 59B are connected in series between the output terminal of the switching circuit 51 and the output terminal of the latch circuit 52. 59B is ON / OFF controlled by the input pulse NRIN and the input pulse PXIN, so that the output of the switching circuit 51 and the output of the latch circuit 52 are switched when the control pulse NSW is switched between the low-side potential VSS and the high-side potential VDD. It is possible to avoid a collision between the two.

  The control pulse generator 12B (the control pulse generators 12B1, 12B2, and 12B3 according to the second, third, and fourth embodiments) that employs the above-described method using the input of the own stage and the output of the next stage in the shift register circuit is also a shift register circuit. The shift circuit 10 uses the control pulse generator 12 as the control pulse generator 12 in the same manner as the control pulse generator 12A adopting the method using the own stage input and the own stage output.

  When the control pulse generation unit 12B is used as the control pulse generation unit 12, the configuration of the shift circuit 10 using the level shift unit 11A according to the first embodiment as the level shift unit 11 according to the third modification of the first embodiment. FIG. 20 shows the configuration of the shift circuit 10C, and FIG. 21 shows the configuration of the shift circuit 10 using the level shift unit 11B according to Example 2 as the level shift unit 11 as the shift circuit 10D according to Modification 4 of the first embodiment. The configuration of the shift circuit 10 using the level shift unit 11C according to Example 3 as the level shift unit 11 is shown in FIG. 22 as a shift circuit 10E according to Modification 5 of the first embodiment.

  FIG. 23 shows the timing relationship between the clock pulse CK, the input pulses PRIN and NXIN, the control pulses NSW and PSW, and the output pulse OUT used in the shift circuits 10C, 10D, and 10E according to the modified examples 3, 4, and 5.

  The shift circuits 10D and 10E according to the modification examples 4 and 5 are different from the shift circuit 10C according to the modification example 3 in that the constant voltage Vin is supplied to the level shift units 11B and 11C. The significance of applying the voltage Vin is as described in the level shift unit 11B according to the second embodiment, and the basic operation is the same for any of the shift circuits 10C, 10D, and 10E.

  The control pulse generator 12B has three types of control pulse generators 12B1, 12B2, and 12B3 according to the second, third, and fourth embodiments. The three patterns of the combination of the unit 12B and the level shift units 11A, 11B, and 11C according to the first, second, and third examples are shown as examples, but actually, the control pulse according to the second, third, and fourth examples There are combinations of the generation units 12B1, 12B2, and 12B3 and the level shift units 11A, 11B, and 11C according to the first, second, and third embodiments, and a total of nine combinations are possible.

  The shift circuit 10 (10A, 10B, 10C, 10D) composed of various combination patterns of the level shift unit 11 (11A, 11B, 11C) and the control pulse generator 12 (12A, 12B1, 12B2, 12B3) described above. , 10E) can be used as a general shift circuit with a level shift function, and can also be used as each transfer stage (shift stage) of the shift register circuit. Hereinafter, an application example in which the shift circuit 10 (10A, 10B, 10C, 10D, 10E) according to the first embodiment is used for each shift stage of the shift register circuit will be described.

(Application 1)
FIG. 24 is a block diagram showing a configuration of a shift register circuit according to Application Example 1 of the present invention. As shown in FIG. 24, the shift register circuit 61A according to the first application example includes the shift circuit 10 according to the first embodiment or the shift circuits 10A and 10B according to the modifications 1 and 2 connected in cascade. A clock pulse CK and a reverse-phase clock pulse xCK are alternately supplied to the transfer stage, and a start pulse ST that instructs the start of the shift operation is given to the first shift stage as an input pulse IN, and the output of each transfer stage The pulse OUT becomes the input pulse IN of the next stage and is derived as transfer pulses o1, o2, o3,.

  In addition, a reset pulse rst and a constant voltage Vin that are always at a High potential (power supply potential VDD) during driving are commonly applied to the transfer stages. However, when the shift circuit 10 according to the first embodiment is used as each transfer stage, it is not necessary to apply the constant voltage Vin. FIG. 25 shows the timing relationship between the clock pulses CK and xCK, the start pulse ST, the first and second control pulses NSW, and the output pulses (transfer pulses) o1, o2, o3, o4,. .

(Application example 2)
FIG. 26 is a block diagram showing a configuration of a shift register circuit according to Application Example 2 of the present invention. As shown in FIG. 26, in the shift register circuit 61B according to the second application example, the shift circuits 10C to 10E according to the modification examples 3 to 5 of the first embodiment are cascaded in 2N (N is a natural number) stages (even stages). Then, the clock pulse CK and the reverse-phase clock pulse xCK are alternately supplied to each transfer stage, and the start pulse ST is supplied as the input pulse PRIN to the first shift stage. Further, in each transfer stage, the output pulse OUT of the own stage becomes the input pulse PRIN of the next stage and is derived as transfer pulses o1, o2, o3,.

  Further, a reset pulse rst and a constant voltage Vin, which are always at a low potential (power supply potential VSS) during driving, are commonly applied to the respective transfer stages. However, when the shift circuit 10C according to the modification 3 is used as each transfer stage, it is not necessary to apply the constant voltage Vin.

  Here, the shift circuits 10C to 10E according to the modified examples 3 to 5 are circuits that require the output pulse OUT of the next stage as the input pulse NXIN of the own stage. However, in the case of the last transfer stage (2N stage), the next transfer stage does not exist, and therefore the end pulse ED corresponding thereto is externally applied to the last transfer stage instead of the output pulse of the next stage. Will give.

  FIG. 27 shows clock pulses CK, xCK, start pulse ST, first stage, second stage, 2N stage control pulse NSW, output pulses (transfer pulses) o1, o2, o3,. The timing relationship of the end pulse ED is shown.

(Application 3)
FIG. 28 is a block diagram showing a configuration of a shift register circuit according to the third application example of the present invention. As shown in FIG. 28, the shift register circuit 61C according to the third application example has a configuration in which the shift circuits 10C to 10E according to the modification examples 3 to 5 of the first embodiment are cascade-connected in 2N-1 stages (odd number stages). The shift register circuit 61B according to the application example 2 is only the difference in whether the number of transfer stages is an odd number or an even number.

  FIG. 29 shows clock pulses CK, xCK, start pulse ST, first stage, second stage, 2N stage-1 control pulse NSW, output pulses (transfer pulses) o1, o2, o3,. The timing relationship between o2N-1 and the end pulse ED is shown.

(Application 4)
FIG. 30 is a block diagram showing a configuration of a shift register circuit according to Application Example 4 of the present invention. As shown in FIG. 30, the shift register circuit 61D according to the fourth application example includes 2N (even numbered) transfer stages, and is a modification of the first embodiment as the first to 2N−1 transfer stages. The shift circuits 10C to 10E according to Examples 3 to 5 are used, and the shift circuit 10 according to the first embodiment or the shift circuits 10A and 10B according to modifications 1 and 2 thereof are used as the final transfer stage (2N stage). It has become the composition.

  As described above, by arranging the shift circuit 10 according to the first embodiment or the shift circuits 10A and 10B according to the first and second modifications as the final transfer stage, the end pulse ED with respect to the final transfer stage. There is an advantage that it is not necessary to give the outside. Here, the case where the transfer stage is an even number stage is taken as an example. However, even when the transfer stage is an odd number stage (FIG. 28), the shift circuit 10 according to the first embodiment or a modification thereof is used as the final transfer stage. It is possible to arrange the shift circuits 10A and 10B according to Examples 1 and 2.

(Application example 5)
FIG. 31 is a block diagram showing a configuration of a shift register circuit according to Application Example 5 of the present invention. As shown in FIG. 31, the shift register circuit 61E according to the fifth application example is formed by cascading 2N stages (even stages) of shift circuits 10C to 10E according to modifications 3 to 5 of the first embodiment. A power supply potential VSS is applied to the transfer stage instead of the end pulse ED, and a TRN circuit 62 is provided.

  The TRN circuit 62 uses the output pulse OUT of the 2N-th transfer stage as an input pulse IN, and also receives the input pulse PRIN of the 2N-1-th transfer stage as a control pulse CNT, and the control pulse CNT becomes a high potential VDD. In this case, the low potential VSS is output, and when the control pulse CNT is the low potential VSS, the input pulse IN, that is, the output pulse OUT of the 2N-th transfer stage is passed through. The output pulse OUT of the TRN circuit 62 is given as the input pulse NXIN to the 2N-1 transfer stage.

  When the power supply potential VSS is input instead of the end pulse ED to the final transfer stage, the control pulse NSW of the transfer stage including the shift circuits 10C to 10E according to the modified examples 3 to 5 of the first embodiment is once High. Once the potential is reached, each transfer stage functions as a level shift circuit until reset is applied. Therefore, the output o2N at the final stage has a waveform obtained by level shifting the clock pulse CK. Therefore, it is important to provide the TRN circuit 62 in order to generate a normal waveform as the 2N-1 stage control pulse NSW. Further, when the start pulse ST is used instead of the end pulse ED, the final stage can be reset every time ST = High (only the final stage is driven as a level shifter from o2n-1 = High to ST = High). In this case, the TRN circuit 62 is not necessary.

  32, the clock pulses CK, xCK, the start pulse ST, the first stage, the second stage, the 2N stage-1 control pulse NSW, and the output pulses (transfer pulses) o1, o2, o3,. The timing relationship of o2N-1 is shown.

  FIG. 33 is a circuit diagram showing an example of the configuration of the TRN circuit 62. FIG. 34 shows the timing relationship between the input pulse IN, the control pulse CNT, and the output pulse OUT.

  As shown in FIG. 33, the TRN circuit 62 according to this example is connected in series between the input terminal 621 and the power supply potential VSS, the gates are connected in common and the control terminal 622 is connected, and the drains are connected. Are commonly connected and connected to the output terminal 623, the PMOS transistor p51 and the NMOS transistor n51, the NMOS transistor n52 connected in parallel to the PMOS transistor p51, the control pulse CNT is inverted, and the NMOS transistor n52 And an inverter circuit 624 applied to the gate.

  As described above, in the shift register circuit 61E in which the shift circuits 10C to 10E according to the modifications 3 to 5 of the first embodiment are cascade-connected in 2N stages (even stages), the TRN circuit 62 is provided near the final transfer stage. In addition to providing the power supply potential VSS to the final transfer stage, there is an advantage that it is not necessary to externally supply the end pulse ED to the final transfer stage.

  Here, the case where the transfer stage is an even number has been described as an example. However, when the transfer stage is an odd number, the TRN circuit 62 is provided in the vicinity of the transfer stage of the final stage (2N-1 stages). By adopting a configuration in which the power supply potential VSS is applied to the final transfer stage, it is possible to obtain the same effect.

  Further, in the shift register circuits 61A to 61E according to the application examples described above, the transfer pulses o1, o2, o3,... Having no blanking period between the transfer pulses are generated. In the shift register circuit using the shift circuits 10C to 10E according to 3 to 5 as the transfer stage, that is, the shift register circuit 61B according to the application example 2 in FIG. 26 and the shift register circuit 61E according to the application example 5 in FIG. As shown in each timing chart of FIG. 36, a blanking period can be provided between transfer pulses by creating a blanking period at the timing of the clock pulses CK and xCK.

  Here, a Vin potential generation circuit that generates the constant voltage Vin used in the shift register circuits 61A to 61E according to the application examples 1 to 5 will be described.

  Although the constant potential Vin applied to each transfer stage of the shift register circuits 61A to 61E according to the application examples 1 to 5 may be an external input, the constant potential Vin is the high potential of the clock pulses CK and xCK. The constant voltage Vin can be generated by the Vin potential generation circuit 71 having the configuration.

  As shown in FIG. 37, the Vin potential generation circuit 71 includes a PMOS transistor p61 connected between a clock terminal 711 that receives a clock pulse CK and an output terminal 713, and a clock terminal 712 that receives a clock pulse xCK. And a PMOS transistor p62 connected between the output terminal 713 and the clock pulse xCK to the gate of the PMOS transistor p61 and the clock pulse CK to the gate of the PMOS transistor p62, respectively.

  The timing relationship between the clock pulses CK and xCK and the output OUT of the constant potential Vin is shown in FIG. FIG. 39 shows the timing relationship when a blanking period is provided for the clock pulses CK and xCK. When a blanking period is provided for the clock pulses CK and xCK, the constant potential Vin can be supplied outside the blanking period.

  As described above, in a shift register circuit in which a plurality of transfer stages (shift stages) are cascade-connected, as each transfer stage, a level shift unit 11 (11A, 11B, 11C) and a control pulse generator 12 (12A, 12A, By using the shift circuit 10 (10A, 10B, 10C, 10D, 10E) having a combination pattern with 12B1, 12B2, 12B3), no leakage current flows in the level shift unit 11 (11A, 11B, 11C). Since power consumption is low, power consumption of the shift register circuit can be reduced.

  The shift register circuits 61A to 61E according to the application examples 1 to 5 can be used as a general shift register circuit with a level shift function, and as an example, pixels including electro-optical elements are two-dimensionally arranged in a matrix. In a display device integrated with a drive circuit in which a peripheral drive circuit for driving the pixel array unit formed on the same substrate as the pixel array unit is used as a shift register circuit constituting a scanner for a vertical driver or a horizontal driver Can do.

(Application example)
FIG. 40 is a block diagram illustrating an example of a configuration of a display device according to an application example of the present invention. Here, an active matrix liquid crystal display device using a liquid crystal cell as an electro-optic element of a pixel will be described as an example of the display device.

  As shown in FIG. 40, an active matrix liquid crystal display device 80 according to this application example includes a pixel array unit 81, a vertical driver 82, a horizontal driver 83, and the like, and peripheral drive circuits such as the vertical driver 82 and the horizontal driver 83. Are integrally formed on the same liquid crystal panel 84 as the pixel array portion 81. The liquid crystal panel 84 has a configuration in which two insulating substrates, for example, glass substrates are arranged to face each other with a certain gap, and a liquid crystal material is sealed in the gap.

  In the pixel array unit 81, the pixels 90 are two-dimensionally arranged in m rows and n columns. Further, scanning lines 85-1 to 85 -m are wired for each row and signal lines 86-1 to 86 -n are wired for each column in the matrix-like arrangement of the pixels 90. The pixel 90 includes a TFT (Thin Film Transistor) 91 which is a pixel transistor, a liquid crystal cell 92 having a pixel electrode connected to the drain electrode of the TFT 91, and a storage capacitor having one electrode connected to the drain electrode of the TFT 91. 93.

  In this pixel structure, the TFT 91 of each pixel 90 has its gate electrode connected to the scanning line 85 (85-1 to 85-m) and its source electrode connected to the signal line 86 (86-1 to 86-n). Has been. The counter electrode of the liquid crystal cell 92 and the other electrode of the storage capacitor 93 are connected to a common line 87 to which a common voltage VCOM is applied.

  The vertical driver 82 includes a shift register circuit and the like, and selects each pixel 90 of the pixel array unit 81 in units of rows. The horizontal driver 83 includes a shift register circuit, a sampling switch, and the like, and sequentially applies video signals input from the outside of the panel to each pixel 90 in the row selected by the vertical driver 82 in units of pixels (dot sequential). Or, write in units of lines all at once (line sequential).

  In the active matrix liquid crystal display device 80 having the above-described configuration, the shift register circuits 61A to 61E according to the above-described application examples 1 to 5 are used as the shift register circuit constituting at least one of the vertical driver 82 and the horizontal driver 83.

  In this way, by using the shift register circuits 61A to 61E as the shift register circuits constituting the vertical driver 82 and the horizontal driver 83, the shift register circuits 61A to 61E have no leakage current and no current consumption as the transfer stages. Since the shift circuit 10 including the level shift unit 11 (11A, 11B, 11C) with a small amount is used, the consumption in the shift register circuits 61A to 61E is small, and as a result, the low consumption of the liquid crystal display device 80 is achieved. Electricity can be realized.

  In the application example described above, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as an electro-optical element of the pixel has been described as an example. For example, an EL display device using an EL (electro luminescence) element as an optical element, such as a vertical driver or a horizontal driver configured using a shift register circuit on the same substrate as the pixel array unit, Furthermore, the present invention is applicable to all devices equipped with a scanner configured using a shift register circuit.

  A display device typified by the liquid crystal display device according to the application example described above can be mounted and used as a screen display unit of a mobile device such as a mobile phone, a PDA (Personal Digital Assistants), and a notebook PC (Personal Computer).

1 is a circuit diagram showing a circuit configuration of a shift circuit according to a first embodiment of the present invention. 4 is a timing chart showing the level relationship and timing relationship of a clock pulse CK, an input pulse IN, a control pulse NSW, a negative phase control pulse PSW, and an output pulse OUT. FIG. 3 is a circuit diagram illustrating a configuration of a level shift unit according to the first embodiment. 3 is a timing chart for explaining the circuit operation of the level shift unit according to the first embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a level shift unit according to a second embodiment. 6 is a timing chart for explaining the circuit operation of the level shift unit according to the second embodiment. It is a block diagram which shows the circuit structure of the shift circuit which concerns on the modification 1 of 1st Embodiment. FIG. 9 is a circuit diagram illustrating a configuration of a level shift unit according to a third embodiment. 10 is a timing chart for explaining circuit operations of the level shift unit according to the third embodiment. It is a block diagram which shows the circuit structure of the shift circuit which concerns on the modification 2 of 1st Embodiment. FIG. 3 is a block diagram illustrating a configuration of a control pulse generator according to the first embodiment. 3 is a timing chart for explaining the circuit operation of the control pulse generator according to the first embodiment. It is a circuit diagram which shows an example of a structure of a NOR circuit. It is a circuit diagram which shows an example of a structure of an inverter circuit. FIG. 6 is a block diagram illustrating a configuration of a control pulse generator according to a second embodiment. 6 is a timing chart for explaining a circuit operation of a control pulse generator according to the second embodiment. FIG. 9 is a block diagram illustrating a configuration of a control pulse generator according to a third embodiment. 10 is a timing chart for explaining the circuit operation of the control pulse generator according to the third embodiment. FIG. 10 is a block diagram illustrating a configuration of a control pulse generator according to a fourth embodiment. It is a block diagram which shows the circuit structure of the shift circuit which concerns on the modification 3 of 1st Embodiment. It is a block diagram which shows the circuit structure of the shift circuit which concerns on the modification 4 of 1st Embodiment. It is a block diagram which shows the circuit structure of the shift circuit which concerns on the modification 5 of 1st Embodiment. 10 is a timing chart for explaining the circuit operation of a shift circuit according to modification examples 3, 4, and 5. It is a block diagram which shows the structure of the shift register circuit which concerns on the application example 1 of this invention. 12 is a timing chart for explaining the operation of the shift register circuit according to Application Example 1; It is a block diagram which shows the structure of the shift register circuit which concerns on the application example 2 of this invention. 10 is a timing chart for explaining the operation of the shift register circuit according to Application Example 2; It is a block diagram which shows the structure of the shift register circuit which concerns on the application example 3 of this invention. 12 is a timing chart for explaining the operation of the shift register circuit according to Application Example 3. It is a block diagram which shows the structure of the shift register circuit which concerns on the application example 4 of this invention. It is a block diagram which shows the structure of the shift register circuit which concerns on the application example 5 of this invention. 16 is a timing chart for explaining the operation of the shift register circuit according to Application Example 5. It is a circuit diagram which shows an example of a structure of a TRN circuit. 6 is a timing chart for explaining the operation of the TRN circuit. It is a timing chart (the 1) which shows the timing relationship in the case of providing a blanking period between transfer pulses. It is a timing chart (the 2) which shows the timing relationship in the case of providing a blanking period between transfer pulses. It is a circuit diagram which shows an example of a structure of Vin potential generation circuit. 6 is a timing chart (part 1) for explaining the operation of the Vin potential generation circuit. 6 is a timing chart (part 1) for explaining the operation of the Vin potential generation circuit. It is a block diagram which shows an example of a structure of the active matrix type liquid crystal display device which concerns on the application example of this invention. It is a circuit diagram which shows the prior art example of the shift circuit with a level shift function.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,10A-10E ... Shift circuit, 11, 11A-11C ... Level shift part, 12, 12A, 12B (12B1-12B3) ... Control pulse generation part, 21 ... Complementary circuit, 22-24, 31, 32 ... Switch Circuit 41... NOR circuit 42. Inverter circuit 43 and 53 reset circuit 51 switching circuit 52 latch circuit 59B 59B switch circuit

Claims (23)

Level shift means for shifting the level of the clock pulse from the first amplitude to the second amplitude when the control pulse is in an active state;
A shift circuit comprising control pulse generating means for generating the control pulse,
The level shift means includes
First and second transistors of opposite conductivity type connected in series between a first power supply potential and a second power supply potential;
A clock terminal to which the clock pulse is input;
A first switch means connected between the clock terminal and the gate of the first transistor and turned on when the control pulse is in an active state;
A second switch means connected between the second power supply potential and the gate of the second transistor and turned off when the control pulse is in an active state;
A shift circuit comprising: a capacitor connected between the clock terminal and the gate of the second transistor. The level shift means further includes third switch means connected between the second power supply potential and the gate of the first transistor, and turned off when the control pulse is in an active state. The shift circuit according to claim 1, wherein: The level shift means is connected between the clock terminal and the capacitive element, and when the control pulse is in an inactive state, the level shift means cuts off the electrical connection between the clock terminal and the capacitive element. The shift circuit according to claim 1, further comprising: The level shift means further includes means for fixing a potential of a connection node between the fourth switch means and the capacitive element to a constant potential when the control pulse is in an inactive state. The shift circuit described. The shift circuit according to claim 1, wherein the control pulse is in an active state for one cycle of the clock pulse. Level shift means for shifting the level of the clock pulse from the first amplitude to the second amplitude when the control pulse is in an active state;
A shift register circuit comprising a shift circuit having a control pulse generating means for generating the control pulse is cascaded in a plurality of stages,
The level shift means includes
First and second transistors of opposite conductivity type connected in series between a first power supply potential and a second power supply potential;
A clock terminal to which the clock pulse is input;
A first switch means connected between the clock terminal and the gate of the first transistor and turned on when the control pulse is in an active state;
A second switch means connected between the second power supply potential and the gate of the second transistor and turned off when the control pulse is in an active state;
A shift register circuit comprising: a capacitor connected between the clock terminal and the gate of the second transistor. The level shift means further includes third switch means connected between the second power supply potential and the gate of the first transistor, and turned off when the control pulse is in an active state. The shift register circuit according to claim 6. The level shift means is connected between the clock terminal and the capacitive element, and when the control pulse is in an inactive state, the level shift means cuts off the electrical connection between the clock terminal and the capacitive element. The shift register circuit according to claim 6, further comprising: a switch unit. The level shift means further includes means for fixing a potential of a connection node between the fourth switch means and the capacitive element to a constant potential when the control pulse is in an inactive state. The shift register circuit described. The shift register circuit according to claim 6, wherein the control pulse generation unit generates the control pulse based on an input of the shift circuit of the own stage and an output of the shift circuit of the own stage. 7. The shift register circuit according to claim 6, wherein the control pulse generation unit generates the control pulse based on an input of the shift circuit of the own stage and an output of the shift circuit of the next stage. Among the plurality of stages, the control pulse generating means in the shift circuit from the first stage to the stage one stage before the last stage is provided with an input of the shift circuit of the own stage and an output of the shift circuit of the next stage. Based on said control pulse,
The control pulse generating means in the shift circuit in the final stage generates the control pulse based on an input of the shift circuit in the own stage and an output of the shift circuit in the own stage. Shift register circuit. Of the plurality of stages, a power supply potential is input as an output of the shift circuit in the next stage to the control pulse generating means in the shift circuit in the final stage,
The power supply potential is output when the output of the shift circuit in the stage immediately preceding the final stage is in an active state, the output of the shift circuit in the final stage is in the inactive state, and the shift of the stage immediately before the final stage is performed. The shift register circuit according to claim 11, further comprising means for supplying to the circuit. Each of the shift circuits performs a shift operation based on clock pulses of opposite phases with the constant potential as a high level side potential,
The shift register circuit according to claim 9, further comprising means for generating the constant potential based on the clock pulses having opposite phases to each other. A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix, a vertical driving unit that selects each pixel of the pixel array unit in units of rows, and an image in a row selected by the vertical driving unit A display device comprising a horizontal drive means for writing signals, wherein at least one of the vertical drive means and the horizontal drive means is constituted by a shift register circuit,
The shift register circuit includes:
Level shift means for shifting the level of the clock pulse from the first amplitude to the second amplitude when the control pulse is in an active state;
A shift circuit having a control pulse generating means for generating the control pulse is cascaded in a plurality of stages,
The level shift means includes
First and second transistors of opposite conductivity type connected in series between a first power supply potential and a second power supply potential;
A clock terminal to which the clock pulse is input;
A first switch means connected between the clock terminal and the gate of the first transistor and turned on when the control pulse is in an active state;
A second switch means connected between the second power supply potential and the gate of the second transistor and turned off when the control pulse is in an active state;
A display device comprising: a capacitor connected between the clock terminal and a gate of the second transistor. The level shift means further includes third switch means connected between the second power supply potential and the gate of the first transistor, and turned off when the control pulse is in an active state. The display device according to claim 15, characterized in that: The level shift means is connected between the clock terminal and the capacitive element, and when the control pulse is in an inactive state, the level shift means cuts off the electrical connection between the clock terminal and the capacitive element. The display device according to claim 15, further comprising: a switching unit. The level shift means further includes means for fixing a potential of a connection node between the fourth switch means and the capacitive element to a constant potential when the control pulse is in an inactive state. The display device described. The display device according to claim 15, wherein the control pulse generating unit generates the control pulse based on an input of the shift circuit of the own stage and an output of the shift circuit of the own stage. The display device according to claim 15, wherein the control pulse generating unit generates the control pulse based on an input of the shift circuit of the own stage and an output of the shift circuit of the next stage. Among the plurality of stages, the control pulse generating means in the shift circuit from the first stage to the stage one stage before the last stage is provided with an input of the shift circuit of the own stage and an output of the shift circuit of the next stage. Based on said control pulse,
The control pulse generation means in the shift circuit in the final stage generates the control pulse based on an input of the shift circuit in the own stage and an output of the shift circuit in the own stage. Display device. Of the plurality of stages, a power supply potential is input as an output of the shift circuit in the next stage to the control pulse generating means in the shift circuit in the final stage,
The power supply potential is output when the output of the shift circuit in the stage immediately preceding the final stage is in an active state, the output of the shift circuit in the final stage is in the inactive state, and the shift of the stage immediately before the final stage is performed. 21. The display device according to claim 20, further comprising means for providing the circuit. Each of the shift circuits performs a shift operation based on clock pulses of opposite phases with the constant potential as a high level side potential,
The display device according to claim 18, further comprising means for generating the constant potential based on the clock pulses having opposite phases to each other.

Images