KR20140031760A - Data processing device, method thereof, and apparatuses having the same - Google Patents

Abstract

Disclosed are a method of muxing data by using clock signals having different timings, and an apparatus for performing the method. By the method, the storage and muxing or sorting of the data are carried out at the same time. The apparatus includes a first latch circuit which responds a non-overlapping latch control signal and arranges in parallel data blocks which are inputted in series, and a second latch circuit which responds a clock signal and latches at the same time data blocks which are arranged in parallel.

Description

DATA PROCESSING DEVICE, METHOD THEREOF, AND APPARATUSES HAVING THE SAME}

Embodiments of the inventive concept relate to a data processing apparatus. In particular, a data processing apparatus capable of muxing data using clock signals having different timings, a method of operating the same, and a data processing apparatus may be described. It relates to devices that include.

The source driver (or data line driver) converts digital signals corresponding to image data to be displayed into analog signals and supplies the converted analog signals to pixels of the display panel. Thus, the image data may be displayed on the display panel.

In order to prevent performance deterioration of liquid crystal displays (LCDs), for example, crosstalk or flicker, a typical source driver inverts the polarity of an analog signal supplied to a pixel from frame to frame. Let's do it. This is called polarity inversion driving.

The polarity inversion driving method includes a frame inversion method, a column inversion method, a line inversion method, and a dot inversion method.

In the screen inversion method, the polarities of analog signals supplied to pixels in one frame are the same. In the column inversion scheme, polarities of analog signals supplied to pixels in adjacent columns are different from each other. In the row inversion method, polarities of analog signals supplied to pixels in adjacent rows are different from each other.

In the point inversion method, polarities of analog signals supplied to adjacent pixels having different polarities of analog signals supplied to adjacent pixels are the same as those of n (n is a natural number greater than 1) pixels adjacent to each other. The polarities of the analog signals supplied to the n pixels and the polarities of the analog signals supplied to the pixels adjacent to the n pixels have different n-DOT inversion schemes.

Among the polarity inversion driving methods, the point inversion method is the most resistant to the image cross-talk phenomenon, so it is widely used in a large display and a mobile display.

The source driver includes a digital-to-analog conversion circuit including a digital-to-analog converter (or anode decoder) and a digital-to-analog converter (or cathode decoder) of the cathode to implement the point inversion scheme.

In conventional source drivers, adjacent channels share a digital-to-analog conversion circuit to reduce circuit complexity and chip size. Specifically, a conventional source driver converts digital signals, i.e., data, to each other between adjacent channels in response to a polarity control signal, converts each of the exchanged data into analog signals, and exchanges analog signals back to each other for digital-to-analog conversion. Circuit complexity and chip size can be reduced.

The conventional source driver must include a multiplexer equal to the number of channels in order to implement the above operation, so that the overall circuit complexity and chip size are large.

SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to reduce the complexity of a circuit and the size of a chip by processing data, for example, by muxing data using non-overlapping latch control signals or clock signals having different timings. A data processing device, a method of operating the same, and devices including the same are provided.

The data processing apparatus includes a first latch circuit for parallelly arranging data blocks input in series in response to non-overlapping latch control signals, and a second latch for simultaneously latching data blocks aligned in parallel in response to a clock signal. It includes a circuit.

The data processing apparatus further includes a latch control circuit that generates the non-overlapping latch control signals sequentially in response to a selection signal.

The latch control circuit includes a plurality of multiplexers, each outputting any one of a plurality of latch clock signals as one of the plurality of latch control signals in response to the selection signal.

Each of the plurality of multiplexers alternately outputs the plurality of latch clock signals as the one latch control signal.

The data processing apparatus further includes a control circuit for generating the selection signal based on the polarity control signal and the inversion mode control signal.

The data processing apparatus includes a digital-analog conversion circuit for converting output signals of the second latch circuit into analog signals, a multiplexing circuit for rearranging the analog signals in response to the selection signal, and the rearranged analog signals. And an output buffer circuit for buffering and outputting.

A display apparatus according to an embodiment of the present invention includes the data processing apparatus and a display panel displaying output signals of the data processing apparatus in response to a gating signal output from a gate driver.

According to an embodiment of the present invention, a data processing method includes: arranging data blocks input in series in parallel in response to non-overlapping latch control signals, and simultaneously latching data blocks aligned in parallel in response to a clock signal. It includes a step.

The method further includes sequentially generating the non-overlapping latch control signals in response to a select signal.

Generating the latch control signals sequentially includes alternately outputting a plurality of latch clock signals as one of the latch control signals in response to the selection signal.

The data processing apparatus and its operation method according to an embodiment of the present invention have an effect of reducing the complexity of a circuit and the size of a chip by using non-overlapping latch control signals.

The data processing apparatus and its operation method according to an exemplary embodiment of the present invention may mux data using non-overlapping latch control signals or clock signals having different timings (or phases). At this time, the storage and muxing (or classification) of the data is performed at the same time.

The data processing apparatus according to the embodiment of the present invention may reduce the number of data lines and increase the speed of data transmitted through the data lines.

The data processing apparatus according to the embodiment of the present invention has an effect of reducing the number of multiplexers.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more fully understand the drawings recited in the detailed description of the present invention, a detailed description of each drawing is provided.
1 is a schematic block diagram of a source driver according to an exemplary embodiment of the present invention.
FIG. 2 is a schematic block diagram of the data latch circuit shown in FIG. 1.
3 is a circuit diagram illustrating an example of a data latch circuit shown in FIG. 2.
FIG. 4 is a timing diagram for describing an operation of the data latch circuit shown in FIG. 3.
FIG. 5 is a circuit diagram illustrating an example embodiment of a latch control circuit illustrated in FIG. 2.
FIG. 6 is a circuit diagram illustrating an example embodiment of a data latch block shown in FIG. 2.
FIG. 7 is a timing diagram for describing an exemplary operation of the data latch circuit shown in FIG. 6.
FIG. 8 is a timing diagram for explaining another embodiment of the operation of the data latch circuit shown in FIG. 6.
FIG. 9 is a circuit diagram illustrating another embodiment of the data latch block shown in FIG. 2.
FIG. 10 is a circuit diagram illustrating another embodiment of the data latch circuit shown in FIG. 2.
FIG. 11 is a timing diagram for describing an operation of the data latch circuit shown in FIG. 9.
12 is a circuit diagram illustrating another embodiment of the latch control circuit shown in FIG. 2.
FIG. 13 is a circuit diagram illustrating still another embodiment of the data latch block shown in FIG. 2.
FIG. 14 is a timing diagram for describing an exemplary operation of the data latch block shown in FIG. 13.
FIG. 15 is a timing diagram for describing another exemplary operation of the data latch block shown in FIG. 13.
FIG. 16 is a circuit diagram illustrating still another embodiment of the data latch circuit shown in FIG. 2.
FIG. 17 is a schematic block diagram of a display module including the source driver shown in FIG. 1.
FIG. 18 is a schematic block diagram of an electronic system and interface including the source driver shown in FIG. 1.

It is to be understood that the specific structural or functional description of embodiments of the present invention disclosed herein is for illustrative purposes only and is not intended to limit the scope of the inventive concept But may be embodied in many different forms and is not limited to the embodiments set forth herein.

The embodiments according to the concept of the present invention can make various changes and can take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. It should be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms disclosed, but includes all modifications, equivalents, or alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms may be named for the purpose of distinguishing one element from another, for example, without departing from the scope of the right according to the concept of the present invention, the first element may be referred to as a second element, The component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the terms "comprises" or "having" and the like are used to specify that there are features, numbers, steps, operations, elements, parts or combinations thereof described herein, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings attached hereto.

Embodiments according to the inventive concept, that is, a method of muxing input data using clock signals having different timings or phases may be used in various data processing apparatuses or data processing circuits. In the present specification, for convenience of description, the source driver will be described as an example of a data processing device, but the technical spirit of the present invention is not limited thereto.

1 is a schematic block diagram of a source driver according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a data processing apparatus such as a source driver 1010 may include a shift register 1100, a control circuit 1200, a data latch circuit 1300, a digital-to-analog conversion circuit 1400, and a multiplexing circuit 1500. And an output buffer circuit 1600.

The shift register 1100 may sequentially output the plurality of latch clock signals LCLK to the data latch circuit 1300 in response to the start signal SE for starting the operation of the source driver 1010. The plurality of latch clock signals LCLK have different timings or phases as non-overlapping signals. Therefore, the data processing apparatus 1010 may have an effect of temporally muxing the input data by using the plurality of latch clock signals LCLK or signals having different timings.

The control circuit 1200 may output at least one selection signal SEL based on the polarity control signal POL and the inversion mode control signal DOT.

The polarity control signal POL may be a signal converted for each frame. For example, when the polarity control signal POL is high level in the current frame, it may be low level in the next frame.

The inversion mode control signal DOT is a signal for controlling the inversion method of the display panel. When the inversion mode control signal DOT indicates an n-DOT (n is a natural number) inversion scheme, the control circuit 1200 may include at least one selection signal SEL such that the source driver 1010 operates in an n-DOT inversion scheme. ) Can be created.

For example, when the inversion mode control signal DOT indicates a 1-DOT inversion scheme, the control circuit 1200 may determine that the source driver 1010 is a 1-DOT inversion scheme, that is, the analog signals supplied to adjacent pixels. At least one selection signal SEL may be generated such that polarities operate differently.

For another example, when the inversion mode control signal DOT indicates an n-DOT inversion scheme, the control circuit 1200 supplies the source driver 1010 in an n-DOT inversion scheme, that is, to n adjacent pixels. The polarities of the analog signals are the same, and the polarities of the analog signals supplied to the n pixels and the polarities of the analog signals supplied to the other n pixels adjacent to the n pixels are different from each other. The selection signal SEL may be generated.

The data latch circuit 1300 arranges the data blocks DATA input in series in parallel in response to the plurality of latch clock signals LCLK, the clock signal CLK, and the at least one selection signal SEL. Latch data blocks arranged in parallel.

The data latch circuit 1300 generates a plurality of latch clock signals LCLK as a plurality of latch control signals (LCS of FIG. 2 or 4) in response to the selection signal SEL, and generates the plurality of latch controls. The data blocks DATA input in series in response to the signals LCS may be arranged in parallel, and the data blocks DATA arranged in parallel in response to the clock signal CLK may be simultaneously latched.

The operation of the data latch circuit 1300 will be described in detail with reference to FIGS. 2 through 16.

The digital-analog conversion circuit 1400 converts output signals of the data latch circuit 1300 into analog signals.

According to an embodiment, the digital-to-analog conversion circuit 1400 may include a plurality of positive digital-to-analog converters (or positive decoders) and a plurality of negative digital-to-analog converters ( Or negative decoders).

Each of the plurality of positive digital-to-analog converters converts a corresponding one of the output signals of the data latch circuit 1300 into a positive analog signal, and each of the plurality of negative digital-to-analog converters includes a data latch. The other corresponding one of the output signals of the circuit 1300 may be converted into a negative analog signal.

In the present specification, for convenience of description, polarities of analog signals are divided into positive and negative portions, but the concept of the present invention is not limited thereto. That is, in the present specification, positive may mean a voltage higher than a reference voltage, and negative may mean a voltage lower than the reference voltage.

The multiplexing circuit 1500 may rearrange the output signals of the digital-to-analog conversion circuit 1400 in response to the at least one selection signal SEL. That is, the multiplexing circuit 1500 may rearrange the analog signals such that the analog signals are output to corresponding pixels in response to at least one selection signal SEL.

The output buffer circuit 1600 may buffer the output signals of the multiplexing circuit 1500 and output them to the pixels of the display panel. According to an embodiment, the output buffer circuit 1600 may include a plurality of amplifiers.

In response to the gating signal output from the gate driver 1050 of FIG. 17, output signals of the output buffer circuit 1600 may be supplied to pixels so that an image may be output to the display.

According to an embodiment, the shift register 1100, the control circuit 1200, the data latch circuit 1300, the digital-to-analog conversion circuit 1400, the multiplexing circuit 1500, and the output buffer circuit 1600 are one chip. It may be implemented as or as a separate independent chip.

FIG. 2 is a schematic block diagram of the data latch circuit shown in FIG. 1.

1 and 2, the data latch circuit 1300 may include a latch control circuit 1310 and a data latch block 1330.

The latch control circuit 1310 may output the plurality of latch clock signals LCLK as the plurality of latch control signals LCS in response to the at least one selection signal SEL.

For example, the latch control circuit 1310 outputs any one of the plurality of latch clock signals LCLK as one of the plurality of latch control signals LCS in response to the at least one selection signal SEL. Multiplexers (1311 and 1312 of FIG. 3, 1313 to 1316 of FIG. 10, or 1317 to 1319 of FIG. 16).

The data latch block 1330 arranges the data blocks DATA input in series in parallel in response to the plurality of latch control signals LCS output from the latch control circuit 1310 and to the clock signal CLK. In response, the data blocks DATA arranged in parallel may be simultaneously latched.

The data latch block 1330 may include a first latch circuit 1350 and a second latch circuit 1370.

The first latch circuit 1350 arranges the data blocks DATA input in series in parallel in response to the plurality of latch control signals LCS output from the latch control circuit 1310.

The second latch circuit 1370 may simultaneously latch the output signals of the first latch circuit 1350, that is, the data blocks DATA arranged in parallel, in response to the clock signal CLK.

3 is a circuit diagram illustrating an example of a data latch circuit shown in FIG. 2, and FIG. 4 is a timing diagram for describing an operation of the data latch circuit shown in FIG. 3.

1 to 4, the data latch circuit 1300-1 according to an embodiment of the data latch circuit 1300 may include a latch control circuit 1310-1 and a data latch block 1330-1. Can be. The data latch block 1330-1 may include a first latch circuit 1350-1 and a second latch circuit 1370-1.

The latch control circuit 1310-1 may include a plurality of multiplexers 1311 and 1312, the first latch circuit 1350-1 may include a plurality of data latches 1351 and 1352, The second latch circuit 1370-1 may include a plurality of data latches 1372 and 1372.

The multiplexer 1311 may output any one of the plurality of latch clock signals LCLK1 and LCLK2 to the data latch 1351 as the latch control signal LCS1 in response to the selection signal SEL, and the multiplexer 1312. In response to the selection signal SEL, another one of the plurality of latch clock signals LCLK1 and LCLK2 may be output as the latch control signal LCS2 to the data latch 1352. That is, each of the multiplexers 1311 and 1312 may output different latch clock signals.

As shown in FIG. 4, when the selection signal SEL is at the high level, the multiplexer 1311 outputs the latch clock signal LCLK1 as the latch control signal LCS1 and the multiplexer 1312 outputs the latch clock signal LCLK2. ) Can be output as the latch control signal LCS2.

In contrast, when the select signal SEL is at the low level, the multiplexer 1311 outputs the latch clock signal LCLK2 as the latch control signal LCS1 and the multiplexer 1312 outputs the latch clock signal LCLK1 to the latch control signal ( LCS2).

Since the plurality of latch clock signals LCLK1 and LCLK2 are non-overlapping signals or signals having different timings, the plurality of latch control signals LCS1 and LCS2 may also have non-overlapping or different timings. Signals may have.

The data latch 1351 may receive a data block input when the latch control signal LCS1 is activated among the data blocks DATA input in series in response to the latch control signal LCS1 output from the multiplexer 1311. It can be latched.

In response to the latch control signal LCS2 output from the multiplexer 1312, the data latch 1352 receives a data block input when the latch control signal LCS2 is activated among the data blocks DATA that are serially input. It can be latched.

As shown in Fig. 4, the data latch 1351 can latch the data block Y1-1 or Y2-2 which is input when the latch control signal LCS1 is activated, and the data latch 1352 corresponds. When the latch control signal LCS2 is activated, the input data block Y2-1 or Y1-2 may be latched. D1351 is an output signal of the data latch 1351, and D1352 is an output signal of the data latch 1352.

The data latch 1371 latches the data block D1351 output from the data latch 1351 in response to the clock signal CLK. The data latch 1372 may latch the data block D1352 output from the data latch 1352 in response to the clock signal CLK. That is, each data latch 1371 and 1372 can latch the output signals D1351 and D1352 of each data latch 1351 and 1352 at the same time.

As shown in FIG. 4, the data latch 1372 may latch the data block D1351 = Y1-1 or D1351 = Y2-2 output from the data latch 1351 in response to the clock signal CLK. Can be. The data latch 1372 may latch the data block D1352 = Y2-1 or D1352 = Y1-2 output from the data latch 1352 in response to the clock signal CLK.

5 is a circuit diagram illustrating an embodiment of the latch control circuit shown in FIG. 2, FIG. 6 is a circuit diagram illustrating an embodiment of the data latch block shown in FIG. 2, and FIG. 7 is a data latch shown in FIG. 6. FIG. 8 is a timing diagram illustrating an operation of a circuit, and FIG. 8 is a timing diagram illustrating another embodiment of the operation of the data latch circuit shown in FIG. 6.

1, 2, and 5 to 8, the latch control circuit 1310-2 according to the embodiment of the latch control circuit 1310 of FIG. 2 includes a plurality of multiplexers 1311A, 1312A, 1311B, And 1312B). The data latch block 1330-2A may include a first latch circuit 1350-2A and a second latch circuit 1370-2A.

The first latch circuit 1350-2A may include data latches 1351A to 1351F and 1352A to 1352F. The second latch circuit 1370-2A may include data latches 1372A to 1372F and 1372A to 1372F.

5 illustrates a data latch circuit 1300 for outputting a plurality of data blocks input through a bus having a 6-bit width through 12 channels, but the concept of the present invention is not limited thereto.

The function and operation of each of the multiplexers 1311A and 1311B of FIG. 5 and the function and operation of the multiplexer 1311 of FIG. 3 are the same or similar, and the function and operation of each of the multiplexers 1312A and 1312B and the multiplexer of FIG. 3. The function and operation of 1312 are the same or similar.

The multiplexer 1311A outputs any one of the plurality of latch clock signals LCLK1 and LCLK2 as the latch control signal LCS1 in response to the selection signal SEL1, and the multiplexer 1312A responds to the selection signal SEL1. The other one of the plurality of latch clock signals LCLK1 and LCLK2 may be output as the latch control signal LCS2.

As shown in FIG. 7, when the selection signal SEL1 is at the high level, the multiplexer 1311A outputs the latch clock signal LCLK1 as the latch control signal LCS1 and the multiplexer 1312A outputs the latch clock signal LCLK2. ) Can be output as the latch control signal LCS2.

In contrast, when the select signal SEL1 is at the low level, the multiplexer 1311A outputs the latch clock signal LCLK2 as the latch control signal LCS1 and the multiplexer 1312A outputs the latch clock signal LCLK1 to the latch control signal ( LCS2).

The multiplexer 1311B outputs any one of the plurality of latch clock signals LCLK1 and LCLK2 as the latch control signal LCS3 in response to the selection signal SEL2, and the multiplexer 1312B responds to the selection signal SEL2. The other one of the plurality of latch clock signals LCLK1 and LCLK2 may be output as the latch control signal LCS4.

As shown in Fig. 7, when the select signal SEL2 is at the high level, the multiplexer 1311B outputs the latch clock signal LCLK1 as the latch control signal LCS3 and the multiplexer 1312B outputs the latch clock signal LCLK2. ) Can be output as the latch control signal LCS4.

On the contrary, when the selection signal SEL2 is at the low level, the multiplexer 1311B outputs the latch clock signal LCLK2 as the latch control signal LCS3 and the multiplexer 1312B outputs the latch clock signal LCLK1 to the latch control signal ( LCS4).

The function and operation of each of the data latches 1351A to 1351F of FIG. 6 are similar to the function and operation of the data latch 1351 of FIG. 3, and the function and operation of each of the data latches 1353A to 1353F of FIG. Similar to the function and operation of data latch 1352 of FIG.

Data latches 1351A and 1352A, data latches 1351B and 1352B, data latches 1351C and 1352C, data latches 1351D and 1352D, data latches 1351E and 1352E, and data latches ( Each of 1351F and 1352F may receive data blocks DATA1 to DATA6 that are serially input through the same bus.

Each of the data latches 1351A through 1351F and 1352A through 1352F may latch a data block input when the corresponding latch control signals LCS1 through LCS6 are activated.

For example, the data latch 1351A may latch the data block Y1-1 or Y12-2 input when the corresponding latch control signal LCS1 is activated, and the data latch 1351B may correspond to the corresponding latch. When the control signal LCS2 is activated, the data block Y12-1 or Y1-2 may be latched.

The functions and operations of each of the data latches 1372A to 1372F of FIG. 6 are similar to those of the data latches 1137 of FIG. 3, and the functions and operations of the data latches 1372A to 1372F of FIG. The function and operation of the data latch 1372 of FIG. 3 are similar.

Each of the plurality of data latches 1372A to 1372F and 1372A to 1372F latches the data block output from the corresponding data latches 1351A to 1351F and 1352A to 1352F in response to the clock signal CLK. can do.

For example, the data latch 1371A may latch the data block Y1-1 or Y12-2 output from the data latch 1351A in response to the clock signal CLK. The data latch 1372A may latch the data block Y12-1 or Y1-2 output from the data latch 1352A in response to the clock signal CLK.

The data block latched by the plurality of data latches 1372A to 1372F and 1372A to 1372F may be output to the digital-to-analog conversion circuit 1400.

When the control circuit 1200 generates the selection signals SEL1 and SEL2 as shown in FIG. 7, the source driver 1010 performs a 1-DOT inversion scheme, eg, polarities of analog signals supplied to adjacent pixels. This can work differently.

On the other hand, when the control circuit 1200 generates the selection signals SEL1 and SEL2 as shown in FIG. 8, the source driver 1010 is supplied to six adjacent pixels in a 6-DOT inversion scheme, for example. The polarities of the analog signals are the same, and the polarities of the analog signals supplied to the six pixels and the polarities of the analog signals supplied to the other six pixels adjacent to the six pixels may operate differently.

FIG. 9 is a circuit diagram illustrating another embodiment of the data latch block shown in FIG. 2.

1, 2, 5, and 7 through 9, the data latch block 1330-2B may include a first latch circuit 1350-2B and a second latch circuit 1370-2B. Can be.

The first latch circuit 1350-2B may include data latches 1351A to 1351F and 1352A to 1352F. The second latch circuit 1370-2B may include data latches 1372A to 1372F and 1372A to 1372F.

Functions and operations of the plurality of data latches 1351A to 1351F, 1352A to 1352F, 1371A to 1372F, and 1372A to 1372F of FIG. 9, and the plurality of data latches 1351A to 1351F, 1352A to 1352F, and 1371A of FIG. The functions and operations of ˜1371F and 1372A to 1372F are substantially the same except for the input path of the plurality of latch control signals LCS1 to LCS4.

Each of the data latches 1351A, 1351D, and 1352E latches a data block that is input when the latch control signal LCS1 is activated.

Each of the data latches 1352E, 1352A, and 1351E latches a data block that is input when the latch control signal LCS2 is activated.

Each of the data latches 1351B, 1352C, and 1352F latches a data block that is input when the latch control signal LCS3 is activated. Each of the data latches 1351C, 1351F, and 1352B may latch a data block input when the latch control signal LCS4 is activated.

For example, the data latch 1351A may latch the data block Y1-1 or Y12-2 input when the corresponding latch control signal LCS1 is activated, and the data latch 1351B may correspond to the corresponding latch. When the control signal LCS3 is activated, the data block Y12-1 or Y1-2 may be latched.

When the control circuit 1200 generates the selection signals SEL1 and SEL2 as shown in FIG. 7, the source driver 1010 is a 2-DOT inversion scheme, for example, an analog signal supplied to two adjacent pixels. Polarities of the two signals are the same, and the polarities of the analog signals supplied to the two pixels and the polarities of the analog signals supplied to the other two pixels adjacent to the two pixels may operate differently.

On the other hand, when the control circuit 1200 generates the selection signals SEL1 and SEL2 as shown in FIG. 8, the source driver 1010 is supplied to, for example, three adjacent pixels in a 3-DOT inversion scheme. The polarities of the analog signals are the same, and the polarities of the analog signals supplied to the three pixels and the polarities of the analog signals supplied to the other three pixels adjacent to the three pixels may operate differently.

FIG. 10 is a circuit diagram illustrating another embodiment of the data latch circuit shown in FIG. 2, and FIG. 11 is a timing diagram for describing an operation of the data latch circuit shown in FIG. 9.

1, 2, 10, and 11, the data latch circuit 1300-3 may include a latch control circuit 1310-3 and a data latch block 1330-3. The data latch block 1330-3 may include a first latch circuit 1350-3 and a second latch circuit 1370-3.

The latch control circuit 1310-3 may include a plurality of multiplexers 1313-1316, the first latch circuit 1350-3 may include a plurality of data latches 1353-1356, The second latch circuit 1370-3 may include a plurality of data latches 1373 to 1376.

Each of the multiplexers 1313 to 1316 may output one of the plurality of latch clock signals LCLK1 to LCLK4 as the latch control signals LCS1 to LCS4 in response to the selection signal SEL.

For example, the multiplexer 1313 may output one of the plurality of latch clock signals LCLK1 and LCLK4 to the data latch 1353 as the latch control signal LCS1 in response to the selection signal SEL. The multiplexer 1314 may output another one of the plurality of latch clock signals LCLK1 and LCLK4 to the data latch 1354 as the latch control signal LCS2 in response to the selection signal SEL.

The multiplexer 1315 may output any one of the plurality of latch clock signals LCLK2 and LCLK3 to the data latch 1355 as the latch control signal LCS3 in response to the selection signal SEL. The multiplexer 1316 may output another one of the plurality of latch clock signals LCLK2 and LCLK3 to the data latch 1356 as the latch control signal LCS4 in response to the selection signal SEL.

That is, each of the multiplexers 1313 to 1316 may output any one of the different latch clock signals as the latch control signal.

As shown in FIG. 11, when the selection signal SEL is at the high level, the multiplexer 1314 outputs the latch clock signal LCLK1 as the latch control signal LCS1 and the multiplexer 1315 outputs the latch clock signal LCLK4. ) Is output as the latch control signal LCS2 and the multiplexer 1316 outputs the latch clock signal LCLK2 as the latch control signal LCS3 and the multiplexer 1317 outputs the latch clock signal LCLK3 to the latch control signal LCS4. Can be output as

In contrast, when the selection signal SEL is at the low level, the multiplexer 1314 outputs the latch clock signal LCLK4 as the latch control signal LCS1 and the multiplexer 1315 outputs the latch clock signal LCLK1 to the latch control signal ( LCS2) and the multiplexer 1316 can output the latch clock signal LCLK3 as the latch control signal LCS3 and the multiplexer 1317 can output the latch clock signal LLK2 as the latch control signal LCS4.

Since the latch clock signals LCLK1 to LLK4 are non-overlapping signals, the latch control signals LCS1 to LCS4 may also be non-overlapping signals.

Each of the data latches 1353 to 1536 may latch a data block DATA input through a bus when the latch control signals LCS1 to LCS4 output from the corresponding multiplexers 1314 to 1317 are activated.

As shown in FIG. 11, the data latch 1353 may latch the data block Y1-1 or Y4-2 input when the corresponding latch control signal LCS1 is activated, and the data latch 1354. May latch a data block Y4-1 or Y1-2 that is input when the corresponding latch control signal LCS2 is activated, and the data latch 1355 is activated when the corresponding latch control signal LCS3 is activated. The data block Y2-1 or Y3-2 to be input may be latched, and the data latch 1356 is input to the data block Y3-1 or Y2-2 which is input when the corresponding latch control signal LCS4 is activated. Can be latched.

Each data latch 1373 to 1376 may latch a data block output from each of the data latches 1353 to 1356 corresponding to the clock signal CLK.

As shown in FIG. 11, the data latch 1373 may latch the data block Y1-1 or Y4-2 output from the data latch 1353 in response to the clock signal CLK and the data latch 1374. ) May latch the data block Y4-1 or Y1-2 output from the data latch 1354 in response to the clock signal CLK, and the data latch 1375 may latch the data in response to the clock signal CLK. The data block Y2-1 or Y3-2 output from the 1355 can be latched and the data latch 1376 outputs the data block Y3-1 output from the data latch 1356 in response to the clock signal CLK. Or Y2-2).

Each of the signals D1353 to D1356 and D1373 to D1376 means an output signal of each of the latches 1353 to 1356 and 1373 to 1376.

12 is a circuit diagram illustrating another embodiment of the latch control circuit shown in FIG. 2, FIG. 13 is a circuit diagram illustrating another embodiment of the data latch block shown in FIG. 2, and FIG. 14 is a data diagram shown in FIG. 13. FIG. 15 is a timing diagram for describing an exemplary operation of the latch block, and FIG. 15 is a timing diagram for describing another exemplary operation of the data latch block illustrated in FIG. 13.

1, 2, and 12 to 15, the latch control circuit 1310-4 may include a plurality of multiplexers 1313A to 1316A and 1313B to 1316B. The data latch block 1330-4 of FIG. 13 may include a first latch circuit 1350-4 and a second latch circuit 1370-4. The first latch circuit 1350-4 may include a plurality of data latches 1353A to 1356A, 1353B to 1356B, and 1353C to 1356C, and the second latch circuit 1370-4 may include a plurality of data latches. (1373A-1376A, 1373B-1376B, and 1373C-1376C).

FIG. 13 exemplarily illustrates a data latch circuit including a data latch block 1330-4 outputting a plurality of data blocks input through a bus having a 3-bit width through 12 channels. The concept of the present invention is not limited to this.

The function and operation of the multiplexers 1313A and 1313B of FIG. 12 and the function and operation of the multiplexer 1313 of FIG. 10 are the same or similar, and the function and operation of each of the multiplexers 1314A and 1314B and the multiplexer of FIG. 10. The function and operation of 1314 are the same or similar, and the function and operation of the multiplexers 1315A and 1315B and the function and operation of the multiplexer 1315 of FIG. 10 are the same or similar, and the multiplexers 1316A and 1316B. Each function and operation and the function and operation of the multiplexer 1316 of FIG. 10 are the same or similar.

Each of the multiplexers 1313A to 1316A and 1313B to 1316B of FIG. 12 receives a plurality of latch clock signals LCLK1 to LCLK4 in response to a corresponding selection signal SEL1 or SEL2. Can be output as

As shown in Figs. 14 and 15, when the selection signal SEL1 is at a high level, the multiplexer 1313A outputs the latch clock signal LCLK1 as the latch control signal LCS1 and the multiplexer 1314A is the latch clock. The signal LCLK4 can be output as the latch control signal LCS2, the multiplexer 1315A outputs the latch clock signal LCLK2 as the latch control signal LCS7, and the multiplexer 1316A outputs the latch clock signal LCLK3. It can output as a latch control signal LCS8.

In contrast, when the selection signal SEL1 is at the low level, the multiplexer 1313A outputs the latch clock signal LCLK4 as the latch control signal LCS1 and the multiplexer 1314A outputs the latch clock signal LCLK1 to the latch control signal ( LCS2), the multiplexer 1315A outputs the latch clock signal LCLK3 as the latch control signal LCS7, and the multiplexer 1316A outputs the latch clock signal LCLK2 as the latch control signal LCS8. Can be.

Since the functions and operations of the multiplexers 1313A to 1316A and the functions and operations of the multiplexers 1313B to 1316B are complementary to each other, a description thereof will be omitted.

The functions and operations of the data latches 1353A to 1353C of FIG. 13 are similar to those of the data latches 1353 of FIG. 10, and the functions and operations of the data latches 1354A to 1354C of FIG. 13. The functions and operations of the data latch 1354 of FIG. 10 are similar, and the functions and operations of each of the data latches 1355A to 1355C of FIG. 13 are similar to those of the data latch 1355 of FIG.

Data latches 1353A, 1354A, 1355A, and 1356A, data latches 1353B, 1354B, 1355B, and 1356B, and data latches 1353C, 1354C, 1355C, and 1356C, respectively, are in series through the same bus. The input data blocks DATA1 to DATA3 may be received.

Each of the data latches 1353A to 1356A, 1353B to 1356B, and 1353C to 1356C may latch a data block input when the corresponding latch control signals LCS1 to LCS8 are activated.

For example, the data latch 1353A may latch the data block Y1-1 or Y12-2 input when the corresponding latch control signal LCS1 is activated, and the data latch 1353B may correspond to the corresponding latch. The data block Y2-1 or Y11-2 input when the control signal LCS3 is activated may be latched.

The functions and operations of the data latches 1373A to 1373C of FIG. 13 are similar to those of the data latches 1373 of FIG. 10, and the functions and operations of the data latches 1374A to 1374C of FIG. 13. The function and operation of the data latch 1374 of FIG. 10 are similar, and the function and operation of each of the data latches 1375A to 1375C of FIG. 13 are similar to the function and operation of the data latch 1375 of FIG. The function and operation of each of the data latches 1376A to 1768C of 13 and the function and operation of the data latch 1374 of FIG. 10 are similar.

Each of the plurality of data latches 1373A-1376A, 1373B-1376B, and 1373C-1376C is from one of the corresponding data latches 1353A-1356A, 1353B-1356B, and 1353C-1356C in response to the clock signal CLK. The output data block can be latched.

For example, the data latch 1373A can latch the data block Y1-1 or Y12-2 output from the data latch 1353A in response to the clock signal CLK, and the data latch 1373B can clock. The data block Y2-1 or Y11-2 output from the data latch 1353B may be latched in response to the signal CLK.

The data block latched by the plurality of data latches 1373A to 1376A, 1373B to 1376B, and 1373C to 1376C may be output to the digital-analog conversion circuit 1400.

When the control circuit 1200 generates the selection signals SEL1 and SEL2 as shown in FIG. 14, the source driver 1010 may operate in a 1-DOT inversion scheme.

On the other hand, when the control circuit 1200 generates the selection signals SEL1 and SEL2 as shown in FIG. 15, the source driver 1010 may operate in a 6-DOT inversion scheme.

The number of multiplexers included in the latch control circuit 1310-4 shown in FIGS. 12 and 13 is smaller than the number of multiplexers included in the conventional data latch circuits. Therefore, there is an effect that the size of the chip on which the data latch circuit is implemented can be reduced.

FIG. 16 is a circuit diagram illustrating still another embodiment of the data latch circuit shown in FIG. 2.

1, 2, and 16, the data latch circuit 1300-5 may include a latch control circuit 1310-5 and a data latch block 1330-5. The data latch block 1330-5 may include a first latch circuit 1350-5 and a second latch circuit 1370-5.

The latch control circuit 1310-5 may include a plurality of multiplexers 1317-1319, the first latch circuit 1350-5 may include a plurality of data latches 1357-1359, The second latch circuit 1370-5 may include a plurality of data latches 1377 ˜ 1379.

Each of the multiplexers 1317 to 1319 may output any one of the plurality of latch clock signals LCLK1 to LCLK3 as the latch control signals LCS1 to LCS3 in response to the selection signal SEL.

Each of the multiplexers 1317 to 1319 may output different latch clock signals LCLK1 to LCLK3 as the latch control signals LCS1 to LCS3, respectively. Since the latch clock signals LCLK1 to LCLK3 are non-overlapping signals, the latch control signals LCS1 to LCS3 are also non-overlapping signals.

Each of the data latches 1357 to 1539 may latch a data block DATA input through a bus when the latch control signals LCS1 to LCS3 output from the corresponding multiplexers 1317 to 1319 are activated.

Each data latch 1377 to 1379 may latch a data block output from the corresponding data latches 1357 to 1359 in response to the clock signal CLK.

FIG. 17 is a schematic block diagram of a display module including the source driver shown in FIG. 1.

Referring to FIG. 17, the display module 1000 may include a source driver 1010, an interface 1030, a gate driver 1050, and a display panel 1070.

The interface 1030 is output from the host and receives the image data to be displayed through the display panel 1070, the source driver 1010, the start signal (SE), data blocks (DATA), polarity control signal (POL) , The inversion mode control signal DOT and the clock signal CLK may be output, and the operation of the gate driver 1050 may be controlled.

The gate driver 1050 outputs gating signals to the display panel 1070 under the control of the interface 1030 so that the signals output from the output buffer circuit 1600 of the source driver 1010 may cause the display panel 1070 to operate. Can be controlled to be displayed.

The display panel 1070 may display the signals output from the source driver 1010 in response to the gating signals output from the gate driver 1050.

According to an embodiment, the source driver 1010, the interface 1030, and the gate driver 1050 may be implemented as one chip or as separate independent chips.

FIG. 18 is a schematic block diagram of an electronic system and interface including the source driver shown in FIG. 1.

Referring to FIG. 18, an electronic system 3000 may include a data processing device capable of using or supporting a MIPI interface, such as a mobile phone, personal digital assistants, portable multimedia players, digital TVs, and IPTVs. ), A smart phone, or a tablet personal computer (PC).

The electronic system 3000 includes an application processor 3010, an image sensor 3040, and a display 3050.

The CSI host 3012 implemented in the application processor 3010 may serially communicate with the CSI device 3041 of the image sensor 3040 through a camera serial interface (CSI). The CSI host 3012 may include a deserializer (DES) and the CSI device 3041 may include a serializer (SER).

The DSI host 3011 implemented in the application processor 3010, via the display serial interface (DSI), the DSI device 3051 of the display 3050 including the source driver 1010 of FIG. Serial communication with

For example, the DSI host 3011 may include a serializer (SER), and the DSI device 3051 may include a deserializer (DES).

The electronic system 3000 may further include an RF chip 3060 that can communicate with the application processor 3010. The PHY 3013 of the electronic system 3000 and the PHY 3031 of the RF chip 3060 may exchange data according to the MIPI DigRF.

The electronic system 3000 may further include a global positioning system receiver 3020, a storage 3070, a microphone 3080, a DRAM 3085, and a speaker 3090.

The electronic system 3000 uses a World Interoperability for Microwave Access (Wimax) transceiver 3030, a wireless lan (WLAN) transceiver 3100, an ultra wideband (UWB) transceiver 3110, a long term evolution (LTE) transceiver, or the like. Wirelessly communicate with other devices.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

1010; Data Processing Unit, Source Driver
1100; Shift register
1200; Control circuit
1300; Data latch circuit
1310; Latch control circuit
1311-1319; Multiplexer
1330; Data latch block
1350; First latch circuit
1351-1359; Data latch
1370; Second latch circuit
1371-1379; Data latch
1400; Digital-to-analog conversion circuit
1500; Multiplexing circuit
1600; Output buffer circuit

Claims (10)

A first latch circuit for aligning serially input data blocks in parallel in response to non-overlapping latch control signals; And
And a second latch circuit for simultaneously latching data blocks aligned in parallel in response to a clock signal. The data processing apparatus of claim 1, wherein the data processing apparatus comprises:
And a latch control circuit for successively generating the non-overlapping latch control signals in response to a select signal. The method of claim 2, wherein the latch control circuit,
And a plurality of multiplexers, each outputting any one of a plurality of latch clock signals as one of the plurality of latch control signals in response to the selection signal. The method of claim 3,
And each of the plurality of multiplexers alternately outputs the plurality of latch clock signals as the one latch control signal. The data processing apparatus of claim 2, wherein the data processing apparatus comprises:
And a control circuit for generating the selection signal based on a polarity control signal and an inversion mode control signal. The data processing apparatus of claim 1, wherein the data processing apparatus comprises:
A digital-analog conversion circuit for converting output signals of the second latch circuit into analog signals;
A multiplexing circuit for rearranging the analog signals in response to the selection signal; And
And an output buffer circuit for buffering and outputting rearranged analog signals. A data processing apparatus of claim 1; And
And a display panel for displaying output signals of the data processing device in response to a gating signal output from a gate driver. Aligning serially input data blocks in parallel in response to non-overlapping latch control signals; And
And simultaneously latching data blocks aligned in parallel in response to a clock signal. The method of claim 8, wherein the operation method of the data processing apparatus comprises:
And sequentially generating the non-overlapping latch control signals in response to a selection signal. The method of claim 9, wherein generating the latch control signals sequentially comprises:
And alternately outputting a plurality of latch clock signals as any one of the latch control signals in response to the selection signal.

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