CN112583412B - Digital-to-analog conversion circuit and digital-to-analog converter - Google Patents
Digital-to-analog conversion circuit and digital-to-analog converter Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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- H03M1/66—Digital/analogue converters
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Abstract
The application discloses digital-to-analog conversion circuit and digital-to-analog conversion, output first electric current through power supply circuit, conversion circuit converts first electric current into first voltage, and the voltage value of the first electric voltage of output when receiving first input signal is by first numerical value incremental change to the second numerical value, and the voltage value of the first electric voltage of output when receiving the second input signal is by the second numerical value decremental change to first numerical value, clamping circuit outputs clamping current according to first electric voltage, output circuit outputs voltage analog quantity according to clamping current, thereby the digital-to-analog conversion circuit of this application realizes the amplification to the voltage analog quantity of output through amplifying single undercurrent into the undercurrent, the problem that is difficult to match a plurality of undercurrent sources that exists in traditional scheme, match with high costs and a plurality of undercurrent matching degree not high results in is solved, and through the rise/decline change time of the voltage analog quantity of control output, stability of output has been improved.
Description
Technical Field
The application belongs to the technical field of digital-to-analog conversion, and particularly relates to a digital-to-analog conversion circuit and a digital-to-analog converter.
Background
The traditional current steering digital-to-analog conversion circuit outputs large current after synthesizing the large current through a plurality of current sources, and the rising time and the falling time of the large current output are limited in a certain interval by a protocol, so that the number of the current sources in the traditional scheme can be very large, the matching degree of the output currents of all the current sources can directly influence the performance of the current steering digital-to-analog conversion circuit, but the matching of all the current sources is difficult, and therefore the traditional current steering digital-to-analog conversion circuit has high cost and poor performance.
Disclosure of Invention
The purpose of the application is to provide a digital-to-analog conversion circuit, which aims to solve the problems of high cost and poor performance of the traditional digital-to-analog conversion circuit.
A first aspect of an embodiment of the present application provides a digital-to-analog conversion circuit, including:
a power supply circuit configured to output a first current;
the conversion circuit is connected with the power supply circuit and is configured to output a first voltage according to the first current, the value interval of the voltage value of the first voltage is a first value to a second value, the voltage value of the first voltage is increased from the first value to the second value when a first input signal is received, and the voltage value of the first voltage is decreased from the second value to the first value when a second input signal is received;
a clamping circuit connected with the conversion circuit and configured to output clamping current according to the first voltage; and
and the output circuit is connected with the clamping circuit and is configured to output voltage analog quantity according to the clamping current.
In one embodiment, the conversion circuit includes:
a switching circuit configured to output a second current and a third current according to the first current, to control a current value of the second current to decrease from a third value to zero and a current value of the third current to increase from zero to the third value when the first input signal is received, and to control a current value of the second current to increase from zero to the third value and a current value of the third current to decrease from the third value to zero when the second input signal is received; and
a current-to-voltage circuit, coupled to the switching circuit, configured to output the first voltage in accordance with the second current and the third current;
wherein the voltage value of the first voltage is the first value when the current value of the second current is zero and the current value of the third current is the third value, and the voltage value of the first voltage is the second value when the current value of the second current is the third value and the current value of the third current is zero.
In one embodiment, the switching circuit comprises a first switching component and a second switching component;
the first switch assembly is configured to output the second current according to the first current, control the current value of the second current to decrease from the third value to zero when the first input signal is received, and control the current value of the second current to increase from zero to the third value when the second input signal is received;
the second switch assembly is configured to output the third current according to the first current, to control the current value of the third current to be increased from zero to the third value when the first input signal is received, and to control the current value of the third current to be decreased from the third value to zero when the second input signal is received.
In one embodiment, the first input signal includes N sequential signals sequentially input, the second input signal includes N clock signals sequentially input, the first switch assembly includes N switch units, and the second switch assembly includes N switch elements;
the L switch unit is configured to be turned on when an L time sequence signal is input, output an L branch current according to the first current, and turned off when an L clock signal is input;
the L-th switching element is configured to be turned off when an L-th timing signal is input, turned on when an L-th clock signal is input, and output an L-th shunt current according to the first current;
wherein all branch currents constitute the second current and the branch currents constitute the third current;
n is an integer greater than or equal to 2, and L is a positive integer less than or equal to N.
In one embodiment, the L-th switching unit includes an L-th field effect transistor, and the L-th switching element includes an L-th unipolar transistor;
the input end of the L-th field effect transistor is connected to the first current input end of the L-th switching unit, the output end of the L-th field effect transistor is connected to the second current output end of the L-th switching unit, and the enabling end of the L-th field effect transistor is connected to the L-th time sequence signal input end and the L-th clock signal input end of the L-th switching unit;
the input end of the L unipolar transistor is connected to the first current input end of the L switching element, the output end of the L unipolar transistor is connected to the third current output end of the L switching element, and the control end of the L unipolar transistor is connected to the L timing signal input end and the L clock signal input end of the L switching element.
In one embodiment, the current-to-voltage circuit includes a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor;
the first end of the first resistor, the first end of the second resistor and the first end of the third resistor are commonly connected, the first end of the first resistor and the first end of the first capacitor are connected and connected to the second current input end of the current-to-voltage circuit, the first end of the second resistor and the first end of the second capacitor are connected and connected to the third current input end and the first voltage output end of the current-to-voltage circuit, and the second end of the first capacitor, the second end of the second capacitor and the second end of the third resistor are all connected with power ground.
In one embodiment, the clamping circuit includes an operational amplifier, a first MOS transistor, and a fourth resistor;
the positive phase input end of the operational amplifier is connected to the first voltage input end of the clamping circuit, the negative phase input end of the operational amplifier, the first end of the fourth resistor and the source electrode of the first MOS tube are commonly connected, the output end of the operational amplifier is connected with the grid electrode of the first MOS tube, the second end of the fourth resistor is connected with the power ground and is connected to the clamping current output end of the clamping circuit, and the drain electrode of the first MOS tube is connected to the clamping current input end of the clamping circuit.
In one embodiment, the output circuit includes a second MOS transistor and a fifth resistor;
the grid electrode of the second MOS tube is connected to the working signal input end of the output circuit, the source electrode of the second MOS tube is connected to the clamping current output end of the output circuit, the drain electrode of the second MOS tube is connected with the first end of the fifth resistor and is connected to the voltage analog output end of the output circuit, and the second end of the fifth resistor is connected with an internal power supply.
In one embodiment, the time for the voltage value of the first voltage to be increased from the first value to the second value is 3-5 ns, and the time for the voltage value of the first voltage to be decreased from the second value to the first value is 3-5 ns.
A second aspect of an embodiment of the present application provides a digital-to-analog converter comprising a digital-to-analog conversion circuit as claimed in any one of the first aspects.
Compared with the prior art, the beneficial effects that this application exists are: the digital-to-analog conversion circuit comprises a power supply circuit, a conversion circuit, a clamping circuit, an output circuit and a digital-to-analog conversion circuit, wherein the power supply circuit outputs first current, the conversion circuit converts the first current into first voltage, the voltage value of the first voltage output when receiving a first input signal is changed from a first numerical value to a second numerical value in an increasing mode, the voltage value of the first voltage output when receiving a second input signal is changed from a second numerical value to the first numerical value in a decreasing mode, the clamping circuit outputs clamping current according to the first voltage, and the output circuit outputs voltage analog quantity according to the clamping current.
Drawings
Fig. 1 is a first example schematic block diagram of a digital-to-analog conversion circuit provided in an embodiment of the present application;
FIG. 2 is a second exemplary functional block diagram of a digital-to-analog conversion circuit provided in an embodiment of the present application;
FIG. 3 is a third exemplary functional block diagram of a digital-to-analog conversion circuit provided by an embodiment of the present application;
fig. 4 is a fourth exemplary schematic block diagram of a digital-to-analog conversion circuit provided by an embodiment of the present application;
fig. 5 is a schematic circuit diagram of an example of a digital-to-analog conversion circuit according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
Fig. 1 shows a first exemplary schematic block diagram of a digital-to-analog conversion circuit 200 provided in an embodiment of the present application, and for convenience of explanation, only the portions related to the present embodiment are shown, which is described in detail below:
the digital-to-analog conversion circuit 200 includes a power supply circuit 100, a conversion circuit 200, a clamp circuit 300, and an output circuit 400.
The power supply circuit 100 is configured to output a first current.
The conversion circuit 200 is connected to the power circuit 100 and configured to output a first voltage according to the first current, wherein a voltage value of the first voltage ranges from a first value to a second value, the voltage value of the first voltage increases from the first value to the second value when the first input signal is received, and the voltage value of the first voltage decreases from the second value to the first value when the second input signal is received.
The clamp circuit 300 is connected to the conversion circuit 200 and configured to output a clamp current according to the first voltage.
The output circuit 400 is connected to the clamp circuit 300 and configured to output a voltage analog quantity according to the clamp current.
In this embodiment, the conversion circuit 200 converts the first current output by the power supply circuit 100 into a first voltage, and the voltage value of the first voltage output by the conversion circuit 200 upon receiving the first input signal is changed from a first value to a second value in an increasing manner, the first voltage output by the conversion circuit 200 upon receiving the first input signal is not increased instantaneously but is increased in a certain period of time, the voltage value of the first voltage output by the conversion circuit 200 upon receiving the second input signal is changed from a second value to a first value in a decreasing manner, the first voltage output by the conversion circuit 200 upon receiving the second input signal is not decreased instantaneously but is reduced in a certain period of time, the clamp circuit 300 outputs a clamp current according to the first voltage, the clamp current is used as a current output by the output circuit 400 at the output circuit 400 equal to the clamp current, the output circuit 400 outputs a voltage analog quantity according to the clamp current, the voltage analog quantity output by the output circuit 400 increases along with the increment of the first voltage when the conversion circuit 200 receives the first input signal, and the voltage analog quantity output by the output circuit 400 decreases along with the decrement of the first voltage when the conversion circuit 200 receives the second input signal, so that a certain time is required for rising and falling of the voltage analog quantity output by the digital-to-analog conversion circuit 200 of the embodiment, in addition, the first current output by the power supply circuit 100 can be amplified and converted into the clamp current through the conversion circuit 200 and the clamp circuit 300, the amplification of the output voltage analog quantity by amplifying a single small current (the first current) to output a large current (the clamp current) is realized, and the problems that a plurality of small current sources are difficult to match in the traditional scheme are solved, the matching cost of a plurality of small current sources is high, and the performance is poor due to the fact that the matching degree of a plurality of small currents is not high.
The increasing speed of the first voltage from the first value to the second value can be kept consistent or can be changed, the decreasing speed of the first voltage from the second value to the first value can be kept consistent or can be changed, and the changing speed of the first voltage from the first value to the second value can be the same as or different from the changing speed of the first voltage from the second value to the first value.
Referring to fig. 2, in one embodiment, the conversion circuit 200 includes a switch circuit 210 and a current-to-voltage circuit 220.
The switching circuit 210 is configured to output a second current and a third current according to the first current, control the current value of the second current to decrease from the third value to zero and the current value of the third current to increase from zero to the third value when the first input signal is received, and control the current value of the second current to increase from zero to the third value and the current value of the third current to decrease from the third value to zero when the second input signal is received.
The current-to-voltage circuit 220, coupled to the switching circuit 210, is configured to output a first voltage based on the second current and the third current.
The voltage value of the first voltage is a first value when the current value of the second current is zero and the current value of the third current is a third value, and the voltage value of the first voltage is a second value when the current value of the second current is a third value and the current value of the third current is zero.
In the present embodiment, the switch circuit 210 distributes the first current into the second current and the third current, when the switch circuit 210 receives the first input signal, the current value of the second current controlled to be output decreases from the third value to zero and the current value of the third current increases from zero to the third value, when the switch circuit 210 receives the second input signal, the current value of the second current controlled to be output increases from zero to the third value and the current value of the third current decreases from the third value to zero, the current-to-voltage circuit 220 outputs the first voltage according to the second current and the third current, because the ratio of the second current to the third current converted into the voltage by the current-to-voltage circuit 220 is different, and therefore, when the second current and the third current change, the first voltage outputted by the current-to-voltage circuit 220 also changes.
The third value is the current value of the first current, and considering that there is a certain loss after the current value of the first current passes through the switch circuit 210, the third value is actually smaller than the current value of the first current.
Referring to fig. 3, in one embodiment, the switch circuit 210 includes a first switch component 230 and a second switch component 240.
The first switching component 230 is configured to output a second current according to the first current, to control the current value of the second current to decrease from a third value to zero when the first input signal is received, and to control the current value of the second current to increase from zero to the third value when the second input signal is received.
The second switching component 240 is configured to output a third current according to the first current, to control the current value of the third current to increase from zero to a third value when the first input signal is received, and to control the current value of the third current to decrease from the third value to zero when the second input signal is received.
In this embodiment, the first switch assembly 230 outputs the second current according to the first current, the first switch assembly 230 controls the output second current value to decrease from the third value to zero when receiving the first input signal, the first switch assembly 230 controls the output second current value to increase from zero to the third value when receiving the second input signal, the second switch assembly 240 outputs the third current according to the first current, the second switch assembly 240 controls the output third current value to increase from zero to the third value when receiving the first input signal, the third switch assembly 230 controls the output third current value to decrease from the third value to zero when receiving the second input signal, the first switch assembly 230 realizes the change of the second current value and the time required for the change of the third current value, and the second switch assembly 240 realizes the change of the third current value and the time required for the change.
Referring to fig. 4, in one embodiment, the first input signal includes N sequential signals, the second input signal includes N clock signals, the first switch assembly 230 includes N switch units (denoted by reference numeral 231 … N), and the second switch assembly 240 includes N switch elements (denoted by reference numeral 241 … N).
The L-th switching unit is configured to be turned on when the L-th timing signal is input and to output an L-th branch current according to the first current, and to be turned off when the L-th clock signal is input.
The L-th switching element is configured to be turned off when an L-th timing signal is input, turned on when an L-th clock signal is input, and output an L-th shunt current according to the first current.
All branch currents form a second current, and the branch currents form a third current;
n is an integer greater than or equal to 2, and L is a positive integer less than or equal to N.
In this embodiment, N timing signals are sequentially input to the N switch units and the N switch elements at intervals, when the L switch unit inputs the L timing signal, the L switch unit is turned on and outputs the L branch current according to the first current, so that the L switch unit is essentially impedance when turned on, and therefore the L switch unit is turned on, and branches of the first current are split to generate the L branch current, all branch currents are added to form the second current, when the L switch element inputs the L clock signal, the L switch unit is turned on and outputs the L branch current according to the first current, and is essentially impedance when the L switch element is turned on, and therefore the L switch element is turned on, and shunts the first current to generate the L branch current, and all branch currents are added to form the third current, so that the N switch units and the N switch elements realize the distribution of the first current to the second current and the third current and realize the gradual change of controlling the second current and the third current.
Referring to fig. 5, in one embodiment, the L-th switching unit includes an L-th field effect transistor (denoted by reference numeral Q1 … Qn), and the L-th switching unit includes an L-th unipolar transistor (denoted by reference numeral qn+1 … q2n).
The input end of the L-th field effect transistor is connected to the first current input end of the L-th switching unit, the output end of the L-th field effect transistor is connected to the second current output end of the L-th switching unit, and the enabling end of the L-th field effect transistor is connected to the L-th time sequence signal input end and the L-th clock signal input end of the L-th switching unit.
The input end of the L unipolar transistor is connected to the first current input end of the L switching element, the output end of the L unipolar transistor is connected to the third current output end of the L switching element, and the control end of the L unipolar transistor is connected to the L time sequence signal input end and the L clock signal input end of the L switching element.
Referring to fig. 5, in one embodiment, the current-to-voltage circuit 220 includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a second capacitor C2.
The first end of the first resistor R1, the first end of the second resistor R2 and the first end of the third resistor R3 are commonly connected, the first end of the first resistor R1 and the first end of the first capacitor C1 are connected and connected to the second current input end of the current-to-voltage circuit 220, the first end of the second resistor R2 and the first end of the second capacitor C2 are connected and connected to the third current input end and the first voltage output end of the current-to-voltage circuit 220, and the second end of the first capacitor C1, the second end of the second capacitor C2 and the second end of the third resistor R3 are all connected with the power ground.
Referring to fig. 5, in one embodiment, the clamping circuit 300 includes an operational amplifier U1, a first MOS (Metal Oxide Semiconductor ) transistor M1 and a fourth resistor R4.
The positive phase input end of the operational amplifier U1 is connected to the first voltage input end of the clamping circuit 300, the negative phase input end of the operational amplifier U1, the first end of the fourth resistor R4 and the source electrode of the first MOS tube M1 are commonly connected, the output end of the operational amplifier U1 is connected with the grid electrode of the first MOS tube M1, the second end of the fourth resistor R4 is connected with the power ground and is connected to the clamping current output end of the clamping circuit 300, and the drain electrode of the first MOS tube M1 is connected to the clamping current input end of the clamping circuit 300.
Referring to fig. 5, in one embodiment, the output circuit 400 includes a second MOS transistor M2 and a fifth resistor R5.
The grid electrode of the second MOS tube M2 is connected to the working signal input end of the output circuit 400, the source electrode of the second MOS tube M2 is connected to the clamping current output end of the output circuit 400, the drain electrode of the second MOS tube M2 is connected with the first end of the fifth resistor R5 and is connected to the voltage analog output end of the output circuit 400, and the second end of the fifth resistor R5 is connected with an internal power supply.
The digital-to-analog conversion circuit 200 shown in fig. 5 is described below with reference to the working principle, when N high levels (clock signals) sequentially act on N field effect transistors and N unipolar transistors, the N unipolar transistors are sequentially turned on, when all the N field effect transistors are turned off and all the N unipolar transistors are turned on, at this time, the first current output by the current source A1 flows through the N unipolar transistors and outputs the third current at the source of the N unipolar transistors, the third current flows through the second resistor R2 and the third resistor R3 to be output to the power supply ground, and the third current forms the first voltage under the voltage dividing action of the second resistor R2 and the third resistor R3 and is output to the positive phase input end of the operational amplifier U1, because the output end of the operational amplifier U1 is connected with the gate of the first MOS transistor M1, the negative phase input end of the operational amplifier U1 and the first end of the fourth resistor R4 are commonly connected, the output end of the operational amplifier U1 outputs the third current at the output end of the second MOS transistor R2 and the fourth MOS transistor R4, at this time, the voltage output end of the operational amplifier U1 acts on the fourth clamp voltage at the fourth MOS transistor R4 and the fourth voltage is equal to the voltage dividing the fourth voltage, at this time, the fourth voltage is equal to the fourth voltage, the fourth voltage is subtracted from the fourth voltage flowing through the fourth resistor R4, and the fourth voltage is equal to the fourth voltage flowing through the fourth voltage resistor R4, and the fourth voltage is equal to the fourth voltage, at this time, the fourth voltage is equal to the fourth voltage, and the fourth voltage is subtracted, and the fourth voltage is equal to the fourth voltage value is calculated, and has the fourth voltage, and has the voltage value.
When N low levels (time sequence signals) are sequentially input to N field effect transistors and N unipolar transistors instead of N high levels, the N field effect transistors are sequentially turned on, the N unipolar transistors are sequentially turned off, when the N field effect transistors are sequentially turned on and the N unipolar transistors are sequentially turned off, the resistance of the N field effect transistors is increased, the resistance of the N unipolar transistors is reduced, so that the second current formed by the first current flowing through the N field effect transistors is increased, the third current formed by the first current flowing through the N unipolar transistors is decreased, at the moment, the second current flows through the first resistor R1 and the third resistor R3 to be grounded, the third current flows through the second resistor R2 and the third resistor R3 to be grounded, the second current is formed under the action of the third resistor R3 and outputs a second voltage, the second voltage is equal to the partial pressure of the second current on the third resistor R3, the third current forms and outputs a third voltage under the action of the second resistor R2 and the third resistor R3, the third voltage is equal to the partial pressure of the third current on the second resistor R2 and the third resistor R3, the second voltage is added with the third voltage to be equal to the first voltage, because the numerical proportion of the second current to the second voltage is smaller than that of the third current to the third voltage, under the condition that the total current value of the second current and the third current is unchanged, the larger the second current is, the smaller the first voltage is, so that the first voltage is decreased when N field effect transistors are sequentially turned on and N unipolar transistors are sequentially turned off, the finally outputted voltage analog quantity is decreased, and similarly, when N high levels replace N low levels to be sequentially inputted to the N field effect transistors and the N unipolar transistors, the finally outputted voltage analog quantity is increased, the minimum ratio of the clamping current of the fourth resistor R4 to the first current depends on the ratio of the clamping current of the first resistor R1 to the first current of the fourth resistor R4, the maximum ratio of the clamping current of the fourth resistor R4 to the first current depends on the ratio of the sum of the resistances of the second resistor R2 and the third resistor R3 to the resistance of the fourth resistor R4, for example, when the sum of the resistances of the second resistor R2 and the third resistor R3 is ten times the resistance of the fourth resistor R4, the clamping current can reach ten times the maximum value of the first current, and in the manufacturing process, the resistance accuracy control of the resistor is easier than the accuracy control of the output current of the current source A1, so the resistance accuracy of the resistor is easy to be made high and low, and the accuracy of the output current is controlled through the ratio relation of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 is high and low, thereby the accuracy of the digital-to-analog conversion circuit 200 is improved and the cost is reduced.
In one embodiment, the time for increasing the voltage value of the first voltage from the first value to the second value is 3-5 ns, and the time for decreasing the voltage value of the first voltage from the second value to the first value is 3-5 ns.
In this embodiment, the time for the voltage value of the first voltage to be increased from the first value to the second value is 3-5 ns, and the time for the voltage value of the first voltage to be decreased from the second value to the first value is 3-5 ns, so that the rising and falling time of the voltage analog quantity output by the digital-to-analog conversion circuit 200 both meet the protocol requirements.
The digital-to-analog converter of the present embodiment further provides a digital-to-analog converter including the digital-to-analog conversion circuit 200 of any one of the above embodiments, and therefore the digital-to-analog converter of the present embodiment at least includes the beneficial effects corresponding to the digital-to-analog conversion circuit 200 of any one of the above embodiments.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. A digital-to-analog conversion circuit, comprising:
a power supply circuit configured to output a first current;
the conversion circuit is connected with the power supply circuit and is configured to output a first voltage according to the first current, the value interval of the voltage value of the first voltage is a first value to a second value, the voltage value of the first voltage is increased from the first value to the second value when a first input signal is received, and the voltage value of the first voltage is decreased from the second value to the first value when a second input signal is received;
a clamping circuit connected with the conversion circuit and configured to output clamping current according to the first voltage; and
and the output circuit is connected with the clamping circuit and is configured to output voltage analog quantity according to the clamping current.
2. The digital to analog conversion circuit of claim 1, wherein said conversion circuit comprises:
a switching circuit configured to output a second current and a third current according to the first current, to control a current value of the second current to decrease from a third value to zero and a current value of the third current to increase from zero to the third value when the first input signal is received, and to control a current value of the second current to increase from zero to the third value and a current value of the third current to decrease from the third value to zero when the second input signal is received; and
a current-to-voltage circuit, coupled to the switching circuit, configured to output the first voltage in accordance with the second current and the third current;
wherein the voltage value of the first voltage is the first value when the current value of the second current is zero and the current value of the third current is the third value, and the voltage value of the first voltage is the second value when the current value of the second current is the third value and the current value of the third current is zero.
3. The digital to analog conversion circuit of claim 2, wherein said switching circuit comprises a first switching component and a second switching component;
the first switch assembly is configured to output the second current according to the first current, control the current value of the second current to decrease from the third value to zero when the first input signal is received, and control the current value of the second current to increase from zero to the third value when the second input signal is received;
the second switch assembly is configured to output the third current according to the first current, to control the current value of the third current to be increased from zero to the third value when the first input signal is received, and to control the current value of the third current to be decreased from the third value to zero when the second input signal is received.
4. The digital-to-analog conversion circuit of claim 3, wherein the first input signal comprises N sequential signals sequentially input, the second input signal comprises N clock signals sequentially input, the first switch assembly comprises N switch units, and the second switch assembly comprises N switch elements;
the L switch unit is configured to be turned on when an L time sequence signal is input, output an L branch current according to the first current, and turned off when an L clock signal is input;
the L switching element is configured to be turned off when an L timing signal is input, turned on when an L clock signal is input, and output an L shunt current according to the first current;
wherein all branch currents constitute the second current and the branch currents constitute the third current;
n is an integer greater than or equal to 2, and L is a positive integer less than or equal to N.
5. The digital to analog conversion circuit of claim 4, wherein said L-th switching element comprises an L-th field effect transistor, said L-th switching element comprising an L-th unipolar transistor;
the input end of the L-th field effect transistor is connected to the first current input end of the L-th switching unit, the output end of the L-th field effect transistor is connected to the second current output end of the L-th switching unit, and the enabling end of the L-th field effect transistor is connected to the L-th time sequence signal input end and the L-th clock signal input end of the L-th switching unit;
the input end of the L unipolar transistor is connected to the first current input end of the L switching element, the output end of the L unipolar transistor is connected to the third current output end of the L switching element, and the control end of the L unipolar transistor is connected to the L timing signal input end and the L clock signal input end of the L switching element.
6. The digital to analog conversion circuit of claim 2, wherein the current to voltage circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor;
the first end of the first resistor, the first end of the second resistor and the first end of the third resistor are commonly connected, the first end of the first resistor and the first end of the first capacitor are connected and connected to the second current input end of the current-to-voltage circuit, the first end of the second resistor and the first end of the second capacitor are connected and connected to the third current input end and the first voltage output end of the current-to-voltage circuit, and the second end of the first capacitor, the second end of the second capacitor and the second end of the third resistor are all connected with power ground.
7. The digital to analog conversion circuit of claim 1, wherein the clamping circuit comprises an operational amplifier, a first MOS transistor, and a fourth resistor;
the positive phase input end of the operational amplifier is connected to the first voltage input end of the clamping circuit, the negative phase input end of the operational amplifier, the first end of the fourth resistor and the source electrode of the first MOS tube are commonly connected, the output end of the operational amplifier is connected with the grid electrode of the first MOS tube, the second end of the fourth resistor is connected with the power ground and is connected to the clamping current output end of the clamping circuit, and the drain electrode of the first MOS tube is connected to the clamping current input end of the clamping circuit.
8. The digital to analog conversion circuit of claim 1, wherein said output circuit comprises a second MOS transistor and a fifth resistor;
the grid electrode of the second MOS tube is connected to the working signal input end of the output circuit, the source electrode of the second MOS tube is connected to the clamping current output end of the output circuit, the drain electrode of the second MOS tube is connected with the first end of the fifth resistor and is connected to the voltage analog output end of the output circuit, and the second end of the fifth resistor is connected with an internal power supply.
9. The digital to analog conversion circuit of claim 1, wherein a time for the voltage value of the first voltage to be incremented from the first value to the second value is 3 to 5ns, and a time for the voltage value of the first voltage to be decremented from the second value to the first value is 3 to 5ns.
10. A digital-to-analog converter comprising a digital-to-analog conversion circuit as claimed in any one of claims 1 to 9.
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| CN113805843B (en) * | 2021-09-24 | 2024-03-19 | 上海集成电路装备材料产业创新中心有限公司 | Maximum value solving circuit and maximum value solving method |
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|---|---|---|---|---|
| KR20070023596A (en) * | 2005-08-24 | 2007-02-28 | 마이크렐 인코포레이티드 | Analog internal soft-start and clamp circuit for switching regulator |
| WO2020125603A1 (en) * | 2018-12-17 | 2020-06-25 | 上海艾为电子技术股份有限公司 | Circuit and method for turning on analog switch |
| CN211930938U (en) * | 2020-06-11 | 2020-11-13 | 深圳市明微电子股份有限公司 | LED drive circuit with high power factor and low harmonic and LED device |
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| CN107425845B (en) * | 2017-05-08 | 2020-12-25 | 华为技术有限公司 | Superposition operation circuit and floating voltage digital-to-analog conversion circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070023596A (en) * | 2005-08-24 | 2007-02-28 | 마이크렐 인코포레이티드 | Analog internal soft-start and clamp circuit for switching regulator |
| WO2020125603A1 (en) * | 2018-12-17 | 2020-06-25 | 上海艾为电子技术股份有限公司 | Circuit and method for turning on analog switch |
| CN211930938U (en) * | 2020-06-11 | 2020-11-13 | 深圳市明微电子股份有限公司 | LED drive circuit with high power factor and low harmonic and LED device |
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