CN112583412A - Digital-to-analog conversion circuit and digital-to-analog converter - Google Patents
Digital-to-analog conversion circuit and digital-to-analog converter Download PDFInfo
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Abstract
The application discloses a digital-to-analog conversion circuit and a digital-to-analog converter, wherein a power supply circuit outputs a first current, the conversion circuit converts the first current into a first voltage, the voltage value of the first voltage output when a first input signal is received is gradually changed from a first numerical value to a second numerical value, the voltage value of the first voltage output when a second input signal is received is gradually changed from the second numerical value to the first numerical value, a clamping circuit outputs a clamping current according to the first voltage, and an output circuit outputs a voltage analog quantity according to the clamping current. And the stability of the output is improved by controlling the rising/falling change time of the output voltage analog quantity.
Description
Technical Field
The application belongs to the technical field of digital-to-analog conversion, and particularly relates to a digital-to-analog conversion circuit and a digital-to-analog converter.
Background
The traditional current steering digital-to-analog conversion circuit synthesizes large current through a plurality of current sources and then outputs the large current, and the rising time and the falling time of the large current output are limited in a certain interval by a protocol, so that the quantity of the current sources in the traditional scheme is very large, the matching degree of the output currents of all the current sources can directly influence the performance of the current steering digital-to-analog conversion circuit, but all the current sources are difficult to match, and the traditional current steering digital-to-analog conversion circuit is high in manufacturing cost and poor in performance.
Disclosure of Invention
The application aims to provide a digital-to-analog conversion circuit, and aims to solve the problems of high cost and poor performance of the traditional digital-to-analog conversion circuit.
A first aspect of an embodiment of the present application provides a digital-to-analog conversion circuit, including:
a power supply circuit configured to output a first current;
the conversion circuit is connected with the power supply circuit and configured to output a first voltage according to the first current, the voltage value of the first voltage ranges from a first value to a second value, the voltage value of the first voltage is increased from the first value to the second value when a first input signal is received, and the voltage value of the first voltage is decreased from the second value to the first value when a second input signal is received;
the clamping circuit is connected with the conversion circuit and is configured to output a clamping current according to the first voltage; and
and the output circuit is connected with the clamping circuit and is configured to output voltage analog quantity according to the clamping current.
In one embodiment, the conversion circuit includes:
the switching circuit is configured to output a second current and a third current according to the first current, control the current value of the second current to decrease from a third value to zero and control the current value of the third current to increment from zero to the third value when the first input signal is received, and control the current value of the second current to increment from zero to the third value and control the current value of the third current to decrease from the third value to zero when the second input signal is received; and
a current-to-voltage circuit connected to the switching circuit and configured to output the first voltage according to the second current and the third current;
wherein the voltage value of the first voltage is the first value when the current value of the second current is zero and the current value of the third current is the third value, and the voltage value of the first voltage is the second value when the current value of the second current is the third value and the current value of the third current is zero.
In one embodiment, the switching circuit includes a first switching component and a second switching component;
the first switch assembly is configured to output the second current according to the first current, control a current value of the second current to decrease from the third value to zero when the first input signal is received, and control a current value of the second current to increase from zero to the third value when the second input signal is received;
the second switch assembly is configured to output the third current according to the first current, control a current value of the third current to be increased from zero to the third value when the first input signal is received, and control a current value of the third current to be decreased from the third value to zero when the second input signal is received.
In one embodiment, the first input signal includes N sequentially input timing signals, the second input signal includes N sequentially input clock signals, the first switch assembly includes N switch units, and the second switch assembly includes N switch elements;
the Lth switching unit is configured to be turned on when an Lth timing signal is input and output an Lth branch current according to the first current, and to be turned off when an Lth clock signal is input;
the Lth switching element is configured to be turned off when an Lth timing signal is input, to be turned on when an Lth clock signal is input, and to output an Lth shunt current according to the first current;
wherein all branch currents constitute the second current and the branch currents constitute the third current;
n is an integer of 2 or more, and L is a positive integer of N or less.
In one embodiment, the lth switching unit comprises an lth field-effect transistor, and the lth switching element comprises an lth unipolar transistor;
the input end of the L-th field effect transistor is connected to the first current input end of the L-th switch unit, the output end of the L-th field effect transistor is connected to the second current output end of the L-th switch unit, and the enable end of the L-th field effect transistor is connected to the L-th time sequence signal input end and the L-th clock signal input end of the L-th switch unit;
an input end of the L-th unipolar transistor is connected to a first current input end of the L-th switching element, an output end of the L-th unipolar transistor is connected to a third current output end of the L-th switching element, and a control end of the L-th unipolar transistor is connected to an L-th timing signal input end and an L-th clock signal input end of the L-th switching element.
In one embodiment, the current-to-voltage circuit includes a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor;
the first end of the first resistor, the first end of the second resistor and the first end of the third resistor are connected in common, the first end of the first resistor and the first end of the first capacitor are connected and connected to the second current input end of the current-to-voltage circuit, the first end of the second resistor and the first end of the second capacitor are connected and connected to the third current input end and the first voltage output end of the current-to-voltage circuit, and the second end of the first capacitor, the second end of the second capacitor and the second end of the third resistor are all connected with a power ground.
In one embodiment, the clamping circuit comprises an operational amplifier, a first MOS transistor and a fourth resistor;
the positive phase input end of the operational amplifier is connected to the first voltage input end of the clamping circuit, the negative phase input end of the operational amplifier, the first end of the fourth resistor and the source electrode of the first MOS tube are connected in common, the output end of the operational amplifier is connected with the grid electrode of the first MOS tube, the second end of the fourth resistor is connected with the power ground and connected to the clamping current output end of the clamping circuit, and the drain electrode of the first MOS tube is connected to the clamping current input end of the clamping circuit.
In one embodiment, the output circuit comprises a second MOS transistor and a fifth resistor;
the grid electrode of the second MOS tube is connected to the working signal input end of the output circuit, the source electrode of the second MOS tube is connected to the clamping current output end of the output circuit, the drain electrode of the second MOS tube is connected with the first end of the fifth resistor and connected to the voltage analog output end of the output circuit, and the second end of the fifth resistor is connected with an internal power supply.
In one embodiment, the time for the voltage value of the first voltage to increase from the first value to the second value is 3-5 ns, and the time for the voltage value of the first voltage to decrease from the second value to the first value is 3-5 ns.
A second aspect of embodiments of the present application provides a digital-to-analog converter comprising a digital-to-analog conversion circuit as claimed in any one of the first aspect.
Compared with the prior art, the application has the beneficial effects that: the power supply circuit outputs a first current, the conversion circuit converts the first current into a first voltage, the voltage value of the first voltage output when a first input signal is received is gradually changed from a first numerical value to a second numerical value, the voltage value of the first voltage output when a second input signal is received is gradually changed from the second numerical value to the first numerical value, the clamping circuit outputs a clamping current according to the first voltage, the output circuit outputs a voltage analog quantity according to the clamping current, the digital-to-analog conversion circuit amplifies a single small current into a large current so as to amplify the output voltage analog quantity, the problems that a plurality of small current sources are difficult to match, the matching cost of the plurality of small current sources is high, and the performance is poor due to low matching degree of the plurality of small currents in the traditional scheme are solved, and meanwhile, the voltage analog quantity output by the digital-to-analog conversion circuit finishes rising and falling within a period of time, the stability of the voltage analog quantity output by the digital-to-analog conversion circuit is improved.
Drawings
Fig. 1 is a first exemplary functional block diagram of a digital-to-analog conversion circuit provided in an embodiment of the present application;
fig. 2 is a second exemplary functional block diagram of a digital-to-analog conversion circuit according to an embodiment of the present disclosure;
fig. 3 is a third exemplary functional block diagram of a digital-to-analog conversion circuit according to an embodiment of the present disclosure;
fig. 4 is a fourth exemplary functional block diagram of a digital-to-analog conversion circuit according to an embodiment of the present disclosure;
fig. 5 is an exemplary circuit schematic diagram of a digital-to-analog conversion circuit according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Fig. 1 shows a first exemplary schematic block diagram of a digital-to-analog conversion circuit 200 provided in an embodiment of the present application, and for convenience of description, only the parts related to the embodiment are shown, and detailed as follows:
the digital-to-analog conversion circuit 200 includes a power supply circuit 100, a conversion circuit 200, a clamp circuit 300, and an output circuit 400.
The power supply circuit 100 is configured to output a first current.
The conversion circuit 200 is connected to the power circuit 100, and configured to output a first voltage according to the first current, where a voltage value of the first voltage ranges from a first value to a second value, the voltage value of the first voltage increases from the first value to the second value when the first input signal is received, and the voltage value of the first voltage decreases from the second value to the first value when the second input signal is received.
The clamping circuit 300 is connected to the converting circuit 200 and configured to output a clamping current according to the first voltage.
And an output circuit 400 connected to the clamping circuit 300 and configured to output a voltage analog according to the clamping current.
In this embodiment, the converting circuit 200 converts the first current output by the power circuit 100 into the first voltage, the voltage value of the first voltage output by the converting circuit 200 when receiving the first input signal is changed from the first value to the second value in an increasing manner, the first voltage output by the converting circuit 200 when receiving the first input signal is not boosted instantaneously but boosted within a certain time, the voltage value of the first voltage output by the converting circuit 200 when receiving the second input signal is changed from the second value to the first value in a decreasing manner, the first voltage output by the converting circuit 200 when receiving the second input signal is not stepped down instantaneously but is stepped down within a certain time, the clamping circuit 300 outputs the clamping current according to the first voltage, the clamping current is used as the current output by the output circuit 400 when the output circuit 400 makes the output circuit 400 equal to the clamping current, and the output circuit 400 outputs the voltage analog quantity according to the clamping current, the analog quantity of the voltage outputted by the output circuit 400 when the first input signal is received by the conversion circuit 200 is increased with the increase of the first voltage, the analog quantity of the voltage outputted by the output circuit 400 when the second input signal is received by the conversion circuit 200 is decreased with the decrease of the first voltage, therefore, it takes a certain time for the analog quantity of the voltage output by the digital-to-analog conversion circuit 200 of the present embodiment to rise and fall, in addition, the first current output by the power supply circuit 100 can be amplified and converted into the clamping current through the conversion circuit 200 and the clamping circuit 300, so that a single small current (first current) is amplified to output a large current (clamping current), and the amplification of the output voltage analog quantity is realized, and the problems of difficult matching of a plurality of small current sources, high matching cost of the plurality of small current sources and poor performance caused by low matching degree of the plurality of small currents in the conventional scheme are solved.
The increasing speed of the voltage value of the first voltage from the first value to the second value can be consistent or can be changed, the decreasing speed of the voltage value of the first voltage from the second value to the first value can be consistent or can be changed, and the changing speed of the voltage value of the first voltage from the first value to the second value can be the same as or different from the changing speed of the voltage value of the first voltage from the second value to the first value.
Referring to fig. 2, in one embodiment, the converting circuit 200 includes a switching circuit 210 and a current-to-voltage circuit 220.
The switching circuit 210 is configured to output a second current and a third current according to the first current, control a current value of the second current to decrease from a third value to zero and a current value of the third current to increase from zero to the third value when the first input signal is received, and control a current value of the second current to increase from zero to the third value and a current value of the third current to decrease from the third value to zero when the second input signal is received.
And a current-to-voltage circuit 220 connected to the switching circuit 210 and configured to output a first voltage according to the second current and the third current.
When the current value of the second current is zero and the current value of the third current is a third value, the voltage value of the first voltage is a first value, and when the current value of the second current is the third value and the current value of the third current is zero, the voltage value of the first voltage is a second value.
In this embodiment, the switch circuit 210 divides the first current into the second current and the third current, the switch circuit 210 controls the output current value of the second current to decrease from the third value to zero and the output current value of the third current to increase from zero to the third value when receiving the first input signal, the switch circuit 210 controls the output current value of the second current to increase from zero to the third value and the output current value of the third current to decrease from the third value to zero when receiving the second input signal, and the current-to-voltage circuit 220 outputs the first voltage according to the second current and the third current because the ratio of the current-to-voltage circuit 220 to the voltage converted from the second current and the third current is different, and therefore when the second current and the third current are changed, the first voltage output by the current-to-voltage circuit 220 is also changed.
The third value is a current value of the first current, and the third value is actually smaller than the current value of the first current in consideration of a certain loss of the current value of the first current after passing through the switching circuit 210.
Referring to fig. 3, in one embodiment, the switch circuit 210 includes a first switch element 230 and a second switch element 240.
The first switch assembly 230 is configured to output a second current according to the first current, control a current value of the second current to decrease from a third value to zero when receiving the first input signal, and control a current value of the second current to increase from zero to the third value when receiving the second input signal.
The second switch component 240 is configured to output a third current according to the first current, control a current value of the third current to be incremented from zero to a third value when the first input signal is received, and control a current value of the third current to be decremented from the third value to zero when the second input signal is received.
In this embodiment, the first switch element 230 outputs the second current according to the first current, the first switch element 230 controls the output current value of the second current to decrease from a third value to zero when receiving the first input signal, the first switch element 230 controls the output current value of the second current to increase from zero to a third value when receiving the second input signal, the second switch element 240 outputs the third current according to the first current, the second switch element 240 controls the output current value of the third current to increase from zero to a third value when receiving the first input signal, when the current value of the third current outputted by the control unit is decreased from the third value to zero when the second input signal is received, the first switching component 230 realizes the control of the change and time required by the change of the current value of the second current, and the second switching component 240 realizes the control of the change and time required by the change of the current value of the third current.
Referring to fig. 4, in an embodiment, the first input signal includes N sequential signals, the second input signal includes N clock signals, the first switch element 230 includes N switch units (indicated by 231 … 23N), and the second switch element 240 includes N switch elements (indicated by 241 … 24N).
The Lth switching unit is configured to be turned on when the Lth timing signal is input and output the Lth branch current according to the first current, and to be turned off when the Lth clock signal is input.
The Lth switching element is configured to be turned off when the Lth timing signal is input, to be turned on when the Lth clock signal is input, and to output the Lth shunt current according to the first current.
All branch currents form second currents, and the shunt currents form third currents;
n is an integer of 2 or more, and L is a positive integer of N or less.
In this embodiment, N timing signals are sequentially input to the N switching units and the N switching elements at intervals, the L-th switching unit is turned on when the L-th timing signal is input, and outputs an L-th branch current according to a first current, and the L-th switching unit essentially has impedance when turned on, so that the turned-on L-th switching unit divides the first current to generate an L-th branch current, all branch currents are added up to form a second current, the L-th switching unit is turned on when the L-th clock signal is input, and outputs an L-th branch current according to the first current, and the L-th switching element essentially has impedance when turned on, so that the turned-on L-th switching element divides the first current to generate an L-th branch current, and all branch currents are added up to form a third current, so that the N switching units and the N switching elements realize the distribution of the first current to the second current and the third current and the gradual control of the second current and the third current And (4) changing.
Referring to fig. 5, in an embodiment, the lth switching unit includes an lth fet (denoted by reference numeral Q1 … Qn in the figure), and the lth switching element includes an lth unipolar transistor (denoted by reference numeral Qn +1 … Q2n in the figure).
The input end of the L-th field effect transistor is connected to the first current input end of the L-th switch unit, the output end of the L-th field effect transistor is connected to the second current output end of the L-th switch unit, and the enabling end of the L-th field effect transistor is connected to the L-th time sequence signal input end and the L-th clock signal input end of the L-th switch unit.
An input end of the L unipolar transistor is connected to a first current input end of the L switching element, an output end of the L unipolar transistor is connected to a third current output end of the L switching element, and a control end of the L unipolar transistor is connected to an L time sequence signal input end and an L clock signal input end of the L switching element.
Referring to fig. 5, in an embodiment, the current-to-voltage circuit 220 includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a second capacitor C2.
The first end of the first resistor R1, the first end of the second resistor R2, and the first end of the third resistor R3 are connected in common, the first end of the first resistor R1 and the first end of the first capacitor C1 are connected to the second current input terminal of the current-to-voltage circuit 220, the first end of the second resistor R2 is connected to the first end of the second capacitor C2 and the third current input terminal and the first voltage output terminal of the current-to-voltage circuit 220, and the second end of the first capacitor C1, the second end of the second capacitor C2, and the second end of the third resistor R3 are all connected to ground.
Referring to fig. 5, in an embodiment, the clamp circuit 300 includes an operational amplifier U1, a first Metal Oxide Semiconductor (MOS) transistor M1, and a fourth resistor R4.
The positive phase input end of the operational amplifier U1 is connected to the first voltage input end of the clamp circuit 300, the negative phase input end of the operational amplifier U1, the first end of the fourth resistor R4 and the source of the first MOS transistor M1 are connected in common, the output end of the operational amplifier U1 is connected to the gate of the first MOS transistor M1, the second end of the fourth resistor R4 is connected to the power ground and to the clamp current output end of the clamp circuit 300, and the drain of the first MOS transistor M1 is connected to the clamp current input end of the clamp circuit 300.
Referring to fig. 5, in an embodiment, the output circuit 400 includes a second MOS transistor M2 and a fifth resistor R5.
The gate of the second MOS transistor M2 is connected to the working signal input terminal of the output circuit 400, the source of the second MOS transistor M2 is connected to the clamping current output terminal of the output circuit 400, the drain of the second MOS transistor M2 is connected to the first end of the fifth resistor R5 and to the voltage analog output terminal of the output circuit 400, and the second end of the fifth resistor R5 is connected to the internal power supply.
The digital-to-analog conversion circuit 200 shown in fig. 5 is described below with reference to the operation principle, when N high levels (clock signals) are sequentially applied to the N field-effect transistors and the N unipolar transistors, the N field-effect transistors are sequentially turned off, the N unipolar transistors are sequentially turned on, when all of the N field-effect transistors are turned off and all of the N unipolar transistors are turned on, a first current output by the current source a1 flows through the N unipolar transistors and outputs a third current at the sources of the N unipolar transistors, the third current is output to the ground via the second resistor R2 and the third resistor R3, and the third current forms a first voltage under the voltage division effect of the second resistor R2 and the third resistor R3 and is output to the positive input terminal of the operational amplifier U1, because the output terminal of the operational amplifier U1 is connected to the gate of the first MOS transistor M1 and the source of the first MOS transistor M1, the negative input terminal of the operational amplifier U1, and the first terminal of the fourth resistor R4 are connected together, the clamp voltage output by the output end of the operational amplifier U1 acts on the fourth resistor R4, the clamp current flowing through the fourth resistor R4 under the action of the clamp voltage is equal to the clamp voltage divided by the fourth resistor R4, and at the same time, when the second MOS transistor M2 has an operating signal input, the internal power supply and the second MOS transistor M2 are turned on, at this time, the fifth resistor R5, the second MOS transistor M2, the first MOS transistor M1 and the fourth resistor R4 form a loop, because the current flowing through the fourth resistor R4 is the clamp current, the current value of the whole loop is clamped to the clamp current, at this time, the voltage analog quantity output through the second end of the fifth resistor R5 is equal to the voltage analog quantity of the internal power supply minus the divided voltage on the fifth resistor R5.
When N low levels (timing signals) are sequentially input to the N field effect transistors and the N unipolar transistors instead of the N high levels, the N field effect transistors are sequentially turned on, the N unipolar transistors are sequentially turned off, when the N field effect transistors are sequentially turned on and the N unipolar transistors are sequentially turned off, the resistances of the N field effect transistors become large, and the resistances of the N unipolar transistors become small, so that a second current formed by the first current flowing through the N field effect transistors increases progressively, a third current formed by the first current flowing through the N unipolar transistors decreases progressively, the second current flows through the first resistor R1 and the third resistor R3 and is grounded, the third current flows through the second resistor R2 and the third resistor R3 and is grounded, the second current forms and outputs a second voltage under the action of the third resistor R3, the second voltage is equal to the voltage division of the second current on the third resistor R3, and the third current forms and outputs a third voltage under the action of the second resistor R2 and the third resistor R3, the third voltage is equal to the divided voltage of the third current on the second resistor R2 and the third resistor R3, the second voltage plus the third voltage is equal to the first voltage, because the numerical ratio of the second current to the second voltage is smaller than the numerical ratio of the third current to the third voltage, under the condition that the total current value of the second current and the third current is not changed, the larger the second current is, the smaller the first voltage is, the first voltage is decreased when the N field effect transistors are sequentially turned on and the N unipolar transistors are sequentially turned off, so the finally output voltage analog quantity is also decreased, similarly, when the N high levels are sequentially input to the N unipolar field effect transistors and the N unipolar transistors instead of the N low levels, the finally output voltage analog quantity is increased, wherein the minimum ratio of the clamping current of the fourth resistor R4 to the first current depends on the ratio resistance value of the first resistor R1 to the fourth resistor R4, the maximum ratio of the clamping current of the fourth resistor R4 to the first current depends on the ratio of the sum of the resistances of the second resistor R2 and the third resistor R3 to the resistance of the fourth resistor R4, for example, when the sum of the resistances of the second resistor R2 and the third resistor R3 is ten times larger than the resistance of the fourth resistor R4, the clamping current can reach ten times larger than the first current at most, and in the manufacturing process, the precision of the resistance of the resistor is easier to control than that of the output current of the current source a1, so the precision of the resistance of the resistor is easier to be made high and the cost is low, and therefore, the precision of the clamping current controlled to be output by the proportional relation of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 is high and the cost is low, thereby improving the precision of the digital-to-analog conversion circuit 200 and reducing the cost.
In one embodiment, the time for the voltage value of the first voltage to increase from the first value to the second value is 3-5 ns, and the time for the voltage value of the first voltage to decrease from the second value to the first value is 3-5 ns.
In this embodiment, the time for the voltage value of the first voltage to increase from the first value to the second value is 3-5 ns, and the time for the voltage value of the first voltage to decrease from the second value to the first value is 3-5 ns, so that the rising and falling time of the voltage analog output by the digital-to-analog conversion circuit 200 both meet the protocol requirements.
The present embodiment further provides a digital-to-analog converter, which includes the digital-to-analog conversion circuit 200 according to any of the above embodiments, because the digital-to-analog converter of the present embodiment includes the digital-to-analog conversion circuit 200 according to any of the above embodiments, the digital-to-analog converter of the present embodiment at least has the corresponding advantages of the digital-to-analog conversion circuit 200 according to any of the above embodiments.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A digital-to-analog conversion circuit, comprising:
a power supply circuit configured to output a first current;
the conversion circuit is connected with the power supply circuit and configured to output a first voltage according to the first current, the voltage value of the first voltage ranges from a first value to a second value, the voltage value of the first voltage is increased from the first value to the second value when a first input signal is received, and the voltage value of the first voltage is decreased from the second value to the first value when a second input signal is received;
the clamping circuit is connected with the conversion circuit and is configured to output a clamping current according to the first voltage; and
and the output circuit is connected with the clamping circuit and is configured to output voltage analog quantity according to the clamping current.
2. The digital-to-analog conversion circuit of claim 1, wherein the conversion circuit comprises:
the switching circuit is configured to output a second current and a third current according to the first current, control the current value of the second current to decrease from a third value to zero and control the current value of the third current to increment from zero to the third value when the first input signal is received, and control the current value of the second current to increment from zero to the third value and control the current value of the third current to decrease from the third value to zero when the second input signal is received; and
a current-to-voltage circuit connected to the switching circuit and configured to output the first voltage according to the second current and the third current;
wherein the voltage value of the first voltage is the first value when the current value of the second current is zero and the current value of the third current is the third value, and the voltage value of the first voltage is the second value when the current value of the second current is the third value and the current value of the third current is zero.
3. The digital-to-analog conversion circuit of claim 2, wherein the switching circuit comprises a first switching component and a second switching component;
the first switch assembly is configured to output the second current according to the first current, control a current value of the second current to decrease from the third value to zero when the first input signal is received, and control a current value of the second current to increase from zero to the third value when the second input signal is received;
the second switch assembly is configured to output the third current according to the first current, control a current value of the third current to be increased from zero to the third value when the first input signal is received, and control a current value of the third current to be decreased from the third value to zero when the second input signal is received.
4. The digital-to-analog conversion circuit according to claim 3, wherein the first input signal includes N timing signals sequentially input, the second input signal includes N clock signals sequentially input, the first switching element includes N switching cells, and the second switching element includes N switching elements;
the Lth switching unit is configured to be turned on when an Lth timing signal is input and output an Lth branch current according to the first current, and to be turned off when an Lth clock signal is input;
the Lth switching element is configured to be turned off when an Lth timing signal is input, to be turned on when an Lth clock signal is input, and to output an Lth shunt current according to the first current;
wherein all branch currents constitute the second current and the branch currents constitute the third current;
n is an integer of 2 or more, and L is a positive integer of N or less.
5. The digital-to-analog conversion circuit according to claim 4, wherein the Lth switching unit includes an Lth field effect transistor, and the Lth switching element includes an Lth unipolar transistor;
the input end of the L-th field effect transistor is connected to the first current input end of the L-th switch unit, the output end of the L-th field effect transistor is connected to the second current output end of the L-th switch unit, and the enable end of the L-th field effect transistor is connected to the L-th time sequence signal input end and the L-th clock signal input end of the L-th switch unit;
an input end of the L-th unipolar transistor is connected to a first current input end of the L-th switching element, an output end of the L-th unipolar transistor is connected to a third current output end of the L-th switching element, and a control end of the L-th unipolar transistor is connected to an L-th timing signal input end and an L-th clock signal input end of the L-th switching element.
6. The digital-to-analog conversion circuit of claim 2, wherein the current-to-voltage conversion circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor;
the first end of the first resistor, the first end of the second resistor and the first end of the third resistor are connected in common, the first end of the first resistor and the first end of the first capacitor are connected and connected to the second current input end of the current-to-voltage circuit, the first end of the second resistor and the first end of the second capacitor are connected and connected to the third current input end and the first voltage output end of the current-to-voltage circuit, and the second end of the first capacitor, the second end of the second capacitor and the second end of the third resistor are all connected with a power ground.
7. The digital-to-analog conversion circuit of claim 1, wherein the clamping circuit comprises an operational amplifier, a first MOS transistor, and a fourth resistor;
the positive phase input end of the operational amplifier is connected to the first voltage input end of the clamping circuit, the negative phase input end of the operational amplifier, the first end of the fourth resistor and the source electrode of the first MOS tube are connected in common, the output end of the operational amplifier is connected with the grid electrode of the first MOS tube, the second end of the fourth resistor is connected with the power ground and connected to the clamping current output end of the clamping circuit, and the drain electrode of the first MOS tube is connected to the clamping current input end of the clamping circuit.
8. The digital-to-analog conversion circuit according to claim 1, wherein the output circuit includes a second MOS transistor and a fifth resistor;
the grid electrode of the second MOS tube is connected to the working signal input end of the output circuit, the source electrode of the second MOS tube is connected to the clamping current output end of the output circuit, the drain electrode of the second MOS tube is connected with the first end of the fifth resistor and connected to the voltage analog output end of the output circuit, and the second end of the fifth resistor is connected with an internal power supply.
9. The digital-to-analog conversion circuit of claim 1, wherein the time for the voltage value of the first voltage to increase from the first value to the second value is 3-5 ns, and the time for the voltage value of the first voltage to decrease from the second value to the first value is 3-5 ns.
10. A digital-to-analog converter comprising a digital-to-analog conversion circuit as claimed in any one of claims 1 to 9.
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| CN113805843A (en) * | 2021-09-24 | 2021-12-17 | 上海集成电路装备材料产业创新中心有限公司 | Maximum value solving circuit and maximum value solving method |
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| CN112583412B (en) | 2024-03-19 |
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