CN115842550A - Current steering digital-to-analog converter and high-frequency linearity improving method thereof - Google Patents
Current steering digital-to-analog converter and high-frequency linearity improving method thereof Download PDFInfo
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Abstract
The invention provides a current-steering digital-to-analog converter and a high-frequency linearity improving method thereof.A cascode transistor which is connected in series is additionally arranged between a tail current source transistor and a switch pair transistor, and an effective cascode transistor which is connected in series is additionally arranged between the switch pair transistor and a differential analog output end of the current-steering digital-to-analog converter, so that the output impedance of a current switch unit can be increased, and the nonlinearity caused by an input digital modulation effect due to the limited output impedance can be reduced; meanwhile, the direct current bias current source provides direct current bias current for the effective cascode transistor, so that the effective cascode transistor is always kept on, nonlinear influence related to input codes caused by parasitic capacitance when the effective cascode transistor is completely disconnected can be avoided, and the linearity of a current switch unit of the current steering digital-to-analog converter and the linearity of the current steering digital-to-analog converter under high frequency are improved.
Description
Technical Field
The invention relates to the technical field of digital-to-analog converters, in particular to a current steering digital-to-analog converter and a high-frequency linearity improving method thereof.
Background
The current steering digital-to-analog converter is composed of a plurality of current switch units, each current switch unit is composed of a pair of switches and a tail current source, and a pair of differential digital signals obtained from digital signals input by the current steering digital-to-analog converter respectively control the on and off of the two switches, so that the tail current source can be determined to flow through one of the two switches. The differential output end of the current steering digital-to-analog converter is formed by connecting the output ends of a plurality of current switch units in parallel, and the current switch units generally drive a load resistor respectively, so that the impedance seen from the output end is the parallel connection of the output impedance and the load resistor, and the magnitude of the output impedance depends on the parallel connection number of the opened current switch units and is related to the input digital code. The impedance of an ideal current source is infinite, whereas the impedance of an actual current source cannot be infinite. Therefore, the total finite output impedance of the current-steering digital-to-analog converter affects its linearity, resulting in harmonic distortion.
At present, a cascode structure is generally adopted to improve the total output impedance of the current steering digital-to-analog converter, the improved cascode structure improves the output resistance, and can reduce the influence of parasitic capacitance from other transistors on the dynamic performance, however, the added cascode transistors also bring the parasitic capacitance from the cascode transistors, and an input digital code with high speed change can directly feed through to a differential analog output end through the parasitic capacitance to generate nonlinearity related to the input digital code, which becomes the main limit of the output impedance of the current steering digital-to-analog converter current switch unit at high frequency.
Therefore, a technical solution is needed to reduce the nonlinear effect related to the input digital code caused by the parasitic capacitance of the cascode stage transistor in the current steering dac.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a technical solution of a current steering dac, wherein for a current switch unit of the current steering dac, a cascode transistor is added in series between a tail current source transistor and a switch pair transistor, and a cascode transistor is added in series between the switch pair transistor and a differential analog output terminal of the current steering dac, so as to increase an output impedance of the current switch unit, so as to reduce nonlinearity caused by an input digital modulation effect due to a limited output impedance; meanwhile, direct current bias current is provided for the effective cascode transistor, so that the effective cascode transistor is always kept on, and nonlinear influence related to input codes caused by parasitic capacitance of the effective cascode transistor is reduced.
In order to achieve the above objects and other related objects, the present invention provides the following technical solutions.
A current steering digital-to-analog converter comprises a tail current source transistor, a cascode transistor, a first switch tube, a second switch tube, a first effective cascode transistor, a second effective cascode transistor, a direct current bias current source and two load resistors, wherein the source electrode of the tail current source transistor is grounded, the grid electrode of the tail current source transistor is connected with a first bias voltage, the drain electrode of the tail current source transistor is connected with the source electrode of the cascode transistor, the grid electrode of the cascode transistor is connected with a second bias voltage, the drain electrode of the cascode transistor is connected with the source electrode of the first switch tube, the grid electrode of the first switch tube is connected with a first digital signal, the drain electrode of the first switch tube is connected with the source electrode of the first effective cascode transistor, and the source electrode of the first effective cascode transistor is also connected with a first output end of the direct current bias current source, the gate of the first effective cascode transistor is connected to a third bias voltage, the drain of the first effective cascode transistor is connected to a working voltage through one of the load resistors connected in series, the drain of the first effective cascode transistor is the positive end of the differential analog output of the current switching unit of the current steering digital-to-analog converter, the source of the second switching tube is connected to the source of the first switching tube, the gate of the second switching tube is connected to the second digital signal, the drain of the second switching tube is connected to the source of the second effective cascode transistor, the source of the second effective cascode transistor is further connected to the second output end of the dc bias current source, the gate of the second effective cascode transistor is connected to the third bias voltage, and the drain of the second effective cascode transistor is connected to the working voltage through the other load resistor connected in series The drain electrode of the second effective cascode transistor is the negative end of the differential analog output of the current switch unit of the current steering digital-to-analog converter; the direct current bias current source provides a first direct current bias current for the first effective cascode transistor, and the direct current bias current source provides a second direct current bias current for the second effective cascode transistor, so that the first effective cascode transistor and the second effective cascode transistor are always kept on.
Optionally, the tail current source transistor, the cascode stage transistor, the first switching tube, the second switching tube, the first effective cascode stage transistor, and the second effective cascode stage transistor are all NMOS tubes.
Optionally, the first switching tube has the same parameter specification as the second switching tube, and the first active cascode stage transistor has the same parameter specification as the second active cascode stage transistor.
Optionally, the size of the first switching tube is smaller than the size of the first effective cascode stage transistor.
Optionally, the dc bias current source includes a buffer amplifier, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor, wherein a source of the first NMOS transistor is grounded, a gate of the first NMOS transistor is connected to the first bias voltage, a drain of the first NMOS transistor is connected to a source of the third NMOS transistor, a gate of the third NMOS transistor is connected to the second bias voltage, a drain of the third NMOS transistor is connected to a source of the fifth NMOS transistor, a gate of the fifth NMOS transistor is connected to an output end of the buffer amplifier, a non-inverting input terminal of the buffer amplifier is connected to the output end of the buffer amplifier, a source of the second NMOS transistor is grounded, a gate of the second NMOS transistor is connected to the first bias voltage, a drain of the second NMOS transistor is connected to a source of the fourth NMOS transistor, a gate of the fourth NMOS transistor is connected to the second bias voltage, a drain of the fourth NMOS transistor is connected to a source of the sixth NMOS transistor, and a gate of the buffer amplifier is connected to the output end of the sixth NMOS transistor; the drain electrode of the fifth NMOS tube is a first output end of the direct current bias current source, and the drain electrode of the sixth NMOS tube is a second output end of the direct current bias current source.
Optionally, the first NMOS transistor has the same specification as the second NMOS transistor, the third NMOS transistor has the same specification as the fourth NMOS transistor, and the fifth NMOS transistor has the same specification as the sixth NMOS transistor.
Optionally, the size of the first NMOS transistor is larger than the size of the third NMOS transistor, and the size of the third NMOS transistor is larger than the size of the fifth NMOS transistor.
A high-frequency linearity improving method of a current steering digital-to-analog converter comprises the following steps:
aiming at least one current switch unit of the current steering digital-to-analog converter, a cascode transistor connected in series is additionally arranged between a tail current source transistor and a switch pair transistor, and a series effective cascode transistor is additionally arranged between the switch pair transistor and a differential analog output end of the current steering digital-to-analog converter so as to increase the output impedance of the current switch unit;
and aiming at least one current switch unit of the current steering digital-to-analog converter, providing direct current bias current for the effective cascode transistor so as to enable the effective cascode transistor to be always kept on.
As described above, the current-steering dac and the high-frequency linearity improving method thereof provided by the present invention have at least the following advantages:
the cascade stage transistor is additionally connected between the tail current source transistor and the first switch tube as well as the second switch tube, the first effective cascade stage transistor is additionally connected between the first switch tube and the differential analog output positive end of the current steering digital-to-analog converter, and the second effective cascade stage transistor is additionally connected between the second switch tube and the differential analog output negative end of the current steering digital-to-analog converter, so that the output impedance of the current switch unit can be effectively increased, and the nonlinearity caused by the input digital modulation effect due to the limited output impedance can be reduced; meanwhile, a first direct current bias current is provided for the first effective cascode transistor through the direct current bias current source, and a second direct current bias current is provided for the second effective cascode transistor, so that the first effective cascode transistor and the second effective cascode transistor are always kept on, nonlinear influences related to input codes caused by parasitic capacitance when the first effective cascode transistor and the second effective cascode transistor are completely disconnected can be effectively avoided, and the linearity of the current steering digital-to-analog converter is improved.
Drawings
Fig. 1 shows a schematic diagram of a conventional current steering dac current switching cell.
Fig. 2 shows a schematic diagram of the output impedance of a current steering dac with a thermometer decoding structure.
Fig. 3 is a schematic diagram of a conventional current steering dac core cell circuit.
Fig. 4 shows an amplitude-frequency curve of the output impedance of the current-steering dac core unit in fig. 3 as a function of the signal frequency.
Fig. 5 shows a schematic diagram of a cascode structure current-steering digital-to-analog converter core cell circuit.
Fig. 6 shows a partial schematic diagram of a current steering dac according to the present invention.
Fig. 7 is a schematic diagram of the dc bias current source of fig. 6.
Fig. 8 is a schematic diagram of the dynamic parasitic capacitance of the current switch cell of fig. 6.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. The structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are for understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined in the claims, and are not essential to the art, and any structural modifications, changes in proportions, or adjustments in size, which do not affect the efficacy and attainment of the same are intended to fall within the scope of the present disclosure.
As mentioned in the background, the current-steering DAC consists of a plurality of current switch units, each of which is configured as shown in FIG. 1 and includes a pair of switches S1 and S2 and a tail current source I O A pair of differential digital signals DN/DP obtained from the digital signals input by the current steering digital-to-analog converter respectively control the on-off of the switches S1 and S2, thereby determining the tail current source I O Is through switch S1 or switch S2. As shown in fig. 1, the differential output V of the current steering dac OUT Comprising a plurality of current switching units, the outputs of which are connected in parallel and each of which usually drives a load resistor R L Load resistance R L One end ofWorking voltage V CC Two load resistors R L The other ends of the two are respectively differential output ends V OUT Positive terminal OUT of P Negative terminal OUT N . Thus, from the differential output terminal V OUT The impedance seen is the output impedance Z DAC And a load resistance R L Due to the output impedance Z DAC Is dependent on the number of parallel connected current switch cells that are switched on and is related to the input digital code of the current steering digital-to-analog converter. Ideal tail current source I O Is infinite, and the actual tail current source I O Cannot be infinite, as shown in fig. 1, tail current source I O Impedance Z of O Comprising an equivalent resistance R O And an equivalent capacitance C O Two parts of impedance Z O And is limited. Therefore, the total finite output impedance of the current steering dac affects its linearity, resulting in harmonic distortion.
On one hand, taking the output impedance of the current steering dac with one thermometer decoding structure shown in fig. 2 as an example, the total number of current switch units is N, fig. 2 shows the relationship between the output impedance and the input signal, where x represents the digital input code, zo represents the output impedance of the current switch units (including the equivalent capacitor Co and the equivalent resistor Ro), and Z represents L Meter load resistance R L The impedance of (c). According to the circuit structure, the differential output voltage of the current steering digital-to-analog converter can be calculated as follows:
further develop equation (1):
taylor expansion of equation (2) at x =0 yields:
after expansion according to the power series, the three-order harmonic distortion formula is obtained:
for a differential output current-steering dac, the output major harmonic component is the third harmonic, and therefore, the response of the Dynamic error of the current-steering dac due to the limited output impedance of the current-steering dac is SFDR (sparse Free Dynamic range):
at low frequencies, the output impedance of the current steering dac is mainly determined by the equivalent resistance Ro, i.e.:
it can be seen from equation (6) that at low frequencies, the influence of the output impedance of the current steering dac on SFDR does not change with the signal frequency. From this point of view, the effect of the finite output impedance at low frequencies on the current-steering digital-to-analog converter can be attributed to the static error INL (Integral Nonlinearity). The influence of the finite output resistance on the INL at low frequency is given by:
from equation (7), it can be seen that for a 12-bit resolution current steering DAC, the load resistance R is the same L At 25 Ω, the equivalent resistance Ro required to obtain an INL of 1LSB is about 100M Ω.
In the case of a high frequency, the output impedance of the current steering dac is mainly determined by its equivalent capacitance Co, and then:
f in formula (8) in Representing the input signal frequency. As can be seen from equation (8), SFDR decreases at a rate of-40 dB per frequency interval with increasing input signal frequency at high frequencies, and the value of the equivalent capacitance (or parasitic capacitance) Co of the tail current source needs to be reduced to improve the dynamic performance of the current-steering dac.
On the other hand, taking the conventional current steering dac core cell circuit shown in fig. 3 as an example, the switches S1 and S2 in fig. 1 adopt an NMOS transistor N in fig. 3 1 And N 2 Implementation, tail current source I in FIG. 1 O In FIG. 3, NMOS transistor N is used 3 Implementation, assuming a switch tube N l And N 2 Respectively, of output impedances r o1 And r o2 ，r o1 ＝r o2 Transconductance is g m Tail current source tube N 3 Has an output impedance of r o3 The parasitic capacitance at the common source point A of the switch pair tube is C A . Parasitic capacitance C at point A A Comprises a transistor N 3 And the line capacitance between each other. When the switch tube N l When conducting, the output impedance of the switch current unit is Z DAC(CELL) Comprises the following steps:
the output impedance Z of the switching current unit can be drawn according to the formula (9) DAC(CELL) Dependent on the input signal f in The amplitude-frequency curve of the frequency change is shown in fig. 4, and it can be seen from fig. 4 that the output impedance Z of the current steering dac switching current cell DAC(CELL) Has a pole l/(2 π r) o3 C A ) When the signal frequency is greater than this pole, the output impedance Z DAC(CELL) Decreasing, the SFDR gradually deteriorates. Although the parasitic capacitance of the connecting line can be reduced by a reasonable layout method, the effect is limited.
Meanwhile, with the progress of process technology, the channel length modulation effect further obviously limits the output of a single transistorOutput impedance r o Value, therefore, in order to improve the accuracy and dynamic performance of the current-steering dac, the output impedance Z of the current-steering dac core cell needs to be increased DAC(CELL) 。
At present, a cascode structure is usually adopted to improve the total output impedance of the current steering digital-to-analog converter, as shown in fig. 5, in the current switch unit, the NMOS transistor N is connected to the switch pair transistor 1 And N 2 To the differential output terminal V OUT Are respectively connected in series with an NMOS tube N 5 And N 6 Active Cascode stage (Active _ Cascode) as current switch unit, and NMOS transistor N as pair transistors 1 And N 2 Source to tail current source transistor N 3 An NMOS tube N is connected in series between the drain electrodes 4 As Cascode stage (Cascode) of the current switch unit, the output impedances of all NMOS transistors in fig. 5 and 3 are simplified to r o Transconductance is g m Then, the output impedance Z of the current switching cell at low frequency DAC(CELL) From g of the original FIG. 3 m ×r o 2 G added to FIG. 5 m 3 ×r o 4 . Thus, the improved cascode structure increases the output resistance of the current switching cell, and the increased effective cascode stage reduces the current steering DAC dynamics from N 1 ～N 4 The effect of the parasitic capacitance of the tube, however, the added effective cascode stage also brings parasitic capacitance from themselves (N) 5 、N 6 C of the pipe GS Capacitance and C GD Capacitance), the input number of the current steering digital-to-analog converter with high-speed change can pass through N 5 、N 6 Parasitic capacitance of the tube, directly feed-through to the differential analog output V OUT The non-linearity associated with the input digital code is generated and becomes the main limitation of the output impedance of the current switching unit of the current steering digital-to-analog converter at high frequency.
Wherein, the NMOS transistor N 1 There is a parasitic capacitance C GS1 And C GD1 N, NMOS tube 2 There is a parasitic capacitance C GS2 And C GD2 NMOS transistor N 3 There is a parasitic capacitance C GS3 And C GD3 N, NMOS tube 4 There is a parasitic capacitance C GS4 And C GD4 NMOS transistor N 5 There is a parasitic capacitance C GS5 And C GD5 NMOS transistor N 6 There is a parasitic capacitance C GS6 And C GD6 。
Therefore, the invention provides a technical scheme for reducing the nonlinear influence related to an input digital code caused by the parasitic capacitance of a cascode transistor in a current steering digital-to-analog converter, which comprises the following steps: a cascode transistor connected in series is additionally arranged between the tail current source transistor and the switch pair transistor, and an effective cascode transistor connected in series is additionally arranged between the switch pair transistor and the differential analog output end of the current steering digital-to-analog converter so as to increase the output impedance of the current switch unit and further reduce the nonlinearity caused by the modulation effect of input codes due to the limited output impedance; meanwhile, a direct current bias current is provided for the effective cascode transistor through the direct current bias current source, so that the effective cascode transistor is always kept on, nonlinear influences related to input codes caused by parasitic capacitance when the effective cascode transistor is completely disconnected are avoided, and the linearity of a current switch unit of the current steering digital-to-analog converter and the linearity of the current steering digital-to-analog converter are improved.
First, as shown in fig. 6, the present invention provides a current steering dac comprising a tail current source transistor N 3 Cascode stage transistor N 4 A first switch tube N 1 A second switch tube N 2 A first active cascode transistor N 5 Second active cascode stage transistor N 6 DC bias current source I 1 And two load resistors R L Tail current source transistor N 3 Is grounded, and a tail current source transistor N 3 Is connected with a first bias voltage V CS Tail current source transistor N 3 Is connected with the drain electrode of the cascode stage transistor N 4 Source of (2), cascode stage transistor N 4 The grid of the first bias voltage is connected with a second bias voltage V CAS Cascode stage transistor N 4 The drain electrode of the first switch tube N 1 Source electrode of, first switching tube N 1 The gate of which is connected to the first digital signal DN,first switch tube N 1 Is connected to the first active cascode transistor N 5 First active cascode stage transistor N 5 The source of the transistor is also connected with a direct current bias current source I 1 First effective cascode stage transistor N 5 Is connected with a third bias voltage V CAS_active First active cascode stage transistor N 5 The drain electrode of the transistor is connected with a load resistor R in series L Connected downstream to a working voltage V CC Second switch tube N 2 Source electrode of the first switch tube N 1 Source electrode of, the second switching tube N 2 The grid of the first switch tube is connected with a second digital signal DP and the second switch tube N 2 Is connected to the second active cascode transistor N 6 Source of a second active cascode stage transistor N 6 The source of the transistor is also connected with a direct current bias current source I 1 Second effective cascode stage transistor N 6 Is connected with a third bias voltage V CAS_active Second active cascode stage transistor N 6 The drain of the transistor is connected in series with another load resistor R L Connected downstream to a working voltage V CC . Wherein, the DC bias current source I 1 Is a first active cascode stage transistor N 5 Providing a first DC bias current I OUT1 d.C. bias current source I 1 As a second active cascode stage transistor N 6 Providing a second DC bias current I OUT2 So that the first active cascode stage transistor N 5 And a second active cascode stage transistor N 6 And is always kept open.
Wherein, the tail current source transistor N 3 Cascode stage transistor N 4 A first switch tube N 1 A second switch tube N 2 A first effective cascode transistor N 5 Second active cascode stage transistor N 6 And a DC bias current source I 1 A current switch unit is formed, the whole current-steering digital-to-analog converter comprises a plurality of current switch units which are arranged in parallel, and the differential output end V of the current-steering digital-to-analog converter OUT Is formed by connecting the output ends of a plurality of current switch units in parallel, and the differential output end V of the current switch units OUT Respectively drives a load resistor R L 。
In detail, as shown in fig. 6, the tail current source transistor N 3 Cascode stage transistor N 4 A first switch tube N 1 The second switch tube N 2 A first active cascode transistor N 5 And a second active cascode stage transistor N 6 Are all NMOS tubes.
In more detail, as shown in fig. 6, the first bias voltage V CS A second bias voltage V as a first input terminal of the current switching unit CAS A third bias voltage V as a second input terminal of the current switching unit CAS_active Is the third input terminal of the current switch unit, the first digital signal DN is the fourth input terminal of the current switch unit, the second digital signal DP is the fifth input terminal of the current switch unit, the first effective cascode transistor N 5 Is the sixth input terminal of the current switching unit, a second active cascode transistor N 6 Is the seventh input terminal of the current switching unit, a first active cascode transistor N 5 Has a drain electrode as a first output terminal of the current switching unit, and a second effective cascode transistor N 6 Is the second output terminal of the current switching unit.
In more detail, as shown in fig. 6, the first switch tube N 1 Parameter specification and second switch tube N 2 Is equal to the parameter specification of the first active cascode stage transistor N 5 And the second active cascode stage transistor N 6 The parameter specifications of the components are the same; first switch tube N 1 Is smaller than the first active cascode stage transistor N 5 The size of (c).
In detail, as shown in fig. 7, in an alternative embodiment of the present invention, a dc bias current source I 1 Comprises a buffer amplifier A1 and a first NMOS transistor N 9 A second NMOS transistor N 10 And a third NMOS transistor N 11 And a fourth NMOS transistor N 12 The fifth NMOS transistor N 13 And a sixth NMOS transistor N 14 First NMOS transistor N 9 The source electrode of the first NMOS tube N is grounded 9 The grid electrode of the grid electrode is connected with a first biasSet voltage V CS First NMOS transistor N 9 Drain electrode of the first NMOS transistor is connected with a third NMOS transistor N 11 Source electrode of (1), third NMOS transistor N 11 Is connected with a second bias voltage V CAS Third NMOS transistor N 11 Drain electrode of the NMOS transistor is connected with a fifth NMOS transistor N 13 Source electrode of (1), fifth NMOS transistor N 13 The grid of the buffer amplifier A1 is connected with the output end of the buffer amplifier A1, the non-inverting input end of the buffer amplifier A1 is connected with the fourth bias voltage 1.2V, the inverting input end of the buffer amplifier A1 is connected with the output end of the buffer amplifier A1, and the second NMOS tube N 10 The source electrode of the first NMOS tube N is grounded, and the second NMOS tube N 10 Is connected with a first bias voltage V CS Second NMOS transistor N 10 Drain electrode of the NMOS transistor is connected with a fourth NMOS transistor N 12 Source electrode of (1), fourth NMOS transistor N 12 Is connected with a second bias voltage V CAS Fourth NMOS transistor N 12 Drain electrode of the first NMOS transistor is connected with a sixth NMOS transistor N 14 Source electrode of (1), sixth NMOS tube N 14 Is connected to the output terminal of the buffer amplifier A1.
Wherein, the first NMOS transistor N 9 A second NMOS transistor N 10 Is a tail current source transistor, a third NMOS transistor N 11 And a fourth NMOS transistor N 12 Is a cascode transistor, and the fifth NMOS transistor N 13 And a sixth NMOS transistor N 14 Is an active cascode stage transistor; first NMOS transistor N 9 The grid of the grid is a DC bias current source I 1 The third NMOS tube N 11 The grid of the grid is a DC bias current source I 1 The non-inverting input end of the buffer amplifier A1 is a DC bias current source I 1 The fifth NMOS transistor N 13 The drain electrode of the transistor is a direct current bias current source I 1 A first output terminal for outputting a first DC bias current I OUT1 Sixth NMOS transistor N 14 The drain electrode of the transistor is a direct current bias current source I 1 A second output terminal for outputting a second DC bias current I OUT2 。
In detail, the first NMOS transistor N 9 Parameter specification and second NMOS transistor N 10 Is the same as the parameter specification of the third NMOS tube N 11 Parameter specification and fourth NMOS transistor N 12 The same parameter specification, the fifth NMOS tube N 13 And sixth NMOS pipe N 14 The parameter specifications of the components are the same; first NMOS transistor N 9 Is larger than the third NMOS transistor N 11 Size of (d), third NMOS transistor N 11 Is larger than the fifth NMOS transistor N 13 The size of (c).
In an alternative embodiment of the invention, the operating voltage V CC Is 1.8V of power supply voltage, a first bias voltage V CS Has a value of 300mV to 400mV, and a second bias voltage V CAS Has a value of 700mV to 800mV and a third bias voltage V CAS_active The value of (1.5V) to (1.6V), the value of the fourth bias voltage is 1.2V, and the digital signals (i.e., the first digital signal DN and the second digital signal DP) of the current switch unit are complementary differential digital signals of 1.2V/0V.
In more detail, as shown in fig. 6 to 8, the operating principle of the current steering dac according to the present invention is analyzed as follows:
in a specific design of the current switching cell, the tail current source transistor N 3 The design size is larger, the W/L is designed to be 2 mu/0.4 mu, the number of the grids is 16, and the aim is mainly to consider the matching of the current source array; cascode stage transistor N 4 The design size is slightly smaller, the W/L is designed to be 0.8 mu/0.2 mu, the number of the grids is 2, and the aim is to support the first switch tube N 1 And a second switch tube N 2 The operating current of (2); first switch tube N 1 And a second switch tube N 2 The size of the gate is designed to be as small as possible, the W/L is designed to be 0.8 mu/0.06 mu, the number of the gates is 1, and the aim is mainly to consider higher conversion rate; first active cascode stage transistor N 5 Second active cascode stage transistor N 6 W/L is designed to be 1.0 mu/0.28 mu, the number of grids is 1, and the design aim is mainly to reduce the N from the first switching tube 1 A second switch tube N 2 Tail current source transistor N 3 And cascode stage transistor N 4 The parasitic resistance introduced, however, comes from the active cascode stage transistor (i.e., the first active cascode stage transistor N) 5 And a second active cascode stage transistor N 6 ) Parasitic capacitance of itself (C) GS And C GD ) The input digital of the current steering digital-to-analog converter controls the first switch tube N 1 And a second switch tube N 2 On or off, high speed varying input code through active cascode stage transistor N 5 And N 6 Parasitic capacitance (C) of GS And C GD ) Direct feed-through to the differential analog output V of the current-steering DAC OUT The non-linearity caused by the digital modulation effect is a major limitation of the output impedance of the current steering dac at high frequencies.
In order to obtain good linear characteristics of the current steering digital-to-analog converter at high frequency, the distortion caused by limited output impedance at high frequency is analyzed, mainly caused by the output impedance of the part which is actually conducted, and any non-conducted impedance (including parasitic capacitance and the like) is fixed and unchanged only at each side of the differential output of the current steering digital-to-analog converter. Thus, the invention is implemented in the first active cascode stage transistor N 5 And a second active cascode stage transistor N 6 The source electrode is added with a direct current bias current source I 1 Providing a first active cascode stage transistor N 5 And a second active cascode stage transistor N 6 With the aim of preventing the first active cascode stage transistor N 5 And a second active cascode stage transistor N 6 In other words, even the first switch tube N of the current steering dac 1 Or a second switch tube N 2 Non-conducting tail current source I O Not through the first active cascode stage transistor N 5 Or a second active cascode stage transistor N 6 But due to the first active cascode stage transistor N 5 And a second active cascode stage transistor N 6 The source electrode of the transistor is designed with a fixed direct current bias current source I with equal amplitude 1 Thus, the first active cascode stage transistor N 5 And a second active cascode stage transistor N 6 Is always in the on state, and can avoid the first effective cascode stage transistor N 5 And a second active cascode stage transistor N 6 The infinite charging and discharging process of the parasitic capacitance under the control of the input digital code when the transistor is completely switched off can eliminate the nonlinear distortion caused by the parasitic capacitance of the effective cascode transistor along with the relevant modulation effect of the input digital code, and the first effective cascode transistor N 5 And a second active cascode stage transistor N 6 Still remain active.
From fig. 6, it can be seen that the differential analog output V of the slave current switching unit OUT In view, although the parasitic capacitances associated with nodes B and C may still exist, those parasitic capacitances are associated with the first switch tube N 1 And a second switch tube N 2 Whether it is in the on or off state is irrelevant because the switch tail current of the current switch unit does not change the effective capacitance seen from the output node from one side to the other side, i.e. the parasitic capacitances connected to the node B and the node C, and these capacitance parasitics do not contribute to the nonlinear distortion of the current steering dac operating at high frequency.
Therefore, the first part causing the change of the dynamic effective capacitance seen from the output of the current steering dac is the first switch tube N in the current switch unit 1 And a second switch tube N 2 C of (A) GS The capacitance, a schematic diagram of the dynamic parasitic capacitance of the current switch cell shown in fig. 7, can be more intuitively understood. Due to the first active cascode stage transistor N 5 And a second active cascode stage transistor N 6 The source electrode of the transistor is designed with a bias small current source I 1 Providing a fixed first direct current bias current I of equal and smaller magnitude OUT1 And a second DC bias current I OUT2 So that the "dynamic effective" capacitance of the first part, as seen from the output, is the first switch tube N in the current switch unit 1 And a second switch tube N 2 C of (A) GS Capacitance to the effect of code dependent modulation due to finite output impedance due to the first switch tube N 1 And a second switch tube N 2 And a first active cascode stage transistor N 5 And a second active cascode stage transistor N 6 Intrinsic gain (g) m ×r o ) And decreases. Active cascodeStage transistor and transistor fixed DC bias current source I thereof 1 The improved design of the current steering digital-to-analog converter realizes that the nonlinear distortion caused by the modulation effect of the current steering digital-to-analog converter and the digital code is reduced by one order of magnitude under high frequency.
Using a dc bias current source I as shown in fig. 7 1 Provided to the active cascode stage transistor N in fig. 5 5 /N 6 As shown in fig. 7: the fourth bias voltage of 1.2V is output through the buffer amplifier A1 and provided to the fifth NMOS transistor N 13 And a sixth NMOS transistor N 14 The gain of the buffer amplifier A1 is designed to be more than 50dB, and the first NMOS tube N 9 And a second NMOS transistor N 10 Is controlled by an external first bias voltage V CS Providing a third NMOS transistor N 11 And a fourth NMOS transistor N 12 Is controlled by an external second bias voltage V CAS Providing; first NMOS transistor N 9 And a second NMOS transistor N 10 The design size of (1) is 2 mu/0.4 mu, and the number of gates is 2; third NMOS transistor N 11 And a fourth NMOS transistor N 12 The design size of (1) is that W/L is designed to be 0.8 mu/0.2 mu and the number of gates is 2; fifth NMOS transistor N 13 And a sixth NMOS transistor N 14 The design size of (1.0 mu/0.28 mu) and the number of gates of (1) is W/L, and the fifth NMOS transistor N 13 And a sixth NMOS transistor N 14 Respectively output a first direct current bias current I OUT1 And a second DC bias current I OUT2 。
Secondly, based on the design idea of the current-steering digital-to-analog converter, the invention also provides a high-frequency linearity improving method of the current-steering digital-to-analog converter, which comprises the following steps:
s1, aiming at least one current switch unit of a current steering digital-to-analog converter, a cascode transistor which is connected in series is additionally arranged between a tail current source transistor and a switch pair transistor, and an effective cascode transistor which is connected in series is additionally arranged between the switch pair transistor and a differential analog output end of the current steering digital-to-analog converter so as to increase the output impedance of the current switch unit;
and S2, aiming at least one current switch unit of the current steering digital-to-analog converter, providing direct current bias current for the effective cascode transistor so as to enable the effective cascode transistor to be kept on all the time.
In detail, in step S1, a cascode transistor connected in series is added between the tail current source transistor and the switch pair transistor, and a series effective cascode transistor is added between the switch pair transistor and the differential analog output terminal of the current steering digital-to-analog converter, so that the output impedance can be effectively increased, and the nonlinearity caused by the modulation effect of the input digital code due to the limited output impedance can be reduced; in step S2, a dc bias current is provided to the effective cascode transistor, so that the effective cascode transistor is always kept on, thereby avoiding a nonlinear effect related to an input digital code caused by a parasitic capacitance when the effective cascode transistor is completely turned off, and improving the linearity of the current steering digital-to-analog converter at a high frequency.
In summary, in the current-steering digital-to-analog converter and the high-frequency linearity improving method thereof provided by the present invention, cascode transistors are added in series between the tail current source transistor and the first and second switching tubes, a first effective cascode transistor is added in series between the first switching tube and the positive differential analog output terminal of the current-steering digital-to-analog converter, and a second effective cascode transistor is added in series between the second switching tube and the negative differential analog output terminal of the current-steering digital-to-analog converter, so that the output impedance of the current switch unit can be effectively increased, and the nonlinearity caused by the modulation effect of the input digital code due to the limited output impedance can be reduced; meanwhile, a first direct current bias current is provided for the first effective cascode transistor through the direct current bias current source, and a second direct current bias current is provided for the second effective cascode transistor, so that the first effective cascode transistor and the second effective cascode transistor are always kept on, nonlinear influences related to input codes caused by parasitic capacitance when the first effective cascode transistor and the second effective cascode transistor are completely disconnected can be effectively avoided, and the linearity of a current switch unit of the current steering digital-to-analog converter and the linearity of the current steering digital-to-analog converter under high frequency are improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A current steering digital-to-analog converter is characterized by comprising a tail current source transistor, a cascode transistor, a first switch tube, a second switch tube, a first effective cascode transistor, a second effective cascode transistor, a direct current bias current source and two load resistors, wherein a source of the tail current source transistor is grounded, a gate of the tail current source transistor is connected with a first bias voltage, a drain of the tail current source transistor is connected with a source of the cascode transistor, a gate of the cascode transistor is connected with a second bias voltage, a drain of the cascode transistor is connected with a source of the first switch tube, a gate of the first switch tube is connected with a first digital signal, a drain of the first switch tube is connected with a source of the first effective cascode transistor, a source of the first effective cascode transistor is further connected with a first output end of the direct current bias current source, a gate of the first effective cascode transistor is connected with a third bias voltage, a drain of the first effective cascode transistor is connected with a drain of the cascode transistor after being connected with a positive terminal of the cascode transistor, a drain of the first effective cascode transistor is connected with a drain of the second effective cascode transistor, and the second effective cascode transistor is connected with a drain of the second switch transistor, and the second effective cascode transistor, the drain of the second effective cascode transistor is connected with a drain of the second bias current steering digital-analog-to the second switch transistor, and the second effective cascode transistor, the drain of the second effective cascode transistor is connected with a differential transistor, and the second effective cascode transistor, the drain electrode of the second effective cascode transistor is connected with the working voltage through another load resistor in series, and the drain electrode of the second effective cascode transistor is the negative end of the differential analog output of the current switch unit of the current steering digital-to-analog converter; the direct current bias current source provides a first direct current bias current for the first effective cascode transistor, and the direct current bias current source provides a second direct current bias current for the second effective cascode transistor, so that the first effective cascode transistor and the second effective cascode transistor are always kept on.
2. The current steering digital-to-analog converter according to claim 1, wherein the tail current source transistor, the cascode stage transistor, the first switching transistor, the second switching transistor, the first active cascode stage transistor, and the second active cascode stage transistor are all NMOS transistors.
3. The current steering digital-to-analog converter according to claim 1 or 2, wherein the first switching tube has the same parameter specification as the second switching tube, and the first active cascode stage transistor has the same parameter specification as the second active cascode stage transistor.
4. The current steering digital-to-analog converter according to claim 3, wherein the size of the first switching tube is smaller than the size of the first active cascode stage transistor.
5. The current steering dac of claim 1 or 2, wherein the dc bias current source comprises a buffer amplifier, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor, wherein a source of the first NMOS transistor is grounded, a gate of the first NMOS transistor is connected to the first bias voltage, a drain of the first NMOS transistor is connected to a source of the third NMOS transistor, a gate of the third NMOS transistor is connected to the second bias voltage, a drain of the third NMOS transistor is connected to a source of the fifth NMOS transistor, a gate of the fifth NMOS transistor is connected to an output terminal of the buffer amplifier, a non-inverting input terminal of the buffer amplifier is connected to the fourth bias voltage, a inverting input terminal of the buffer amplifier is connected to an output terminal of the buffer amplifier, a source of the second NMOS transistor is grounded, a gate of the second NMOS transistor is connected to the first bias voltage, a drain of the second NMOS transistor is connected to a source of the fourth NMOS transistor, a gate of the fourth NMOS transistor is connected to the second bias voltage, a source of the fourth NMOS transistor is connected to the sixth NMOS transistor, and a gate of the buffer amplifier is connected to a drain of the sixth NMOS transistor; the drain electrode of the fifth NMOS tube is a first output end of the direct current bias current source, and the drain electrode of the sixth NMOS tube is a second output end of the direct current bias current source.
6. The current steering dac of claim 5 wherein the first NMOS transistor has the same parameter specification as the second NMOS transistor, the third NMOS transistor has the same parameter specification as the fourth NMOS transistor, and the fifth NMOS transistor has the same parameter specification as the sixth NMOS transistor.
7. The current steering dac of claim 6 wherein the first NMOS transistor has a size greater than the third NMOS transistor, which has a size greater than the fifth NMOS transistor.
8. A high-frequency linearity improving method of a current steering digital-to-analog converter is characterized by comprising the following steps:
aiming at least one current switch unit of the current steering digital-to-analog converter, a cascode transistor connected in series is additionally arranged between a tail current source transistor and a switch pair transistor, and a series effective cascode transistor is additionally arranged between the switch pair transistor and a differential analog output end of the current steering digital-to-analog converter so as to increase the output impedance of the current switch unit;
and aiming at least one current switch unit of the current steering digital-to-analog converter, providing direct current bias current for the effective cascode transistor so as to enable the effective cascode transistor to be always kept on.
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| CN202211268816.3A CN115842550A (en) | 2022-10-17 | 2022-10-17 | Current steering digital-to-analog converter and high-frequency linearity improving method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117097318A (en) * | 2023-10-20 | 2023-11-21 | 中国电子科技集团公司第五十八研究所 | High-speed current rudder DAC self-adaptive switch amplitude limiting circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117097318A (en) * | 2023-10-20 | 2023-11-21 | 中国电子科技集团公司第五十八研究所 | High-speed current rudder DAC self-adaptive switch amplitude limiting circuit |
| CN117097318B (en) * | 2023-10-20 | 2024-02-13 | 中国电子科技集团公司第五十八研究所 | High-speed current rudder DAC self-adaptive switch amplitude limiting circuit |
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