CN115378435A - Reference voltage buffer - Google Patents
Reference voltage buffer Download PDFInfo
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- CN115378435A CN115378435A CN202211065854.9A CN202211065854A CN115378435A CN 115378435 A CN115378435 A CN 115378435A CN 202211065854 A CN202211065854 A CN 202211065854A CN 115378435 A CN115378435 A CN 115378435A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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Abstract
The application discloses reference voltage buffer includes: the output stage comprises first to fifth transistors, the grid electrode of the first transistor is connected with a second bias voltage, the source electrode of the first transistor is connected with the ground terminal, the drain electrode of the first transistor is connected with the source electrode of the second transistor and the drain electrode of the third transistor, the grid electrode of the second transistor is connected with the first bias voltage, the drain electrode of the second transistor, the drain electrode and the grid electrode of the fourth transistor are connected with the grid electrode of the fifth transistor, and the source electrodes of the fourth transistor and the fifth transistor are connected with a power supply end; the inverting input end of the operational amplifier is connected with the drain electrode of the fifth transistor and the source electrode of the third transistor, the non-inverting input end of the operational amplifier is connected with the reference voltage, and the output end of the operational amplifier is connected with the grid electrode of the third transistor; and the current injection module is connected with the operational amplifier and respectively injects current into the operational amplifier. The voltage regulation range of the application is large, the precision is high, and the current driving capability of the reference circuit is not influenced.
Description
Technical Field
The present invention relates generally to the field of integrated circuit technology, and more particularly to a reference voltage buffer.
Background
The reference voltage buffer is a circuit for providing a reference voltage having a driving capability in an analog-to-digital converter, and performance thereof is required to have a stable voltage output while providing a current output and an input. Especially in the application of a high-speed medium-precision successive approximation type analog-to-digital converter, a multichannel interleaving technology is widely applied, random errors exist in reference voltages among different channels, the performance of the interleaved analog-to-digital converter is seriously affected by the characteristic, and therefore the reference voltage of each channel can be finely adjusted in a uniform step size within a certain range through digital control. Meanwhile, the power consumption requirement of each channel is higher due to the fact that the channels are provided. Therefore, the reference buffer needs to realize a function of fast recovery of the output voltage with low power consumption, and the output voltage can be configured by digital control.
Disclosure of Invention
The invention aims to provide a reference voltage buffer which has large voltage regulation range and high precision and does not influence the current driving capability of a reference circuit.
The application discloses reference voltage buffer includes:
an output stage including first to fifth transistors, a gate of the first transistor being connected to a second bias voltage, a source of the first transistor being connected to ground, a drain of the first transistor being connected to a source of the second transistor and a drain of the third transistor, a gate of the second transistor being connected to a first bias voltage, a drain of the second transistor, a drain and a gate of the fourth transistor being connected to a gate of the fifth transistor, sources of the fourth and fifth transistors being connected to a power supply terminal;
an inverting input terminal of the operational amplifier is connected to the drain of the fifth transistor and the source of the third transistor, a non-inverting input terminal of the operational amplifier is connected to a reference voltage, and an output terminal of the operational amplifier is connected to the gate of the third transistor; and
and the current injection module is connected with the operational amplifier and respectively injects current into the operational amplifier.
In a preferred embodiment, the operational amplifier includes: the drain electrodes of the sixth transistor and the seventh transistor are respectively connected with the load module, the source electrodes of the sixth transistor and the seventh transistor are both connected with the drain electrode of the eighth transistor, the grid electrode of the eighth transistor is connected with a third bias voltage, the source electrode of the eighth transistor is connected with the ground end, the grid electrode of the sixth transistor is connected with the grid electrode of the third transistor, and the grid electrode of the seventh transistor is connected with the reference voltage.
In a preferred embodiment, the current injection unit includes a first branch and a second branch, and the first branch and the second branch respectively include: the sources of the ninth to eleventh transistors are all connected to the power supply terminal, the drain of the ninth transistor and the gates of the ninth to eleventh transistors are connected to each other and to the current-steering dac, the drain of the tenth transistor is connected to the drain of the twelfth transistor, the source of the twelfth transistor, the gates of the twelfth and thirteenth transistors are connected to the ground, and the source of the thirteenth transistor is connected to the ground, wherein the drain of the sixth transistor is connected to the drain of the eleventh transistor in the first branch and the drain of the thirteenth transistor in the second branch, respectively, and the drain of the seventh transistor is connected to the drain of the thirteenth transistor in the first branch and the drain of the eleventh transistor in the second branch, respectively.
In one preferred example, the load unit includes fourteenth to nineteenth transistors, sources of the fourteenth to sixteenth transistors are connected to the power source terminal, gates and drains of the fourteenth transistor and the sixteenth transistor are connected to a drain of an eleventh transistor in the first branch and a drain of a thirteenth transistor in the second branch, gates and drains of the fifteenth transistor and the seventeenth transistor are connected to a drain of a thirteenth transistor in the first branch and a drain of an eleventh transistor in the first branch, a drain of the fourteenth transistor is connected to a gate and a drain of the eighteenth transistor and a gate of the nineteenth transistor, and a drain of the seventeenth transistor is connected to a gate of the third transistor and a drain of the nineteenth transistor.
In a preferred example, the current steering digital-to-analog converter receives an 8-bit digital signal.
In a preferred embodiment, a capacitor is further connected between the drain of the fifth transistor and the source of the third transistor and ground.
Compared with the prior art, the reference voltage buffer of the application has at least the following beneficial effects:
the invention is mainly used for a reference driving circuit of a high-speed multi-path interleaving successive approximation type analog-to-digital converter, has a two-stage amplifier structure formed by an output stage with a push-pull function and a high-gain stage, and has stronger current driving capability while ensuring the accuracy of output reference voltage. The performance characteristic has two remarkable advantages, namely that the requirement on the decoupling capacitor of the output end is reduced, so that the circuit area is saved, and the requirement on the quiescent current of the circuit is reduced, so that the power consumption of the circuit is reduced. In order to perform multi-channel interleaved reference matching, the reference driving circuit requires that the output voltage is adjustable, so that the circuit is added with a current-steering digital-to-analog converter to perform current injection on the output of the first-stage operational amplifier so as to achieve the purpose of adjusting the output of the reference circuit. The scheme has the advantages of large voltage regulation range, high precision and no influence on the current driving capability of the reference circuit.
A large number of technical features are described in the specification of the present application, and are distributed in various technical solutions, so that the specification is too long if all possible combinations of the technical features (i.e., the technical solutions) in the present application are listed. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.
Drawings
FIG. 1 is a schematic diagram of a reference voltage buffer in one embodiment of the present application.
Fig. 2 is a schematic diagram of a gain stage circuit in one embodiment of the present application.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The application discloses a reference voltage buffer, and fig. 1 shows a schematic diagram of the reference voltage buffer in one embodiment. The reference voltage buffer includes an output stage and a gain stage. Fig. 2 shows a schematic diagram of a gain stage circuit in one embodiment. The gain stage comprises an operational amplifier 101 and a current injection module.
The output stage comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5, wherein the gate of the first transistor M1 is connected to a second bias voltage VB2, the source of the first transistor M1 is connected to ground, the drain of the first transistor M1 is connected to the source of the second transistor M2 and the drain of the third transistor M3, the gate of the second transistor M2 is connected to a first bias voltage VB1, the drain of the second transistor M2, the drain and the gate of the fourth transistor M4 are connected to the gate of the fifth transistor M5, and the sources of the fourth transistor M4 and the fifth transistor M5 are connected to a power supply terminal.
The inverting input terminal of the operational amplifier 101 is connected to the drain of the fifth transistor M5 and the source of the third transistor M3, the non-inverting input terminal of the operational amplifier 101 is connected to the reference voltage VIN, and the output terminal of the operational amplifier 101 is connected to the gate of the third transistor M3 (S1). In one embodiment, the operational amplifier 101 includes: a load module, a sixth transistor M6, and seventh to eighth transistors M7 to M8. The drains of the sixth transistor M6 and the seventh transistor M7 are respectively connected to the load module, the sources of the sixth transistor M6 and the seventh transistor M7 are both connected to the drain of the eighth transistor M8, the gate of the eighth transistor M8 is connected to the third bias voltage VB3, the source of the eighth transistor M8 is connected to the ground, the gate of the sixth transistor M6 is connected to the gate (S1) of the third transistor M3, and the gate of the seventh transistor M7 is connected to the reference voltage VIN. The current injection module is connected to the operational amplifier 101 and injects current to the operational amplifier 101.
In one embodiment, the current injection unit includes a first branch 102 and a second branch 103, and the first branch 102 and the second branch 103 respectively include: a ninth transistor M9, M9', a tenth transistor M10, M10', an eleventh transistor M11, M11', a twelfth transistor M12, M12', and a thirteenth transistor M13, M13', the sources of the ninth transistor M9, M9', a tenth transistor M10, M10', and an eleventh transistor M11, M11' are all connected to the power supply terminal, the drains of the ninth transistor M9, M9', the tenth transistor M10, M10', and the eleventh transistor M11, M11 'are connected to the current steering dac 104, the drains of the tenth transistor M10, M10' are connected to the drains of the twelfth transistor M12, M12', the sources of the twelfth transistor M12, M12', the gates of the twelfth transistor M12, M12', and the gates of the thirteenth transistor M13, M13' are connected to the ground terminal, and the sources of the thirteenth transistor M13, M13 'and the drain of the thirteenth transistor M11, M11' are connected to the drain of the eleventh branch transistor M103, M11', the eleventh branch of the thirteenth transistor M11, M11', the thirteenth branch, M11', and the thirteenth branch of the eleventh transistor M11', respectively.
In one embodiment, the load unit includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18 and a nineteenth transistor M19, sources of the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 are connected to the power supply terminal, gates and drains of the fourteenth transistor M14 and the sixteenth transistor M16 are connected to a drain of the eleventh transistor M11 in the first branch 102 and a drain of the thirteenth transistor M13' in the second branch 103, gates and drains of the fifteenth transistor M15 and the seventeenth transistor M17 are connected to a drain of the thirteenth transistor M13 in the first branch 102 and a drain of the eleventh transistor M11 in the first branch 102, a drain of the sixteenth transistor M16 is connected to a gate and a drain of the eighteenth transistor M18 and a gate of the nineteenth transistor M19, and a drain of the seventeenth transistor M17 is connected to a gate (S1) of the third transistor M3 and a drain of the nineteenth transistor M19.
In one embodiment, the current steering dac 104 receives an 8-bit digital signal. In the default mode, the 8-bit digital signal received by the current steering dac 104 is at the middle value (128), where the differential output current of the current steering dac is 0, and there is no differential current injection transistors M9 and M9', and the reference voltage output will follow the reference input (VIN). If the 8-bit digital signal received by the dac 104 is greater than the intermediate value (between 128 and 255), the differential output current of the current-steering dac will be positive, the current IP > IN, the transistor M11 'will inject current into the transistor M7, the transistor M13' will draw current from the transistor M6, and finally the voltage of the output S1 generated by the reference will be reduced, the reduction being proportional to the variation of the 8-bit digital signal. Conversely, when the 8bit number received by the DAC 104 is reduced (0-128), the opposite operation will cause the output S1 voltage of the reference generation circuit to increase.
In one embodiment, a capacitor (not shown) is further connected between the drain of the fifth transistor M5 and the source of the third transistor M3 and the ground. This causes the output voltage of the reference generation circuit to drop when the load of the circuit draws current from the output. At this time, the output stage loop starts to operate, and the source voltage of the transistor M3 drops, so the current of the transistor M3 drops, and the constant current source current formed by the transistor M1 will flow through the transistor M2 instead, which causes the gate voltage of the transistor M4 to drop. The voltage difference between the gate and the source of the transistor M5 is increased, the current of the transistor M5 increases to raise the output voltage, and the loop continues to operate until the voltage reaches the loop stability point.
It should be noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is performed according to a certain element, it means that the action is performed at least according to the element, and includes two cases: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.
All documents mentioned in this specification are to be considered as being integrally included in the disclosure of the present application so as to be able to be a basis for modification as necessary. It should be understood that the above description is only for the preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.
Claims (6)
1. A reference voltage buffer, comprising:
an output stage including first to fifth transistors, a gate of the first transistor being connected to a second bias voltage, a source of the first transistor being connected to a ground terminal, a drain of the first transistor being connected to a source of the second transistor and a drain of the third transistor, a gate of the second transistor being connected to a first bias voltage, a drain of the second transistor, a drain and a gate of the fourth transistor being connected to a gate of the fifth transistor, sources of the fourth and fifth transistors being connected to a power supply terminal;
an inverting input terminal of the operational amplifier is connected to the drain of the fifth transistor and the source of the third transistor, a non-inverting input terminal of the operational amplifier is connected to a reference voltage, and an output terminal of the operational amplifier is connected to the gate of the third transistor; and
and the current injection module is connected with the operational amplifier and respectively injects current into the operational amplifier.
2. The reference voltage buffer of claim 1, wherein the operational amplifier comprises: the drain electrodes of the sixth transistor and the seventh transistor are respectively connected with the load module, the source electrodes of the sixth transistor and the seventh transistor are both connected with the drain electrode of the eighth transistor, the grid electrode of the eighth transistor is connected with a third bias voltage, the source electrode of the eighth transistor is connected with the ground end, the grid electrode of the sixth transistor is connected with the grid electrode of the third transistor, and the grid electrode of the seventh transistor is connected with the reference voltage.
3. The reference voltage buffer of claim 2, wherein the current injection unit comprises a first branch and a second branch, the first branch and the second branch respectively comprising: the sources of the ninth to eleventh transistors are all connected to the power supply terminal, the drain of the ninth transistor and the gates of the ninth to eleventh transistors are connected to each other and to the current-steering dac, the drain of the tenth transistor is connected to the drain of the twelfth transistor, the source of the twelfth transistor, the gates of the twelfth and thirteenth transistors are connected to the ground, and the source of the thirteenth transistor is connected to the ground, wherein the drain of the sixth transistor is connected to the drain of the eleventh transistor in the first branch and the drain of the thirteenth transistor in the second branch, respectively, and the drain of the seventh transistor is connected to the drain of the thirteenth transistor in the first branch and the drain of the eleventh transistor in the second branch, respectively.
4. The reference voltage buffer according to claim 3, wherein the load unit includes fourteenth to nineteenth transistors, sources of the fourteenth to sixteenth transistors are connected to the power source terminal, gates and drains of the fourteenth transistor and the sixteenth transistor are connected to a drain of an eleventh transistor in the first branch and a drain of a thirteenth transistor in the second branch, gates and drains of the fifteenth transistor and the seventeenth transistor are connected to a drain of a thirteenth transistor in the first branch and a drain of an eleventh transistor in the first branch, a drain of the fourteenth transistor is connected to a gate and a drain of the eighteenth transistor and a gate of the nineteenth transistor, and a drain of the seventeenth transistor is connected to a gate of the third transistor and a drain of the nineteenth transistor.
5. The reference voltage buffer of claim 3, wherein the current steering digital-to-analog converter receives an 8-bit digital signal.
6. The reference voltage buffer of claim 1 wherein a capacitor is further coupled between the drain of the fifth transistor and the source of the third transistor and ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211065854.9A CN115378435A (en) | 2022-08-31 | 2022-08-31 | Reference voltage buffer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211065854.9A CN115378435A (en) | 2022-08-31 | 2022-08-31 | Reference voltage buffer |
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| CN115378435A true CN115378435A (en) | 2022-11-22 |
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| CN202211065854.9A Pending CN115378435A (en) | 2022-08-31 | 2022-08-31 | Reference voltage buffer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116192144A (en) * | 2023-02-13 | 2023-05-30 | 集益威半导体(上海)有限公司 | Asynchronous successive approximation analog-to-digital converter |
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2022
- 2022-08-31 CN CN202211065854.9A patent/CN115378435A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116192144A (en) * | 2023-02-13 | 2023-05-30 | 集益威半导体(上海)有限公司 | Asynchronous successive approximation analog-to-digital converter |
| CN116192144B (en) * | 2023-02-13 | 2024-04-02 | 集益威半导体(上海)有限公司 | Asynchronous successive approximation analog-to-digital converter |
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