JP2019036817A - Transimpedance amplifier circuit and variable gain amplifier - Google Patents

Abstract

To improve linearity of an output signal with respect to an input signal.SOLUTION: A variable gain amplifier circuit 13 of a transimpedance amplifier circuit generates a pair of output signals Vout1 and Vout2 according to a voltage signal Vin and a reference signal Vref. A differential circuit 23 of the variable gain amplifier 13 includes: a transistor 31 having a base to which the voltage signal Vin is input; a transistor 32 having a base to which the reference signal Vref is input; and a variable resistance circuit 33 having a plurality of FETs 35_1 to 35_N, each source of which is connected to an emitter of a transistor 31 and each drain of which is connected to an emitter of the transistor 32. On/off states of a plurality of FETs are switched by linearity adjustment signals Vctl_1 to Vctl_N, so that a resistance value of the variable resistance circuit 33 increases as an amplitude of the voltage signal Vin increases.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a transimpedance amplifier circuit and a variable gain amplifier.

  Conventionally, an optical receiver module including a transimpedance amplifier circuit that converts a photocurrent generated in a light receiving element into a voltage signal is known. In PAM4 (4-level Pulse Amplitude Modulation) transmission or the like, linearity of a voltage signal with respect to photocurrent is required. For this reason, the amplitude of the signal is monitored so that the amplifier included in the transimpedance amplifier circuit is not saturated, and the gain of the variable gain amplifier is controlled according to the amplitude.

  Patent Document 1 includes a variable resistor circuit including a pair of transistors and a resistor and a field effect transistor (FET) that are provided between the emitters of the pair of transistors and connected in series. A gain-type differential amplifier is described. In this variable gain differential amplifier, a control voltage is applied to the gate of the FET, and gain control is performed by changing the resistance between the source and drain of the FET in accordance with the control voltage.

JP 2004-304775 A JP 58-204614 A Japanese Patent Laid-Open No. 11-509711 JP 2003-168937 A JP 2003-168938 A Japanese Patent Laid-Open No. 2003-243951 JP 2011-205470 A JP-A-63-175510

  In the configuration in which the control voltage is applied to the gate of the FET as in the variable gain differential amplifier described in Patent Document 1, by applying a control voltage in the vicinity of the threshold voltage of the FET, the gap between the drain and the source is reduced. The resistance value between the source and the drain is changed by using a transient state between an on state in which the transistor is conductive and an off state in which the drain and the source are interrupted. However, when the FET is in a transient state, fluctuations in the source and drain terminal voltages may affect the resistance value between the source and the drain. As a result, the linearity of the output signal with respect to the input signal may be degraded.

  The present invention provides a transimpedance amplifier circuit and a variable gain amplifier that can improve the linearity of an output signal with respect to an input signal.

  A transimpedance amplifier circuit according to an aspect of the present invention includes a variable gain amplifier that generates a pair of complementary signals according to an input signal and a reference signal, and a gain that generates a gain adjustment signal for controlling the gain of the variable gain amplifier. A control circuit; and a linearity control circuit that generates a linearity adjustment signal for controlling the linearity of the variable gain amplifier. The variable gain amplifier distributes the first current and the second current in two according to the input signal and the reference signal, the first current source that supplies the first current, the second current source that supplies the second current, A first differential circuit that generates the first current signal and the second current signal, and a second differential circuit that distributes the first current signal to the third current signal and the fourth current signal according to the gain adjustment signal. A third differential circuit that distributes the second current signal to the fifth current signal and the sixth current signal according to the gain adjustment signal, and a first load resistor that converts the fourth current signal into one of a pair of complementary signals An element and a second load resistance element that converts the sixth current signal into the other of the pair of complementary signals. The first differential circuit includes a control terminal to which an input signal is input, a first current terminal electrically connected to the first current source, and a second current terminal electrically connected to the second differential circuit. A control terminal to which a reference signal is input, a first current terminal electrically connected to the second current source, and a second electrically connected to the third differential circuit. A linearity adjustment signal is input to each gate of a second transistor having a current terminal, each source is connected in common to the first current terminal of the first transistor, and each drain is connected to the second transistor. And a variable resistance circuit having a plurality of field effect transistors connected in common to the first current terminal. In the linearity control circuit, as the amplitude of the input signal or the pair of complementary signals increases, the resistance value between the first current terminal of the first transistor and the first current terminal of the second transistor of the variable resistance circuit increases. As described above, for each of the plurality of field effect transistors, the ON state where the drain and the source are conductive and the OFF state where the drain and the source are blocked are switched by the linearity adjustment signal.

  According to the present invention, the linearity of an output signal with respect to an input signal can be improved.

FIG. 1 is a diagram illustrating a schematic configuration of an optical receiver including a transimpedance amplifier circuit according to the first embodiment. FIG. 2 is a diagram showing a circuit configuration of the variable gain amplifier shown in FIG. FIG. 3 is a diagram showing a circuit configuration of the gain control circuit shown in FIG. FIG. 4 is a diagram showing a circuit configuration of the linearity control circuit shown in FIG. FIG. 5 is a diagram showing a circuit configuration of a variable gain amplifier used in the transimpedance amplifier circuit of the comparative example. FIG. 6 is a diagram showing the DC characteristics of the variable gain amplifier shown in FIG. 7A is a diagram showing a simulation result of distortion of the output waveform with respect to the input optical power of the transimpedance amplifier circuit shown in FIG. 1, and FIG. 7B is an input of the transimpedance amplifier circuit of the comparative example. It is a figure which shows the simulation result of distortion of the output waveform with respect to optical power. FIG. 8 is a diagram illustrating a schematic configuration of an optical receiver including a transimpedance amplifier circuit according to the second embodiment. FIG. 9 is a diagram showing a circuit configuration of the control circuit shown in FIG.

[Description of Embodiment of Present Invention]
First, the contents of the embodiment of the present invention will be listed and described.

  A transimpedance amplifier circuit according to an aspect of the present invention includes a variable gain amplifier that generates a pair of complementary signals according to an input signal and a reference signal, and a gain that generates a gain adjustment signal for controlling the gain of the variable gain amplifier. A control circuit; and a linearity control circuit that generates a linearity adjustment signal for controlling the linearity of the variable gain amplifier. The variable gain amplifier distributes the first current and the second current in two according to the input signal and the reference signal, the first current source that supplies the first current, the second current source that supplies the second current, A first differential circuit that generates the first current signal and the second current signal, and a second differential circuit that distributes the first current signal to the third current signal and the fourth current signal according to the gain adjustment signal. A third differential circuit that distributes the second current signal to the fifth current signal and the sixth current signal according to the gain adjustment signal, and a first load resistor that converts the fourth current signal into one of a pair of complementary signals An element and a second load resistance element that converts the sixth current signal into the other of the pair of complementary signals. The first differential circuit includes a control terminal to which an input signal is input, a first current terminal electrically connected to the first current source, and a second current terminal electrically connected to the second differential circuit. A control terminal to which a reference signal is input, a first current terminal electrically connected to the second current source, and a second electrically connected to the third differential circuit. A linearity adjustment signal is input to each gate of a second transistor having a current terminal, each source is connected in common to the first current terminal of the first transistor, and each drain is connected to the second transistor. And a variable resistance circuit having a plurality of field effect transistors connected in common to the first current terminal. In the linearity control circuit, as the amplitude of the input signal or the pair of complementary signals increases, the resistance value between the first current terminal of the first transistor and the first current terminal of the second transistor of the variable resistance circuit increases. As described above, for each of the plurality of field effect transistors, the ON state where the drain and the source are conductive and the OFF state where the drain and the source are blocked are switched by the linearity adjustment signal.

  In this transimpedance amplifier circuit, an input signal is input to the control terminal of the first transistor included in the first differential circuit, and a reference signal is supplied to the control terminal of the second transistor. In such an asymmetric configuration, particularly when the field effect transistor is in a transient state, fluctuations in the source and drain terminal voltages affect the resistance value between the source and the drain, and the linearity of the complementary signal with respect to the input signal is reduced. May deteriorate. On the other hand, in the transimpedance amplifier circuit, the linearity adjustment signal is supplied to the respective gates of the plurality of field effect transistors, whereby each field effect transistor is switched to either the on state or the off state. Thereby, the resistance value of the variable resistance circuit is set. For this reason, since the resistance value of the variable resistance circuit can be changed in a stepwise manner without causing the field effect transistor to be in a transient state, the resistance value of the variable resistance circuit can be stabilized. As a result, the linearity of the complementary signal with respect to the input signal can be improved.

  The gain control circuit may include a first amplitude detection circuit that detects the amplitude of the pair of complementary signals, and a first generation circuit that generates a gain adjustment signal based on the amplitude. In this case, a gain adjustment signal is generated using a pair of complementary signals. Thereby, for example, the gain can be adjusted so that the linearity of amplification by the variable gain amplifier can be maintained. As a result, the voltage range of the input signal can be expanded.

  The linearity control circuit may include a second generation circuit that generates a linearity adjustment signal based on the amplitude detected by the first amplitude detection circuit. In this case, the variable resistance circuit is controlled using a pair of complementary signals. That is, since both the gain and linearity of the variable gain amplifier are controlled by the amplitude detected by the first amplitude detection circuit, the amplitude detection circuit can be shared by gain control and linearity control of the variable gain amplifier. Thereby, the circuit scale can be reduced.

  The linearity control circuit may include a second amplitude detection circuit that detects the amplitude of the input signal, and a second generation circuit that generates the linearity adjustment signal based on the amplitude. In this case, the variable resistance circuit is controlled using the input signal. In other words, since the linearity of the variable gain amplifier is controlled using the signal before being amplified by the variable gain amplifier, the linearity of the variable gain amplifier is controlled without being affected by variations in amplification by the variable gain amplifier. be able to.

  A variable gain amplifier according to another aspect of the present invention is a variable gain amplifier that generates a pair of complementary signals according to an input signal and a reference signal, and includes a first current source that supplies a first current, and a second current. A first current circuit for generating a first current signal and a second current signal by distributing the first current and the second current into two according to an input signal and a reference signal, A second differential circuit for distributing the first current signal to the third current signal and the fourth current signal according to the gain adjustment signal for controlling the gain, and the second current signal according to the gain adjustment signal. A third differential circuit for distributing the current signal and the sixth current signal; a first load resistance element for converting the fourth current signal into one of a pair of complementary signals; and a sixth current signal as the other of the pair of complementary signals. A second load resistance element to be converted. The first differential circuit includes a control terminal to which an input signal is input, a first current terminal electrically connected to the first current source, and a second current terminal electrically connected to the second differential circuit. A control terminal to which a reference signal is input, a first current terminal electrically connected to the second current source, and a second electrically connected to the third differential circuit. A second transistor having a current terminal; and a plurality of sources each having a source commonly connected to the first current terminal of the first transistor and a drain commonly connected to the first current terminal of the second transistor. A variable resistance circuit having a field effect transistor. Each of the plurality of field effect transistors is supplied with a linearity adjustment signal for switching between an on state in which the drain and the source are conductive and an off state in which the drain and the source are cut off. The

  In this variable gain amplifier, an input signal is input to the control terminal of the first transistor included in the first differential circuit, and a reference signal is supplied to the control terminal of the second transistor. In such an asymmetric configuration, particularly when the field effect transistor is in a transient state, fluctuations in the source and drain terminal voltages affect the resistance value between the source and the drain, and the linearity of the complementary signal with respect to the input signal is reduced. May deteriorate. On the other hand, in the variable gain amplifier, each field effect transistor is switched to either the on state or the off state by supplying a linearity adjustment signal to each gate of the plurality of field effect transistors. Thereby, the resistance value of the variable resistance circuit is set. For this reason, since the resistance value of the variable resistance circuit can be changed in a stepwise manner without causing the field effect transistor to be in a transient state, the resistance value of the variable resistance circuit can be stabilized. As a result, the linearity of the complementary signal with respect to the input signal can be improved.

[Details of the embodiment of the present invention]
Specific examples of the transimpedance amplifier circuit and the variable gain amplifier according to the embodiment of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to the claim are included.

(First embodiment)
FIG. 1 is a diagram illustrating a schematic configuration of an optical receiver including a transimpedance amplifier circuit according to the first embodiment. FIG. 2 is a diagram showing a circuit configuration of the variable gain amplifier shown in FIG. FIG. 3 is a diagram showing a circuit configuration of the gain control circuit shown in FIG. FIG. 4 is a diagram showing a circuit configuration of the linearity control circuit shown in FIG.

  An optical receiver 1 shown in FIG. 1 receives an optical signal Pin transmitted from an optical transmitter (not shown). The optical receiver 1 includes a light receiving element PD and a transimpedance amplifier circuit 10. The light receiving element PD receives the optical signal Pin and generates a photocurrent corresponding to the optical signal Pin. The light receiving element PD is, for example, a photodiode. One terminal of the light receiving element PD is electrically connected to a predetermined bias voltage, and the other terminal of the light receiving element PD outputs a photocurrent.

  The transimpedance amplifier circuit 10 receives the photocurrent from the light receiving element PD as an input signal Din, and outputs output signals DoutP and DoutN that are voltage signals in accordance with the input signal Din. The output signals DoutP and DoutN are a pair of complementary signals. The transimpedance amplifier circuit 10 includes an input terminal 10a, an output terminal 10b, and an output terminal 10c. An input signal Din is input to the input terminal 10a. An output signal DoutP is output from the output terminal 10b, and an output signal DoutN is output from the output terminal 10c. The output signals DoutP and DoutN constitute one differential signal (differential output signal).

  The transimpedance amplifier circuit 10 includes a TIA (TransImpedance Amplifier) unit 11, a dummy TIA unit 12, a variable gain amplifier 13, a buffer 14, an output buffer 15, an offset control circuit 16, a bypass circuit 17, and a gain control. A circuit 18 and a linearity control circuit 19 are provided.

  The TIA unit 11 is a circuit that converts an input signal Din into a voltage signal Vin (input signal). Specifically, the TIA unit 11 includes an amplifier 11a and a feedback resistance element 11b, and generates a voltage signal Vin corresponding to the current signal Iin obtained by subtracting the bypass current Ib from the input signal Din. The TIA unit 11 outputs the voltage signal Vin to the variable gain amplifier 13. The gain of the TIA unit 11 (ratio of the magnitude of the voltage signal Vin to the magnitude of the current signal Iin) is determined by the resistance value (transimpedance) of the feedback resistance element 11b.

  The dummy TIA unit 12 is a circuit that generates a reference signal Vref that is a voltage signal. The dummy TIA unit 12 outputs the reference signal Vref to the variable gain amplifier 13. The reference signal Vref is used to convert a single voltage signal Vin into a differential signal in the variable gain amplifier 13 and has a predetermined voltage value. Similar to the TIA unit 11, the dummy TIA unit 12 may include an amplifier and a feedback resistance element. Since the dummy TIA unit 12 has the same configuration as the TIA unit 11, the reference signal Vref may be generated so as to compensate (cancel) the change in the voltage signal Vin caused by the change in the power supply voltage and temperature of the amplifier.

  The variable gain amplifier 13 is a circuit that generates output signals Vout1 and Vout2 that are a pair of complementary signals in accordance with the voltage signal Vin and the reference signal Vref. As shown in FIG. 2, the variable gain amplifier 13 includes a current source 21 (first current source), a current source 22 (second current source), a differential circuit 23 (first differential circuit), and a difference. The dynamic amplifier 24, the differential circuit 25 (second differential circuit), the differential circuit 26 (third differential circuit), the load resistive element 27 (first load resistive element), and the load resistive element 28 (first 2 load resistance elements).

  The current source 21 is a circuit that supplies a current I1 (first current). The current source 21 supplies the current I1 to the differential circuit 23. The current source 22 is a circuit that supplies a current I2 (second current). The current source 22 supplies the current I2 to the differential circuit 23. The current I1 and the current I2 may be set to the same magnitude.

  The differential circuit 23 distributes the current I1 and the current I2 into two in accordance with the voltage signal Vin and the reference signal Vref, respectively, and a current signal Ic1 (first current signal) and a current signal Ic2 (second current signal). Is a circuit that generates The differential circuit 23 includes a transistor 31 (first transistor), a transistor 32 (second transistor), and a variable resistance circuit 33. The sum of current I1 and current I2 is substantially equal to the sum of current signal Ic1 and current signal Ic2. Here, “substantially equal” is described as follows. When the transistors 31 and 32 are bipolar transistors as will be described later, the base current flows into the emitter, whereby the emitter current (currents I1 and I2) becomes the collector current (current signal). This is because it becomes larger than Ic1, Ic2). For example, when the transistors 31 and 32 are field effect transistors having a MOS (Metal-Oxide-Semiconductor) structure, the gate current may be regarded as zero, so the sum of the current I1 and the current I2 is the current signal Ic1. And the current signal Ic2. The differential circuit 23 distributes the sum of the current I1 and the current I2 into two according to the difference between the voltage signal Vin and the reference signal Vref, and generates a current signal Ic1 and a current signal Ic2, respectively.

  The transistors 31 and 32 are, for example, NPN bipolar transistors. The base (control terminal) of the transistor 31 is electrically connected to the output terminal of the TIA unit 11, and the voltage signal Vin is input to the base of the transistor 31. The emitter (first current terminal) of the transistor 31 is electrically connected to the current source 21. The collector (second current terminal) of the transistor 31 is electrically connected to the differential circuit 25. The base (control terminal) of the transistor 32 is electrically connected to the output terminal of the dummy TIA unit 12, and the reference signal Vref is input to the base of the transistor 32. The emitter (first current terminal) of the transistor 32 is electrically connected to the current source 22. The collector (second current terminal) of the transistor 32 is electrically connected to the differential circuit 26.

  The variable resistance circuit 33 is provided between the emitter of the transistor 31 and the emitter of the transistor 32 and is a circuit for setting a resistance value between the emitter of the transistor 31 and the emitter of the transistor 32. The variable resistance circuit 33 includes a resistance element 34 and a plurality (N; N represents an integer of 2 or more) field effect transistors (FETs) 35. In order to distinguish N FETs 35, they may be expressed as FETs 35_k (k is an integer from 1 to N). The resistance element 34 has a fixed resistance value Re. One end of the resistance element 34 is electrically connected to the emitter of the transistor 31, and the other end of the resistance element 34 is electrically connected to the emitter of the transistor 32.

  The FETs 35 </ b> _ <b> 1 to 35 </ b> _N are connected in parallel to the resistance element 34 and are connected in parallel to each other. That is, the sources of the FETs 35_1 to 35_N are electrically connected to each other and are commonly connected to the emitter of the transistor 31 in common. The drains of the FETs 35_1 to 35_N are electrically connected to each other, and are commonly connected to the emitter of the transistor 32 in common. The linearity adjustment signal Vctl is input to the gates of the FETs 35_1 to 35_N. The linearity adjustment signal Vctl is a control signal for controlling the linearity of the variable gain amplifier 13. The linearity adjustment signal Vctl includes linearity adjustment signals Vctl_1 to Vctl_N. That is, the linearity adjustment signal Vctl_k is input to the gate of the FET 35_k.

  The state of the FET 35_k is determined by the linearity adjustment signal Vctl_k to be in an on state where the drain and the source are conductive with a relatively small resistance value (on resistance value) of, for example, several tens of Ω or less, or between the drain and the source. It is switched to the off state that is blocked. The voltage level of the linearity adjustment signal Vctl_k is set to one of a 0 level that is sufficiently smaller than the threshold voltage of the FET 35_k and a 1 level that is sufficiently larger than the threshold voltage of the FET 35_k. Not set. Therefore, when the 0-level linearity adjustment signal Vctl_k is input, the state of the FET 35_k is turned off, and when the 1-level linearity adjustment signal Vctl_k is input, the state of the FET 35_k is turned on. . Therefore, each FET 35_k functions as an electrical switch controlled by the respective linearity adjustment signal Vctl_k. In the present embodiment, the sizes (channel width W and channel length L) of the FETs 35_1 to 35_N are equal to each other, and the on-resistance values of the FETs 35_1 to 35_N are equal to each other. As described above, each of the FETs 35_1 to 35_N is individually set to the on state or the off state, so that the FETs 35_1 to 35_N function as variable resistors. In this way, with respect to the plurality of FETs 35_1 to 35_N having the same resistance value between the drain and the source, the resistance value of the variable resistance circuit 33 is made equal at regular intervals by changing the number of ON states and the number of OFF states. Can be changed. Further, since the state of each FET 35_k is either an on state or an off state, it is possible to avoid the influence of a transient voltage inside the differential circuit 23 as will be described later, and to reduce the linearity. Can be suppressed.

The differential amplifier 24 is a circuit that receives the gain adjustment signal Vga and generates the gain adjustment signals Vga ₊ and Vga ₋ . The gain adjustment signal Vga is a control signal for controlling the gain of the variable gain amplifier 13. The gain adjustment signals Vga ₊ and Vga ₋ are a pair of signals that change in a complementary manner, ie, a positive phase and a negative phase, which are 180 degrees different from each other. The gain of the output signals Vout1 and Vout2 with respect to the voltage signal Vin of the variable gain amplifier 13 is controlled by the potential difference between the gain adjustment signals Vga ₊ and Vga ₋ . The differential amplifier 24 outputs the gain adjustment signals Vga ₊ and Vga ₋ to the differential circuit 25 and the differential circuit 26.

  The differential circuit 25 is a circuit that distributes the current signal Ic1 into a current signal Ic3 (third current signal) and a current signal Ic4 (fourth current signal) in accordance with the gain adjustment signal Vga. The differential circuit 25 includes a transistor 51 and a transistor 52.

The transistors 51 and 52 are, for example, NPN type bipolar transistors. The base of the transistor 51 is electrically connected to the inverting output terminal of the differential amplifier 24, and the gain adjustment signal Vga ₋ is input to the base of the transistor 51. The base of the transistor 52 is electrically connected to the non-inverting output terminal of the differential amplifier 24, and the gain adjustment signal Vga ₊ is input to the base of the transistor 52. The emitter of the transistor 51 and the emitter of the transistor 52 are electrically connected to each other and are electrically connected to the collector of the transistor 31. The collector of the transistor 51 is electrically connected to the power supply voltage VCC. The collector of the transistor 52 is electrically connected to the power supply voltage VCC via the load resistance element 27.

  The differential circuit 26 is a circuit that distributes the current signal Ic2 into a current signal Ic5 (fifth current signal) and a current signal Ic6 (sixth current signal) in accordance with the gain adjustment signal Vga. The differential circuit 26 includes a transistor 61 and a transistor 62.

The transistors 61 and 62 are, for example, NPN bipolar transistors. The base of the transistor 61 is electrically connected to the inverting output terminal of the differential amplifier 24, and the gain adjustment signal Vga ₋ is input to the base of the transistor 61. The base of the transistor 62 is electrically connected to the non-inverting output terminal of the differential amplifier 24, and the gain adjustment signal Vga ₊ is input to the base of the transistor 62. The emitter of the transistor 61 and the emitter of the transistor 62 are electrically connected to each other and are electrically connected to the collector of the transistor 32. The collector of the transistor 61 is electrically connected to the power supply voltage VCC. The collector of the transistor 62 is electrically connected to the power supply voltage VCC via the load resistance element 28.

The differential circuit 25 distributes the current signal Ic1 into a current signal Ic3 that is the collector current of the transistor 51 and a current signal Ic4 that is the collector current of the transistor 52 in accordance with the gain adjustment signals Vga ₊ and Vga ₋ . The differential circuit 26 distributes the current signal Ic2 into a current signal Ic5 that is a collector current of the transistor 61 and a current signal Ic6 that is a collector current of the transistor 62 in accordance with the gain adjustment signals Vga ₊ and Vga ₋ . In the variable gain amplifier 13, the differential circuits 25 and 26 are configured so that the ratio of the current signal Ic4 to the current signal Ic3 is kept equal to the ratio of the current signal Ic6 to the current signal Ic5.

  The load resistance element 27 converts the current signal Ic4 into an output signal Vout1 (one of a pair of complementary signals). Specifically, the collector potential of the transistor 52 generated when the current signal Ic4 flows through the load resistance element 27 is output as the output signal Vout1. The load resistance element 28 converts the current signal Ic6 into an output signal Vout2 (the other of the pair of complementary signals). Specifically, the collector potential of the transistor 62 generated when the current signal Ic6 flows through the load resistance element 28 is output as the output signal Vout2. The reference potentials of the output signals Vout1 and Vout2 are equal to the power supply voltage VCC to which the load resistance elements 27 and 28 are connected. That is, when the current signal Ic4 is zero, the potential of the output signal Vout1 is equal to the power supply voltage VCC, and when the current signal Ic4 flows through the load resistance element 27, the potential of the output signal Vout1 is higher than the power supply voltage VCC. The voltage drops by a voltage drop (resistance value of the load resistance element 27 × the magnitude of the current signal Ic4). Similarly, when the current signal Ic6 is zero, the potential of the output signal Vout2 is equal to the power supply voltage VCC, and when the current signal Ic6 flows through the load resistance element 28, the potential of the output signal Vout2 is higher than the power supply voltage VCC. The potential is lowered by a voltage drop of 28 (the resistance value of the load resistive element 28 × the magnitude of the current signal Ic6). In many cases, the resistance values of the load resistance elements 27 and 28 are usually set to the same value. In that case, the output signal Vout1 and the output signal Vout2 constitute one differential signal.

  The buffer 14 is a differential amplifier that amplifies the output signals Vout1 and Vout2 and outputs the output signals Voutx1 and Voutx2. At this time, for example, the difference (= Voutx1−Voutx2) between the output signal Voutx1 and the output signal Voutx2 is the difference between the output signal Vout1 and the output signal Vout2 (= Vout1−Vout2). Equal to the multiplied size. The output buffer 15 is a differential amplifier that further amplifies the output signals Voutx1 and Voutx2 amplified by the buffer 14 and outputs output signals DoutP and DoutN. At this time, for example, the difference between the output signal DoutP and the output signal DoutN (= DoutP−DoutN) is the difference between the output signal Voutx1 and the output signal Voutx2 (= Voutx1−Voutx2). It is equal to the size multiplied by. The gains of the buffer 14 and the output buffer 15 are set to predetermined fixed values.

  The offset control circuit 16 is a circuit that generates a control signal Voffset that controls the time average of the current signal Iin to be a predetermined value in accordance with the output signals DoutP and DoutN output from the output buffer 15. The offset control circuit 16 outputs a control signal Voffset to the bypass circuit 17. For example, the offset control circuit 16 controls the bypass circuit 17 so that the bypass current Ib increases as the difference between the output signal DoutP and the output signal DoutN (= DoutP−DoutN) increases, so that the time of the current signal Iin is increased. Suppresses excessive increase of the average value.

  The bypass circuit 17 is a circuit that bypasses (divides) the bypass current Ib from the input signal Din in accordance with the control signal Voffset. In the present embodiment, the bypass circuit 17 includes an FET. The gate of the FET is connected to the output terminal of the offset control circuit 16, and a control signal Voffset is supplied to the gate of the FET. The source of the FET is electrically connected to the ground potential. The drain of the FET is electrically connected to the input terminal 10a. The bypass circuit 17 increases or decreases the magnitude of the bypass current Ib according to the control signal Voffset, but is not limited to the configuration shown in FIG. 1 and may have other circuit configurations to realize the same function. .

  The gain control circuit 18 is a circuit that generates the gain adjustment signal Vga based on the amplitudes of the output signals Vout1, Vout2 (output signals Voutx1, Voutx2). The gain control circuit 18 adjusts the gain of the variable gain amplifier 13 by controlling the current signal Ic4 and the current signal Ic6 using the gain adjustment signal Vga. The gain control circuit 18 generates the gain adjustment signal Vga so that the gain of the variable gain amplifier 13 decreases as the amplitude of the output signals Vout1 and Vout2 increases. In this example, the gain control circuit 18 generates the gain adjustment signal Vga so that the voltage level of the gain adjustment signal Vga decreases as the amplitude of the output signals Vout1 and Vout2 increases.

  As shown in FIG. 3, the gain control circuit 18 includes an amplitude detection circuit 81 (first amplitude detection circuit) and a generation circuit 82 (first generation circuit). The amplitude detection circuit 81 is a circuit that detects the amplitudes of the output signals Vout1 and Vout2. Specifically, the amplitude detection circuit 81 detects the amplitudes of the output signals Voutx1 and Voutx2 amplified by the buffer 14. The amplitude detection circuit 81 includes a peak detection circuit 83, an average value detection circuit 84, and a differential amplifier 85.

  The peak detection circuit 83 is a circuit that detects the peak values of the output signals Voutx1 and Voutx2. The peak detection circuit 83 outputs the detected peak value to the differential amplifier 85. The average value detection circuit 84 is a circuit that detects a time average value (average voltage value) of the output signals Voutx1 and Voutx2. The average value detection circuit 84 outputs the detected average value to the differential amplifier 85. The differential amplifier 85 generates a difference value between the peak value detected by the peak detection circuit 83 and the average value detected by the average value detection circuit 84, and detects the amplitudes of the output signals Voutx1 and Voutx2 based on the difference value. To do. A peak value is input to the non-inverting input terminal of the differential amplifier 85, and an average value is input to the inverting input terminal of the differential amplifier 85. The differential amplifier 85 detects the amplitude from the value obtained by subtracting the average value from the peak value (equal to ½ of the amplitude). The differential amplifier 85 outputs the detected amplitude to the generation circuit 82.

  The generation circuit 82 is a circuit that generates the gain adjustment signal Vga based on the amplitudes of the output signals Voutx1 and Voutx2. In this example, the generation circuit 82 is a differential amplifier. The amplitude output from the amplitude detection circuit 81 is input to the inverting input terminal of the generation circuit 82. The reference signal Aref is input to the non-inverting input terminal of the generation circuit 82. The reference signal Aref is a predetermined fixed value, and is set to a value that does not distort the signals of the buffer 14 and the output buffer 15 within the range of the optical signal Pin to be used. The generation circuit 82 generates the gain adjustment signal Vga by amplifying a value obtained by subtracting the amplitude from the reference signal Aref. According to this configuration, the value of the gain adjustment signal Vga decreases as the amplitude of the output signals Voutx1 and Voutx2 increases. The generation circuit 82 outputs the gain adjustment signal Vga to the variable gain amplifier 13.

  The linearity control circuit 19 is a circuit that generates a linearity adjustment signal Vctl based on the amplitude of the voltage signal Vin. Specifically, the linearity control circuit 19 sets the ON state and the OFF state for each of the FETs 35_1 to 35_N so that the resistance value of the variable resistance circuit 33 increases as the amplitude of the voltage signal Vin increases. Switching is performed according to the adjustment signal Vctl. For example, among the N FETs 35_1 to 35_N, the resistance value of the variable resistance circuit 33 increases as the number of off-state FETs increases and the number of on-state FETs decreases. The linearity adjustment signal Vctl is generated so as to decrease and increase the number of off-state FETs.

  As shown in FIG. 4, the linearity control circuit 19 includes an amplitude detection circuit 91 (second amplitude detection circuit) and a generation circuit 92 (second generation circuit). The amplitude detection circuit 91 is a circuit that detects the amplitude of the voltage signal Vin. The amplitude detection circuit 91 includes a peak detection circuit 93, an average value detection circuit 94, and a differential amplifier 95.

  The peak detection circuit 93 is a circuit that detects the peak value of the voltage signal Vin. The peak detection circuit 93 outputs the detected peak value to the differential amplifier 95. The average value detection circuit 94 is a circuit that detects a time average value (average voltage value) of the voltage signal Vin. The average value detection circuit 94 outputs the detected average value to the differential amplifier 95. The differential amplifier 95 generates a difference value between the peak value detected by the peak detection circuit 93 and the average value detected by the average value detection circuit 94, and detects the amplitude of the voltage signal Vin based on the difference value. A peak value is input to the non-inverting input terminal of the differential amplifier 95, and an average value is input to the inverting input terminal of the differential amplifier 95. The differential amplifier 95 detects the amplitude from the value obtained by subtracting the average value from the peak value (equal to ½ of the amplitude). The differential amplifier 95 outputs the detected amplitude to the generation circuit 92.

  The generation circuit 92 is a circuit that generates the linearity adjustment signal Vctl based on the amplitude of the voltage signal Vin. The generation circuit 92 includes an A / D converter 96 and a digital circuit 97. The A / D converter 96 is a circuit that converts the amplitude of the voltage signal Vin detected by the amplitude detection circuit 91 into a digital value. The A / D converter 96 outputs the digital value to the digital circuit 97. The digital circuit 97 generates the linearity adjustment signal Vctl so that the resistance value of the variable resistance circuit 33 increases as the digital value increases. That is, by adjusting the linearity adjustment signal Vctl, the number of FETs in the off state among the N FETs 35_1 to 35_N is increased, and the number of FETs in the on state is decreased.

  For example, in the digital circuit 97, N threshold values of a first threshold value, a second threshold value,..., And an Nth threshold value are preset in descending order. That is, each threshold value is set such that the first threshold value> the second threshold value>...> The (N-1) th threshold value> the Nth threshold value. When the digital value received from the A / D converter 96 is larger than the first threshold value, the digital circuit 97 generates a linearity adjustment signal Vctl that turns off all of the FETs 35_1 to 35_N. Specifically, the digital circuit 97 generates the zero-level linearity adjustment signals Vctl_1 to Vctl_N. That is, the digital circuit 97 sets all the linearity adjustment signals Vctl_1 to Vctl_N to 0 level. When the digital value is equal to or smaller than the first threshold value and greater than the second threshold value, the digital circuit 97 linearly sets one of the FETs 35_1 to 35_N to the on state and the remaining N−1 pieces to the off state. A sex adjustment signal Vctl is generated. For example, the digital circuit 97 generates the 1-level linearity adjustment signal Vctl_1 and the 0-level linearity adjustment signals Vctl_2 to Vctl_N.

  Similarly, when the digital value is less than or equal to the kth threshold and greater than the k + 1th threshold, the digital circuit 97 turns on k of the FETs 35_1 to 35_N and turns off (N−k). A linearity adjustment signal Vctl is generated. For example, the digital circuit 97 generates 1-level linearity adjustment signals Vctl_1 to Vctl_k and 0-level linearity adjustment signals Vctl_k + 1 to Vctl_N. When the digital value is equal to or smaller than the Nth threshold value, the digital circuit 97 generates the linearity adjustment signal Vctl that turns on all of the FETs 35_1 to 35_N. Specifically, the digital circuit 97 generates one-level linearity adjustment signals Vctl_1 to Vctl_N. That is, the digital circuit 97 sets all of the linearity adjustment signals Vctl_1 to Vctl_N to 1 level.

  That is, as the amplitude of the voltage signal Vin is larger, the linearity control circuit 19 increases the number of off-state FETs among the FETs 35_1 to 35_N and decreases the number of on-state FETs by the linearity adjustment signal Vctl. Further, the linearity control circuit 19 decreases the number of FETs in the OFF state among the FETs 35_1 to 35_N and increases the number of FETs in the ON state as the amplitude of the voltage signal Vin is small. Thereby, the resistance value between the emitter of the transistor 31 and the emitter of the transistor 32 is variably controlled.

  In the transimpedance amplifier circuit 10, as the frequency of the input signal Din increases, it becomes difficult to obtain a sufficient gain only by the TIA unit 11. In order to suppress input conversion noise of the transimpedance amplifier circuit 10, the variable gain amplifier 13 It is necessary to reduce the noise. For this reason, by increasing the gain of the variable gain amplifier 13 by decreasing the resistance value of the variable resistance circuit 33, the shot noise inside the variable gain amplifier 13 and the thermal noise of the load resistance elements 27 and 28 are transimpedance. The degree of influence on the input conversion noise of the amplifier circuit 10 is reduced. That is, the degree of influence of the noise element inside the variable gain amplifier 13 on the input converted noise of the transimpedance amplifier circuit 10 is determined by the noise from those noise sources being input from the transimpedance amplifier circuit 10 to the output of the variable gain amplifier 13. The value divided by the gain up to. For this reason, noise (input conversion noise) is reduced by increasing the gain of the variable gain amplifier 13.

  Therefore, the variable gain amplifier 13 reduces the noise by reducing the resistance value of the variable resistance circuit 33 when the amplitude of the voltage signal Vin is small, and reduces the resistance value of the variable resistance circuit 33 when the amplitude of the voltage signal Vin is large. It is controlled to increase the linear input range.

  Next, the effects of the transimpedance amplifier circuit 10 and the variable gain amplifier 13 will be described with reference to FIGS. 5 to 7 while comparing with the transimpedance amplifier circuit of the comparative example. FIG. 5 is a diagram showing a circuit configuration of a variable gain amplifier used in the transimpedance amplifier circuit of the comparative example.

  As shown in FIG. 5, the variable gain amplifier 113 of the comparative example is mainly different from the variable gain amplifier 13 in that a differential circuit 123 is provided instead of the differential circuit 23. The differential circuit 123 is mainly different from the differential circuit 23 in that a variable resistance circuit 133 is provided instead of the variable resistance circuit 33. The variable resistance circuit 133 is mainly different from the variable resistance circuit 33 in that one FET 35 is provided instead of the FETs 35_1 to 35_N.

  In the transimpedance amplifier circuit using the variable gain amplifier 113, the linearity control circuit outputs an analog value linearity adjustment signal Vctl to the FET 35. That is, as the amplitude of the voltage signal Vin is smaller, the linearity control circuit increases the voltage level of the linearity adjustment signal Vctl to decrease the resistance value of the variable resistance circuit 133 (FET 35), and the amplitude of the voltage signal Vin is larger. As a result, the voltage level of the linearity adjustment signal Vctl is decreased to increase the resistance value of the variable resistance circuit 133 (FET 35).

  FIG. 6 is a diagram showing the DC characteristics of the variable gain amplifier shown in FIG. 7A is a diagram showing a simulation result of distortion of the output waveform with respect to the input optical power of the transimpedance amplifier circuit shown in FIG. 1, and FIG. 7B is an input of the transimpedance amplifier circuit of the comparative example. It is a figure which shows the simulation result of distortion of the output waveform with respect to optical power. 6 indicates the differential input voltage (= Vin−Vref) [V], which is the difference between the voltage signal Vin and the reference signal Vref, and the vertical axis in FIG. 6 indicates the differential gain [a. u. ] Is shown. “Au” means an arbitrary unit. 7A and 7B indicate the optical modulation amplitude (OMA) [dBm] of the optical signal Pin, and the vertical axes of FIGS. 7A and 7B indicate the output waveforms. The distortion rate (Total Harmonic Distortion; THD) [%]. Here, the distortion rate of the output signals Vout1 and Vout2 output from the variable gain amplifiers 13 and 113 when a sine wave having a frequency of 1 GHz is used as the voltage signal Vin is shown. When a sine wave having a frequency of 1 GHz is used as the voltage signal Vin, the frequency spectrum of the output signals Vout1 and Vout2 output from the variable gain amplifiers 13 and 113 has a frequency of 1 GHz in an ideal state without distortion. Has only ingredients. As the distortion increases, frequency components (harmonics) that are integer multiples of 1 GHz increase.

  Graphs G <b> 1 to G <b> 4 shown in FIG. 6 show the DC characteristics of the variable gain amplifier 113 under different bias conditions of the gate voltage of the FET 35. Characteristic values D1 to D4 shown in FIG. 7B are characteristic values under the bias conditions of the graphs G1 to G4. In the order of the graphs G1 to G4, the voltage level of the linearity adjustment signal Vctl increases, and the gain (absolute value) increases. Specifically, under the bias condition of the graph G1, the voltage level of the linearity adjustment signal Vctl is sufficiently smaller than the threshold voltage of the FET 35, and the FET 35 of the variable resistance circuit 133 is in an off state. Under the bias conditions in the graphs G2 and G3, the voltage level of the linearity adjustment signal Vctl is near the threshold voltage of the FET 35. At this time, the resistance value of the FET 35 decreases and the gain of the variable gain amplifier 113 increases, but the slopes of the graphs G2 and G3 when the differential input voltage is 0 are large. That is, in the graphs G2 and G3, the gain is asymmetric between positive and negative of the differential input voltage. For this reason, in each of the output signals Vout1 and Vout2, the positive-side amplitude and the negative-side amplitude are different. Thereby, as shown in FIG. 7B, in the transimpedance amplifier circuit of the comparative example, the linearity is degraded when the OMA of the optical signal Pin is 0 to +1 dBm.

  Under the bias condition of the graph G4, the voltage level of the linearity adjustment signal Vctl is sufficiently larger than the threshold voltage of the FET 35. Therefore, the influence of the terminal voltage (source voltage and drain voltage) of the FET 35 on the resistance value of the FET 35 is small and asymmetric. Sex has been improved.

  On the other hand, in the transimpedance amplifier circuit 10, in order to switch the resistance value of the variable resistor circuit 33, the voltage near the threshold voltage of the FETs 35_1 to 35_N is not used as the voltage level of the linearity adjustment signals Vctl_1 to Vctl_N. For this reason, when the voltage levels of the linearity adjustment signals Vctl_1 to Vctl_N are 0 level, the voltage levels of the linearity adjustment signals Vctl_1 to Vctl_N do not depend on the amplitude of the voltage signal Vin and It is always smaller than the emitter voltage of the transistor 32. On the other hand, when the voltage level of the linearity adjustment signals Vctl_1 to Vctl_N is 1, the voltage level of the linearity adjustment signals Vctl_1 to Vctl_N depends on the emitter voltage of the transistor 31 and the transistor regardless of the amplitude of the voltage signal Vin. Always greater than 32 emitter voltages. As a result, the influence of the terminal voltages (source voltage and drain voltage) of the FETs 35_1 to 35_N on the resistance values of the FETs 35_1 to 35_N is reduced. As a result, as shown in FIG. 7A, the peak distortion rate is reduced from about 7% to about 3%, and the deterioration of linearity is suppressed.

  As described above, in the transimpedance amplifier circuit 10 and the variable gain amplifier 13, the voltage signal Vin is input to the base of the transistor 31 included in the differential circuit 23, and the reference signal Vref is supplied to the base of the transistor 32. In such an asymmetric configuration, as in the case of the transimpedance amplifier circuit of the comparative example, particularly when the FET 35 is in a transient state, fluctuations in the terminal voltage of the source and drain affect the resistance value between the source and drain, The linearity of the output signals Vout1 and Vout2 with respect to the voltage signal Vin may be deteriorated. In contrast, in the transimpedance amplifier circuit 10 and the variable gain amplifier 13, the linearity adjustment signals Vctl_1 to Vctl_N are supplied to the gates of the FETs 35_1 to 35_N, so that the FETs 35_1 to 35_N are in the on state and the off state, respectively. Switch to either. Thereby, the resistance value of the variable resistance circuit 33 is set. For this reason, since the resistance value of the variable resistance circuit 33 can be changed stepwise without causing each of the FETs 35_1 to 35_N to be in a transient state, the resistance value of the variable resistance circuit 33 can be stabilized. . As a result, it is possible to improve the linearity of the output signals Vout1 and Vout2 with respect to the voltage signal Vin.

  The gain control circuit 18 generates a gain adjustment signal Vga based on the amplitudes of the output signals Voutx1 and Voutx2. Therefore, the gain adjustment signal Vga is generated using the output signals Voutx1 and Voutx2. Thereby, for example, the gain of the variable gain amplifier 13 can be adjusted so that the linearity of amplification by the variable gain amplifier 13 can be maintained. As a result, the voltage range of the voltage signal Vin can be expanded.

  The linearity control circuit 19 generates a linearity adjustment signal Vctl based on the amplitude of the voltage signal Vin. For this reason, the variable resistance circuit 33 is controlled using the voltage signal Vin. That is, since the linearity of the variable gain amplifier 13 is controlled using the voltage signal Vin before being amplified by the variable gain amplifier 13, the variable gain amplifier 13 is not affected by variations in amplification by the variable gain amplifier 13. Can be controlled.

(Second Embodiment)
Next, a transimpedance amplifier circuit according to the second embodiment will be described with reference to FIGS. FIG. 8 is a diagram illustrating a schematic configuration of an optical receiver including a transimpedance amplifier circuit according to the second embodiment. FIG. 9 is a diagram showing a circuit configuration of the control circuit shown in FIG. As shown in FIG. 8, the optical receiver 1 </ b> A is mainly different from the optical receiver 1 in that it includes a transimpedance amplifier circuit 10 </ b> A instead of the transimpedance amplifier circuit 10. The transimpedance amplifier circuit 10A is mainly different from the transimpedance amplifier circuit 10 in that a control circuit 20 is provided instead of the gain control circuit 18 and the linearity control circuit 19.

  The control circuit 20 is a circuit that generates the gain adjustment signal Vga and the linearity adjustment signal Vctl based on the amplitudes of the output signals Vout1 and Vout2 (output signals Voutx1 and Voutx2). The control circuit 20 includes a gain control circuit 18 and a linearity control circuit 19A. The linearity control circuit 19A is mainly different from the linearity control circuit 19 in that it does not include the amplitude detection circuit 91 and includes a generation circuit 92A (second generation circuit) instead of the generation circuit 92.

  The generation circuit 92A is a circuit that generates the linearity adjustment signal Vctl based on the amplitude detected by the amplitude detection circuit 81. The generation circuit 92A includes an A / D converter 96A and a digital circuit 97A. The A / D converter 96A is a circuit that converts the amplitudes of the output signals Voutx1 and Voutx2 detected by the amplitude detection circuit 81 into digital values. The A / D converter 96A outputs a digital value to the digital circuit 97A. The digital circuit 97A generates the linearity adjustment signal Vctl so that the resistance value of the variable resistor circuit 33 increases as the digital value converted by the A / D converter 96A increases. The digital circuit 97A is different from the digital circuit 97 in the values of the first threshold value, the second threshold value,. Each threshold value is set according to the amplitude of the output signals Voutx1 and Voutx2.

  That is, the linearity control circuit 19A sets the FETs 35_1 to 35_N to the ON state so that the resistance value of the variable resistance circuit 33 increases as the amplitude of the output signals Vout1 and Vout2 (output signals Voutx1 and Voutx2) increases. The off state is switched by the linearity adjustment signal Vctl. Specifically, the linearity control circuit 19A increases the number of FETs in the off state among the FETs 35_1 to 35_N by the linearity adjustment signal Vctl as the amplitude of the output signals Vout1 and Vout2 (output signals Voutx1 and Voutx2) increases. Reduce the number of on-state FETs. In addition, the linearity control circuit 19A reduces the number of FETs in the off state among the FETs 35_1 to 35_N by the linearity adjustment signal Vctl as the amplitude of the output signals Vout1 and Vout2 (output signals Voutx1 and Voutx2) is small. Increase the number of FETs. Thereby, the resistance value between the emitter of the transistor 31 and the emitter of the transistor 32 is variably controlled.

  Also in the transimpedance amplifier circuit 10A described above, the same effect as the transimpedance amplifier circuit 10 is exhibited.

  In the transimpedance amplifier circuit 10A, the linearity control circuit 19A generates the linearity adjustment signal Vctl based on the amplitudes of the output signals Vout1, Vout2 (output signals Voutx1, Voutx2). Therefore, the variable resistance circuit 33 is controlled using the amplitudes of the output signals Vout1 and Vout2 (output signals Voutx1 and Voutx2). That is, since both the gain and linearity of the variable gain amplifier 13 are controlled by the amplitude detected by the amplitude detection circuit 81, the amplitude detection circuit 81 is shared by the gain control and the linearity control of the variable gain amplifier 13. it can. As a result, the circuit scale of the transimpedance amplifier circuit 10A can be reduced.

  The transimpedance amplifier circuit and the variable gain amplifier according to the present invention are not limited to the above embodiment.

  For example, in the above embodiment, the bipolar transistors are used as the transistors 31, 32, 51, 52, 61, 62. However, the transistors 31, 32, 51, 52, 61, 62 are FETs. Also good. When the transistors 31, 32, 51, 52, 61, and 62 are FETs, the base, emitter, and collector of the bipolar transistor are read as a gate, a source, and a drain, respectively.

  Further, the sizes (channel width W and channel length L) of the FETs 35_1 to 35_N may not be the same. In this case, the resistance values of the FETs 35_1 to 35_N are different from each other. The resistance values of the FETs 35_1 to 35_N increase as the value W / L obtained by dividing the channel width W by the channel length L decreases. In accordance with the digital value output from the A / D converter 96, a combination of the FET to be turned on and the FET to be turned off in the FETs 35_1 to 35_N is determined in advance. The digital circuit 97 generates a linearity adjustment signal Vctl that turns the FET on or off according to the combination of the FETs 35_1 to 35_N. The number of FETs 35 can be reduced by appropriately setting the sizes of the FETs 35_1 to 35_N. As a result, the circuit scale of the variable gain amplifier 13 can be reduced.

  For example, in the variable gain amplifier 13 of FIG. 2, N = 11, a pattern that turns on all of the FETs 35_1 to 35_11, a pattern that turns on only one FET 35, a pattern that turns on three FETs 35, Also, it is assumed that four patterns are required to turn off all of the FETs 35_1 to 35_11. On the other hand, using the three FETs 35 having a size ratio of 1: 2: 8 makes it possible to realize the above four patterns.

  DESCRIPTION OF SYMBOLS 1,1A ... Optical receiver, 10, 10A ... Transimpedance amplifier circuit, 11 ... TIA part, 12 ... Dummy TIA part, 13 ... Variable gain amplifier, 18 ... Gain control circuit, 19, 19A ... Linearity control circuit, 20 ... Control circuit, 21 ... Current source (first current source), 22 ... Current source (second current source), 23 ... Differential circuit (first differential circuit), 25 ... Differential circuit (second differential circuit) ), 26... Differential circuit (third differential circuit), 27... Load resistance element (first load resistance element), 28... Load resistance element (second load resistance element), 31. 32 ... transistor (second transistor), 33 ... variable resistance circuit, 34 ... resistance element, 35_1 to 35_N ... FET, 81 ... amplitude detection circuit (first amplitude detection circuit), 82 ... generation circuit (first generation circuit), 91... Amplitude detection circuit (second Width detection circuit), 92, 92A ... Generation circuit (second generation circuit), I1 ... Current (first current), I2 ... Current (second current), Ic1 ... Current signal (first current signal), Ic2 ... Current Signal (second current signal), Ic3 ... current signal (third current signal), Ic4 ... current signal (fourth current signal), Ic5 ... current signal (fifth current signal), Ic6 ... current signal (sixth current signal) ), Pin ... optical signal, Vctl_1 to Vctl_N ... linearity adjustment signal, Vga ... gain adjustment signal, Vin ... voltage signal, Vout1 ... output signal (one of a pair of complementary signals), Vout2 ... output signal (a pair of complementary signals) On the other hand, Vref ... reference signal.

Claims (5)

A variable gain amplifier that generates a pair of complementary signals according to an input signal and a reference signal;
A gain control circuit for generating a gain adjustment signal for controlling the gain of the variable gain amplifier;
A linearity control circuit for generating a linearity adjustment signal for controlling the linearity of the variable gain amplifier;
With
The variable gain amplifier is:
A first current source for supplying a first current;
A second current source for supplying a second current;
A first differential circuit that distributes the first current and the second current into two in accordance with the input signal and the reference signal, respectively, and generates a first current signal and a second current signal;
A second differential circuit for distributing the first current signal to a third current signal and a fourth current signal in response to the gain adjustment signal;
A third differential circuit for distributing the second current signal to a fifth current signal and a sixth current signal in response to the gain adjustment signal;
A first load resistance element that converts the fourth current signal into one of the pair of complementary signals;
A second load resistance element for converting the sixth current signal into the other of the pair of complementary signals;
With
The first differential circuit includes:
A control terminal to which the input signal is input; a first current terminal electrically connected to the first current source; and a second current terminal electrically connected to the second differential circuit. A first transistor;
A control terminal to which the reference signal is input; a first current terminal electrically connected to the second current source; and a second current terminal electrically connected to the third differential circuit. A second transistor;
The linearity adjustment signal is input to each gate, each source is commonly connected to the first current terminal of the first transistor, and each drain is commonly connected to the first current terminal of the second transistor. A variable resistance circuit having a plurality of field effect transistors,
With
In the linearity control circuit, the larger the amplitude of the input signal or the pair of complementary signals, the greater the gap between the first current terminal of the first transistor and the first current terminal of the second transistor of the variable resistance circuit. For each of the plurality of field effect transistors, an ON state in which the drain and the source are electrically connected and an OFF state in which the drain and the source are interrupted are provided for each of the plurality of field effect transistors. Transimpedance amplifier circuit that is switched by linearity adjustment signal.   2. The gain control circuit according to claim 1, comprising: a first amplitude detection circuit that detects an amplitude of the pair of complementary signals; and a first generation circuit that generates the gain adjustment signal based on the amplitude. Transimpedance amplifier circuit.   The transimpedance amplifier circuit according to claim 2, wherein the linearity control circuit includes a second generation circuit that generates the linearity adjustment signal based on the amplitude detected by the first amplitude detection circuit.   The linearity control circuit includes: a second amplitude detection circuit that detects an amplitude of the input signal; and a second generation circuit that generates the linearity adjustment signal based on the amplitude. A transimpedance amplifier circuit according to 1. A variable gain amplifier that generates a pair of complementary signals according to an input signal and a reference signal,
A first current source for supplying a first current;
A second current source for supplying a second current;
A first differential circuit that generates a first current signal and a second current signal by distributing the first current and the second current into two according to the input signal and the reference signal,
A second differential circuit for distributing the first current signal to a third current signal and a fourth current signal in response to a gain adjustment signal for controlling the gain;
A third differential circuit for distributing the second current signal to a fifth current signal and a sixth current signal in response to the gain adjustment signal;
A first load resistance element that converts the fourth current signal into one of the pair of complementary signals;
A second load resistance element for converting the sixth current signal into the other of the pair of complementary signals;
With
The first differential circuit includes:
A control terminal to which the input signal is input; a first current terminal electrically connected to the first current source; and a second current terminal electrically connected to the second differential circuit. A first transistor;
A control terminal to which the reference signal is input; a first current terminal electrically connected to the second current source; and a second current terminal electrically connected to the third differential circuit. A second transistor;
A variable resistance circuit having a plurality of field-effect transistors each having a source commonly connected to a first current terminal of the first transistor and each drain commonly connected to a first current terminal of the second transistor; ,
With
Each gate of the plurality of field effect transistors is supplied with a linearity adjustment signal for switching between an on state in which the drain and the source are conductive and an off state in which the drain and the source are blocked. A variable gain amplifier.

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