JP2003168937A - Variable gain type differential amplifying circuit, and multiplying circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable gain type differential amplifier which can materialize distortion on and under a certain level, and a multiplying circuit using it. <P>SOLUTION: The emitter of a transistor 1 is connected to a node N11, a resistor 51 is connected between the node N11 and a node N12, and a resistor 52 is connected between the node N12 and a grounding terminal. The emitter of a transistor 2 is connected to a node N21, a resistor 61 is connected between the node N21 and a node N22, and a resistor 62 is connected between the node N22 and a grounding terminal. An FET 71 is connected between the nodes N11 and N21, and an FET 72 is connected between the nodes N12 and N22. The gates of the FETs 71 and 72 are connected to a control terminal NG, which receives control voltage AGC via resistors 81 and 82, respectively. The resistors 51, 52, 61, and 62, and FETs 71 and 72 constitute a variable resistance circuit 30. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain type differential amplifier and a multiplication circuit using the same.

[0002]

2. Description of the Related Art Conventionally, a variable gain type differential amplifier (a differential amplifier circuit with a variable gain function) has been used. In integrated circuits using Si (silicon) devices such as bipolar transistors and MOSFETs (metal oxide field effect transistors), as a variable gain differential amplifier, an amplifier having a Gilbert-type configuration and an OTA (operational transconductance amplifier) are used.
The mainstream is an amplifier having a ductance amplifier configuration.

An amplifier having a Gilbert type structure has a wide variable gain range, but is inferior in terms of power consumption and noise characteristics. Therefore, in mobile communication and the like, an OTA configuration in which a variable resistance circuit including a FET switch and the like is provided in a differential amplifier is generally used.

FIG. 12 is a circuit diagram showing a structure of a conventional variable gain type differential amplifier having an OTA structure.

The variable gain differential amplifier shown in FIG. 12 is a bipolar transistor (hereinafter abbreviated as transistor) 1
01, 102, resistors 103, 104, 105, 106 and an n-MOSFET (hereinafter abbreviated as FET) 10
It is composed of 7. The FET 107 is the variable resistance circuit 20.
Configure 0.

The base of the transistor 101 is the input signal R
It is connected to an input terminal NI1 that receives Fin (+), and the base of the transistor 102 is connected to an input terminal NI2 that receives an input signal RFin (-). Input signal RFi
n (+) and RFin (-) are differential inputs. The collectors of the transistors 101 and 102 are each a resistor 10
Power supply terminal N for receiving power supply voltage Vcc via 3, 104
Connected to VC. The emitters of the transistors 101 and 102 are connected to the ground terminal via the resistors 105 and 106, respectively. Also, the transistors 101, 1
The collector of 02 is connected to the output terminals NO1 and NO2, respectively. Output signals RFout (+) and RFout (-) are derived from the output terminals NO1 and NO2, respectively. The output signals RFout (+) and RFout (-) are differential outputs.

An FET 107 is connected between the nodes N1 and N2 connected to the emitters of the transistors 101 and 102. The gate of the FET 107 is connected to the control terminal NG that receives the control voltage AGC via the resistor 110.

In the variable gain type differential amplifier of FIG.
Applying the control voltage AGC to the gate of T107, FET1
Gain control is performed by changing the source-drain resistance of 07. For example, when the FET 107 is turned on, maximum gain and low noise characteristics can be obtained. In this case, it is suitable for amplifying a minute high frequency signal. Also, F
When the ET 107 is turned off, the amount of attenuation becomes maximum (minimum gain) and the distortion characteristic is improved. In this case, it becomes strong against cross modulation in a state where the electric field strength is high.

[0009]

In the above variable gain type differential amplifier, the FET 107 of the variable resistance circuit 200 is used.
Continuous gain control can be performed by changing the control voltage applied to the gate of the.

However, the variable resistance circuit 200 of the variable gain type differential amplifier described above has a strong non-linearity in the control voltage region near the pinch-off voltage of the FET. As a result, the distortion characteristics deteriorate near the specific control voltage.
Therefore, when performing continuous gain control, the distortion characteristics of the variable gain differential amplifier deteriorate when a control voltage that increases waveform distortion is applied to the FET.

An object of the present invention is to provide a variable gain type differential amplifier capable of realizing distortion below a certain level and a multiplication circuit using the same.

[0012]

A variable gain differential amplifier according to the present invention includes a variable impedance circuit, a first terminal for receiving a first input signal, and a first load via a first load. Via a first transistor having a second terminal connected to the first potential and a third terminal connected to the variable impedance circuit, a first terminal receiving a second input signal, and a second load A second transistor having a second terminal connected to the first potential and a third terminal connected to the variable impedance circuit, wherein the variable impedance circuit includes a third terminal of the first transistor and a third terminal of the first transistor. One or more first resistance elements connected between the second potential and one or more first resistance elements, and one or more second resistance elements connected between the third terminal of the second transistor and the second potential. , At least one first resistor required And one end of the at least one second resistance element and between the other end of the at least one first resistance element and the other end of the at least one second resistance element, respectively, and are common. And a plurality of switching elements having a control terminal for receiving the control voltage.

In the variable gain differential amplifier according to the present invention, the first and second input signals are differentially amplified by the first and second transistors.

In this case, when a current flows from the first potential to the second potential through the first load, the first transistor and the at least one first resistance element, a voltage drop occurs in the first resistance element. . Further, when a current flows from the first potential to the second potential through the second load, the second transistor and the at least one second resistance element, a voltage drop occurs in the second resistance element. As a result, the potentials at one ends of the plurality of switching elements are different and the potentials at the other ends of the plurality of switching elements are also different. In this case, since the common control voltage is applied to the control terminals of the plurality of switching elements, the voltages of the control terminals for one end and the other end of the plurality of switching elements are different. This is equivalent to applying different control voltages to the plurality of switching elements. As a result, when the control voltage is changed to perform continuous gain control, rapid deterioration of the distortion characteristic at a specific control voltage is suppressed. Therefore, a variable gain type differential amplifier capable of realizing distortion below a certain level is realized.

The plurality of switching elements may be a plurality of field effect transistors having gates that receive a common control voltage.

In this case, the source potentials of the plurality of field effect transistors are different, and the drain potentials of the plurality of field effect transistors are different. Here, since a common control voltage is applied to the gates of the plurality of field effect transistors, the gate voltages with respect to the source and the drain of the plurality of field effect transistors are different. This is equivalent to applying different control voltages to the plurality of field effect transistors. As a result, when the control voltage is changed to perform continuous gain control, rapid deterioration of the distortion characteristic at a specific control voltage is suppressed.

The one or more first resistance elements connect the first resistance connected between the third terminal of the first transistor and the first node, and the first node and the second potential. Second to receive
A second resistor connected between the third resistor and a third resistor connected between the third terminal of the second transistor and the third node. And a fourth resistor connected between the third node and a fourth node receiving the second potential, and the plurality of switching elements are connected to the third terminal of the first transistor. It may include a first switching element connected between the third terminal of the second transistor and a second switching element connected between the first node and the third node.

In this case, the potential at one end of the first switching element differs from the potential at one end of the second switching element due to the voltage drop at the first resistor, and the first switching due to the voltage drop at the third resistor. The potential of the other end of the element is different from the potential of the other end of the second switching element. Therefore, different control voltages are applied to the first and second switching elements. As a result, distortion below a certain level can be realized.

The one or more first resistance elements include a first resistance connected between the third terminal of the first transistor and the first node receiving the second potential, and the one or more first resistance elements are included. Second
The resistance element of the second transistor and the third terminal of the second transistor
A second resistor connected between the second resistor and a second node receiving the potential of the plurality of switching elements, the plurality of switching elements having a third terminal of the first transistor and a third terminal of the second transistor. A first switching element connected between the first switching element and the first switching element;
May include a second switching element connected between the node and the second node.

In this case, the potential at one end of the first switching element differs from the potential at one end of the second switching element due to the voltage drop at the first resistor, and the first switching due to the voltage drop at the second resistor. The potential of the other end of the element is different from the potential of the other end of the second switching element. Therefore, different control voltages are applied to the first and second switching elements. As a result, distortion below a certain level can be realized.

The one or more first resistance elements include a first resistor connected between the third terminal of the first transistor and the first node, and a first node and a second node. One or more second resistance elements including a second resistance connected between the second resistance and a third resistance connected between the second node and a third node receiving the second potential. Is a fourth resistor connected between the third terminal of the second transistor and the fourth node, and a fifth resistor connected between the fourth node and the fifth node. , A sixth node receiving the fifth node and the second potential
A sixth resistor connected between the first node and the fourth node, and the plurality of switching elements includes a first switching element connected between the first node and the fourth node, and a second node. And a second switching element connected between the fifth node and the fifth node.

In this case, the potential at one end of the first switching element differs from the potential at one end of the second switching element due to the voltage drop at the second resistor, and the first switching due to the voltage drop at the fifth resistor. The potential of the other end of the element is different from the potential of the other end of the second switching element. Therefore, different control voltages are applied to the first and second switching elements. As a result, distortion below a certain level can be realized.

The one or more first resistance elements connect the first resistance connected between the third terminal of the first transistor and the first node, and the first node and the second potential. Second to receive
A second resistor connected between the third resistor and a third resistor connected between the third terminal of the second transistor and the third node. And a fourth resistor connected between the third node and a fourth node receiving the second potential, and the plurality of switching elements include a first node and a third node. A first switching element connected between the first node and the second node and a second switching element connected between the second node and the fourth node.

In this case, the potential at one end of the first switching element differs from the potential at one end of the second switching element due to the voltage drop at the second resistor, and the first switching due to the voltage drop at the fourth resistor. The potential of the other end of the element is different from the potential of the other end of the second switching element. Therefore, different control voltages are applied to the first and second switching elements. As a result, distortion below a certain level can be realized.

Each of the first and second transistors is
It may be a bipolar transistor or a field effect transistor.

The variable gain type differential amplifier is connected to the second terminal of the first transistor, and is connected to the first output terminal for deriving the first output signal and the second terminal of the second transistor. And a second output terminal for deriving a second output signal.

In this case, the first and second output signals indicating the result of the differential amplification of the first and second input signals are derived as differential outputs at the first and second output terminals.

The multiplication circuit according to the present invention has first, second, third, and third terminals each having a first terminal, a second terminal, and a third terminal.
A fourth terminal includes a fourth transistor, a fifth transistor, and a sixth transistor, and a variable impedance circuit, the first terminal of the first transistor receives the first input signal, and the second terminal of the first transistor via the first load. 1 potential, the third terminal is connected to the second terminal of the fifth transistor, the first terminal of the second transistor receives the second input signal, and the second terminal is connected to the second terminal.
Connected to the first potential via the load of the third transistor, the third terminal is connected to the second terminal of the fifth transistor, the first terminal of the third transistor receives the second input signal, and The second terminal is connected to the first potential via the first load,
Is connected to the second terminal of the sixth transistor,
The first terminal of the fourth transistor receives the first input signal, the second terminal is connected to the second potential through the second load, and the third terminal is the second terminal of the sixth transistor. The first terminal of the fifth transistor receives the third input signal, and the first terminal of the sixth transistor is connected to the fourth terminal of the fifth transistor.
The variable impedance circuit is connected to the third terminal of the fifth transistor and the second potential.
At least one of the above first resistance element, at least one second resistance element connected to the third terminal of the sixth transistor and the second potential, and at least one end of at least one first resistance element One second resistance element and one end of at least one first resistance element and the other end of at least one second resistance element, and receive a common control voltage. And a plurality of switching elements having control terminals.

In the multiplication circuit according to the present invention,
The fourth transistor differentially amplifies the first and second input signals, the fifth and sixth transistors differentially amplify the third and fourth input signals, and the first and second inputs The result of the differential amplification of the signal is multiplied by the result of the differential amplification of the third and fourth input signals.

In this case, from the first potential to the first and second
Through the load and the first and second transistors to the fifth transistor and further to the second potential through the fifth transistor and the at least one first resistive element, A voltage drop occurs in the resistance element. In addition, a current flows from the first potential to the sixth transistor through the first and second loads and the third and fourth transistors, and further through the sixth transistor and at least one second resistance element. When a current flows to the potential of 2, a voltage drop occurs in the second resistance element. As a result, the potentials at one ends of the plurality of switching elements are different and the potentials at the other ends of the plurality of switching elements are also different. In this case, since the common control voltage is applied to the control terminals of the plurality of switching elements, the voltages of the control terminals for one end and the other end of the plurality of switching elements are different. This is equivalent to applying different control voltages to the plurality of switching elements. As a result, when the control voltage is changed to perform continuous gain control, rapid deterioration of the distortion characteristic at a specific control voltage is suppressed.
Therefore, a multiplication circuit that can realize distortion below a certain level is realized.

The plurality of switching elements may be a plurality of field effect transistors having gates that receive a common control voltage.

In this case, the source potentials of the plurality of field effect transistors are different, and the drain potentials of the plurality of field effect transistors are also different. Here, since a common control voltage is applied to the gates of the plurality of field effect transistors, the gate voltages with respect to the source and the drain of the plurality of field effect transistors are different. This is equivalent to applying different control voltages to the plurality of field effect transistors. As a result, when the control voltage is changed to perform continuous gain control, rapid deterioration of the distortion characteristic at a specific control voltage is suppressed.

The one or more first resistance elements connect the first resistance connected between the third terminal of the fifth transistor and the first node, the first node and the second potential. Second to receive
A second resistor connected between the third resistor connected to the third node of the sixth transistor and the third resistor connected to the third node of the sixth transistor. And a fourth resistor connected between the third node and a fourth node receiving the second potential, and the plurality of switching elements are connected to the third terminal of the fifth transistor. It may include a first switching element connected between the third terminal of the sixth transistor and the second switching element connected between the first node and the third node.

In this case, the potential at one end of the first switching element differs from the potential at one end of the second switching element due to the voltage drop at the first resistor, and the first switching due to the voltage drop at the third resistor. The potential of the other end of the element is different from the potential of the other end of the second switching element. Therefore, different control voltages are applied to the first and second switching elements. As a result, distortion below a certain level can be realized.

The one or more first resistance elements include a first resistance connected between the third terminal of the fifth transistor and the first node receiving the second potential, and the one or more first resistance elements are included. Second
The resistance element of the third transistor of the sixth transistor and the second terminal of the sixth transistor.
A second resistor connected between the second resistor and a second node for receiving the potential of the plurality of switching elements, the plurality of switching elements having a third terminal of the fifth transistor and a third terminal of the sixth transistor. A first switching element connected between the first switching element and the first switching element;
May include a second switching element connected between the node and the second node.

In this case, the potential at one end of the first switching element differs from the potential at one end of the second switching element due to the voltage drop at the first resistor, and the first switching due to the voltage drop at the second resistor. The potential of the other end of the element is different from the potential of the other end of the second switching element. Therefore, different control voltages are applied to the first and second switching elements. As a result, distortion below a certain level can be realized.

The one or more first resistance elements include a first resistor connected between the third terminal of the fifth transistor and the first node, and a first node and a second node. One or more second resistance elements including a second resistance connected between the second resistance and a third resistance connected between the second node and a third node receiving the second potential. Is a fourth resistor connected between the third terminal of the sixth transistor and the fourth node, and a fifth resistor connected between the fourth node and the fifth node. , A sixth node receiving the fifth node and the second potential
A sixth resistor connected between the first node and the fourth node, and the plurality of switching elements includes a first switching element connected between the first node and the fourth node, and a second node. And a second switching element connected between the fifth node and the fifth node.

In this case, the potential at one end of the first switching element differs from the potential at one end of the second switching element due to the voltage drop at the second resistor, and the first switching due to the voltage drop at the fifth resistor. The potential of the other end of the element is different from the potential of the other end of the second switching element. Therefore, different control voltages are applied to the first and second switching elements. As a result, distortion below a certain level can be realized.

The one or more first resistance elements connect the first resistance connected between the third terminal of the fifth transistor and the first node, the first node and the second potential. Second to receive
A second resistor connected between the third resistor connected to the third node of the sixth transistor and the third resistor connected to the third node of the sixth transistor. And a fourth resistor connected between the third node and a fourth node receiving the second potential, and the plurality of switching elements include a first node and a third node. A first switching element connected between the first node and the second node and a second switching element connected between the second node and the fourth node.

In this case, the potential at one end of the first switching element differs from the potential at one end of the second switching element due to the voltage drop at the second resistor, and the first switching due to the voltage drop at the fourth resistor. The potential of the other end of the element is different from the potential of the other end of the second switching element. Therefore, different control voltages are applied to the first and second switching elements. As a result, distortion below a certain level can be realized.

Each of the first to sixth transistors may be a bipolar transistor or a field effect transistor.

The multiplication circuit is connected to the second terminals of the first and third transistors, and has a first output terminal for deriving a first output signal and second terminals of the second and fourth transistors. And a second output terminal for deriving the second output signal.

In this case, the first and second output signals indicating the multiplication result of the differential amplification result of the first and second input signals and the differential amplification result of the third and fourth input signals are The differential output is led to the first and second output terminals.

[0044]

1 is a circuit diagram showing the configuration of a variable gain type differential amplifier according to a first embodiment of the present invention.

The variable gain type differential amplifier shown in FIG. 1 includes bipolar transistors (hereinafter abbreviated as transistors) 1.
2, resistors 3, 4, 51, 52, 61, 62, 81, 82
And n-MOSFET (hereinafter abbreviated as FET) 7
1, 72. Resistors 3, 4, 51, 52,
61 and 62 function as constant current sources.

The base of the transistor 1 has an input signal RFi.
It is connected to an input terminal NI1 receiving n (+), and the base of the transistor 2 is connected to an input terminal NI2 receiving an input signal RFin (-). Input signal RFin
(+) And RFin (-) are differential inputs. The collectors of the transistors 1 and 2 are connected to the power supply terminal NVC which receives the power supply voltage Vcc through the resistors 3 and 4, respectively.

The collectors of the transistors 1 and 2 are
They are connected to the output terminals NO1 and NO2, respectively. Output signals RFout from the output terminals NO1 and NO2 respectively
(+) And RFout (-) are derived. Output signal RF
out (+) and RFout (-) are differential outputs.

The emitter of the transistor 1 is the node N11.
, The resistor 51 is connected between the node N11 and the node N12, and the resistor 52 is connected between the node N12 and the ground terminal. The emitter of the transistor 2 is connected to the node N21, the resistor 61 is connected between the node N21 and the node N22, and the resistor 62 is connected between the node N22 and the ground terminal.

An FET 71 is connected between the nodes N11 and N21, and an FET 72 is connected between the nodes N12 and N22. The gates of the FETs 71 and 72 are connected to the control terminal NG that receives the control voltage AGC via the resistors 81 and 82, respectively. Resistors 51, 52, 61, 62
The FETs 71 and 72 form the variable resistance circuit 30.

In this embodiment, the transistor 1 is the first
Transistor, the transistor 2 corresponds to a second transistor, and the FETs 71 and 72 correspond to switching elements. The resistor 3 corresponds to the first load, the resistor 4 corresponds to the second load, the resistors 51 and 52 correspond to the first resistance element, and the resistors 61 and 62 correspond to the second resistance element. To do. Further, the variable resistance circuit 30 corresponds to a variable impedance circuit.

The resistors 3 and 4 have the same resistance value, and the resistor 5
1, 61 have the same resistance value, and resistors 52, 62 have the same resistance value. Here, the resistance values of the resistors 51 and 61 are RE1, and the resistance values of the resistors 52 and 62 are RE2.
Further, the emitter current of the transistors 1 and 2 is IE.

When the emitter current IE of the transistor 1 flows through the variable resistance circuit 30, the resistances 51, 51 connected in series are connected.
A voltage drop occurs at 52. The voltage drop across the resistor 51 is R
E1 x IE and the voltage drop due to the resistor 52 is RE2 x
Become IE. Similarly, the voltage drop across the resistor 61 is RE1.
× IE, and the voltage drop due to the resistor 62 is RE2 × IE
Becomes As a result, the source potential of the FET 71 and FE
The potential of the source of T72 is different, and the potential of the drain of FET71 and the potential of the drain of FET72 are different. That is, the potential difference between the node N11 and the node N12 is RE
1 × IE, and the potential difference between the node N21 and the node N22 also becomes RE1 × IE.

Since the common control voltage AGC is applied to the gates of the FETs 71 and 72, the gate-source voltage and the gate-drain voltage of the FET 71 are different from the gate-source voltage and the gate-drain voltage of the FET 72. This is equivalent to applying different control voltages to the gates of the FETs 71 and 72. Therefore, when the control voltage with the highest non-linearity is applied to the FET 71, the control voltage with the lowest non-linearity is applied to the FET 72. On the contrary, when the control voltage with the highest non-linearity is applied to the FET 72,
A control voltage with low linearity will be applied to.
As a result, when the control voltage AGC is changed to perform continuous gain control, abrupt deterioration of the distortion characteristic of the variable gain differential amplifier at a specific control voltage AGC is suppressed.

Here, the distortion characteristics of the variable gain type differential amplifier of the present embodiment of FIG. 1 and the variable gain type differential amplifier of FIG. 12 are compared. FIG. 2 is a diagram showing calculation results of control voltage dependence of distortion characteristics in the variable gain differential amplifier of the present embodiment of FIG. 1 and the conventional variable gain differential amplifier of FIG. Here, the control voltage AGC is changed according to the change of the input power, and the third-order distortion is calculated under the operating condition where the output power is constant.

As shown in FIG. 2, in the variable gain type differential amplifier of the present embodiment of FIG. 1, compared with the conventional variable gain type differential amplifier of FIG. Second-order distortion is reduced, and third-order distortion at the control voltage indicated by symbol B is increased. As a result, the maximum value of the third-order distortion is reduced, and the distortion characteristics are flat in a wide control voltage range.

As described above, in the variable gain type differential amplifier of the present embodiment, distortion below a certain level can be realized.

FIG. 3 is a circuit diagram showing the structure of a variable gain type differential amplifier according to the second embodiment of the present invention.

The variable gain type differential amplifier of FIG. 3 is different from the variable gain type differential amplifier of FIG. 1 in the variable resistance circuit 30 between the node N12 and the ground terminal and the node N2.
The point is that the resistors 52 and 62 are not connected between 2 and the ground terminal. The configuration of the other parts of the variable gain differential amplifier of FIG. 3 is the same as the configuration of the variable gain differential amplifier of FIG.

Also in the variable gain type differential amplifier of the present embodiment, the distortion characteristic is improved over a wide range of the variable gain range. In particular, the two FETs 7 of the variable resistance circuit 30
Since the effective control voltage difference of 1 and 72 can be increased, it is possible to separate the peak positions where the distortion characteristics deteriorate in the variable gain range.

FIG. 4 is a circuit diagram showing the structure of a variable gain type differential amplifier according to the third embodiment of the present invention.

The variable gain differential amplifier of FIG. 4 differs from the variable gain differential amplifier of FIG. 1 in that in the variable resistance circuit 30, a resistor 50 is further connected between the emitter of the transistor 1 and the node N11. The resistor 60 is further connected between the emitter of the transistor 2 and the node N21. The configuration of the other parts of the variable gain differential amplifier of FIG. 4 is the same as the configuration of the variable gain differential amplifier of FIG.

In the variable gain type differential amplifier of this embodiment, the effective control voltage difference between the two FETs 71 and 72 of the variable resistance circuit 30 is different from that of the variable gain type differential amplifier of the second embodiment. However, it is possible to realize distortion below a certain level.

FIG. 5 is a circuit diagram showing the structure of a variable gain type differential amplifier according to the fourth embodiment of the present invention.

The variable gain type differential amplifier of FIG. 5 differs from the variable gain type differential amplifier of FIG. 1 in that in the variable resistance circuit 30, a resistor 50 is connected between the emitter of the transistor 1 and the node N11. A resistor 60 is connected between the emitter of the transistor 2 and the node N21,
Is not connected between the node N22 and the ground terminal and between the node N22 and the ground terminal. The configuration of the other parts of the variable gain differential amplifier of FIG. 5 is the same as the configuration of the variable gain differential amplifier of FIG.

In the variable gain type differential amplifier of the present embodiment, there is a limit to the reduction of the noise figure, but the variable resistance circuit 3
The difference between the effective control voltages of the two FETs 71 and 72 of 0 can be increased, and distortion below a certain level can be realized.

FIG. 6 is a circuit diagram showing the structure of a variable gain type differential amplifier according to the fifth embodiment of the present invention.

The variable gain type differential amplifier of FIG. 6 is different from the variable gain type differential amplifier of FIG. 1 in that in the variable resistance circuit 30, (m + 1) resistors are provided between the emitter of the transistor 1 and the ground terminal. , 5k, ..., 5m are connected in series, and (m + 1) resistors 60, ..., 6k, ..., 6m are connected in series between the emitter of the resistance transistor 2 and the ground terminal. , ..., 5k, ..., 5m nodes N11, ..., N1k, ..., N1m and resistors 60, ...,
Nodes N21, ..., N2k, ..., N between 6k, ..., 6m
2m and FET71, ..., 7k, ..., 7m respectively
Is connected. Here, m is an integer of 3 or more. The gates of the FETs 71, ..., 7k, ..., 7m are
, 8k, ..., 8m are connected to the control terminal NG which receives the control voltage AGC, respectively. Figure 6
Includes resistors 5k, 6k, 8k, 8k + 1 and FET7
Only k, 7k + 1 are shown. Where k is 0,
…, M. The configuration of the other parts of the variable gain differential amplifier of FIG. 6 is the same as the configuration of the variable gain differential amplifier of FIG.

Also in the variable gain type differential amplifier of the present embodiment, distortion below a certain level can be realized.

In this case, the resistors 50, ..., 5k, ..., 5 connected between the emitter of the transistor 1 and the ground terminal.
m and the number of resistors 60, ..., 6k, ..., 6m connected between the emitter of the resistance transistor 2 and the ground terminal and the number of FETs 71, ..., 7k ,. While the maximum value of the third-order distortion in the above is further reduced, the third-order distortion is increased in a wider region of other control voltage.

Therefore, according to the characteristics required for the variable gain type differential amplifier, the variable gain type differential amplifier having the optimum characteristics among the variable gain type differential amplifiers of the first to fifth embodiments is selected. select.

FIG. 7 is a circuit diagram showing the configuration of a Gilbert-type multiplication circuit (mixer) according to the sixth embodiment of the present invention.

Gilbert-type multiplication circuit (mixer) of FIG.
Is a bipolar transistor (hereinafter abbreviated as transistor) 1, 2, 21, 22, 23, 24, a resistor 3,
4, 51, 52, 61, 62, 81, 82 and n-M
It is composed of OSFETs (hereinafter abbreviated as FETs) 71 and 72. The resistors 3, 4, 51, 52, 61, 62 function as a constant current source. The resistors 51, 52, 61, 62 and the FETs 71, 72 form the variable resistance circuit 30.

The base of the transistor 1 is the input signal RFi.
It is connected to an input terminal NI1 receiving n (+), and the base of the transistor 2 is connected to an input terminal NI2 receiving an input signal RFin (-). Input signal RFin
(+) And RFin (-) are differential inputs. Transistors 21 and 22 are inserted between the collector of the transistor 1 and the output terminals NO1 and NO2, respectively. Also, the collector of the transistor 2 and the output terminals NO1, NO
Transistors 23 and 24 are respectively inserted between the two. The bases of the transistors 21 and 24 are input signals L
It is connected to an input terminal NI3 that receives Oin (+), and the bases of the transistors 22 and 23 are input signals LOin (−).
It is connected to the input terminal NI4 that receives the signal. Input signal L
Oin (+) and LOin (-) are differential inputs. The collectors of the transistors 21 and 23 are connected to the power supply terminal NVC which receives the power supply voltage Vcc via the resistor 3.
The collectors of the transistors 22 and 24 are connected to the power supply terminal NVC via the resistor 4.

The configuration of the other parts of the Gilbert type multiplication circuit of FIG. 7 is the same as the configuration of the variable gain type differential amplifier of FIG.

In this embodiment, the transistor 1 is the first
, The transistor 2 corresponds to a second transistor, the transistor 21 corresponds to a third transistor, the transistor 22 corresponds to a fourth transistor, the transistor 23 corresponds to a fifth transistor, The transistor 24 corresponds to the sixth transistor. The FETs 71 and 72 correspond to switching elements.
The resistor 3 corresponds to the first load, the resistor 4 corresponds to the second load, the resistors 51 and 52 correspond to the first resistance element, and the resistors 61 and 62 correspond to the second resistance element. To do. Further, the variable resistance circuit 30 corresponds to a variable impedance circuit.

Here, one differential input signal is RF = RF
in (+)-RFin (-), the other differential input signal is LO = LOin (+)-LOin (-), and the differential output signal is IF = IFout (+)-IFout (-). Further, the frequency of the differential input signal RF is f _RF , the frequency of the differential input signal LO is f _LO , and the differential output signal IF
If the frequency of is f _IF , the following equation holds.

F _IF = f _RF ± f _LO For example, the differential input signal R
The frequency f _RF of F is set to 1.1 GHz, and the differential input signal LO
When the frequency f _LO of 1 is set to 1 GHz, the frequency f _IF of the differential output signal _IF is 2.1 GHz and 100 MHz.
Therefore, the Gilbert-type multiplication circuit of FIG.
By taking out the frequency f _IF of Hz, it can be used as a down converter.

In the Gilbert type multiplication circuit of FIG. 7,
Since the common control voltage AGC is applied to the gates of the FETs 71 and 72, the gate-source voltage and the gate-drain voltage of the FET 71 are different from the gate-source voltage and the gate-drain voltage of the FET 72. this is,
This is equivalent to applying different control voltages to the gates of the FETs 71 and 72. Therefore, when the control voltage with the highest non-linearity is applied to the FET 71,
A control voltage that reduces the non-linearity is applied to. On the contrary, when the control voltage having the highest non-linearity is applied to the FET 72, the control voltage having the low linearity is applied to the FET 71. As a result, when the control voltage AGC is changed to perform continuous gain control, abrupt deterioration of the distortion characteristic of the variable gain differential amplifier at a specific control voltage AGC is suppressed.

As described above, in the Gilbert type multiplication circuit of the present embodiment, distortion below a certain level can be realized.

FIG. 8 is a circuit diagram showing the structure of the Gilbert type multiplication circuit according to the seventh embodiment of the present invention.

The Gilbert-type multiplying circuit of FIG. 8 differs from the Gilbert-type multiplying circuit of FIG. 7 in that in the variable resistance circuit 30, between the node N12 and the ground terminal and the node N2.
The point is that the resistors 52 and 62 are not connected between 2 and the ground terminal. The configuration of the other parts of the variable gain differential amplifier shown in FIG. 8 is the same as the configuration of the variable gain differential amplifier shown in FIG. 7.

Also in the Gilbert type multiplication circuit of the present embodiment, the distortion characteristic is improved over a wide range of the variable gain range. In particular, the two FETs 7 of the variable resistance circuit 30
Since the effective control voltage difference of 1 and 72 can be increased, it is possible to separate the peak positions where the distortion characteristics deteriorate in the variable gain range.

FIG. 9 is a circuit diagram showing the structure of the Gilbert type multiplication circuit according to the eighth embodiment of the present invention.

The Gilbert-type multiplication circuit of FIG. 9 differs from the Gilbert-type multiplication circuit of FIG. 7 in that in the variable resistance circuit 30, a resistor 50 is further connected between the emitter of the transistor 1 and the node N11, and The point is that a resistor 60 is further connected between the emitter and the node N21. The configuration of the other parts of the Gilbert-type multiplication circuit of FIG. 9 is similar to the configuration of the Gilbert-type multiplication circuit of FIG. 7.

In the Gilbert-type multiplication circuit of this embodiment, the difference between the effective control voltages of the two FETs 71 and 72 of the variable resistance circuit 30 is made larger than that of the Gilbert-type multiplication circuit of the seventh embodiment. However, distortion below a certain level can be realized.

FIG. 10 is a circuit diagram showing the structure of the Gilbert type multiplication circuit according to the ninth embodiment of the present invention.

The Gilbert-type multiplication circuit of FIG. 10 differs from the Gilbert-type multiplication circuit of FIG. 7 in that in the variable resistance circuit 30, the resistor 50 is connected between the emitter of the transistor 1 and the node N11 and the emitter of the transistor 2 is connected. A resistor 60 is connected between the node N1 and the node N21,
2 is not connected to the ground terminal and between the node N22 and the ground terminal, the resistors 52 and 62 are not connected. Figure 1
The configuration of the other parts of the Gilbert-type multiplication circuit of 0 is the same as the configuration of the Gilbert-type multiplication circuit of FIG.

In the Gilbert-type multiplication circuit of this embodiment, there is a limit to the reduction of noise figure, but the variable resistance circuit 3
The difference between the effective control voltages of the two FETs 71 and 72 of 0 can be increased, and distortion below a certain level can be realized.

FIG. 11 is a circuit diagram showing the structure of a Gilbert type multiplication circuit according to the tenth embodiment of the present invention.

The Gilbert-type multiplication circuit of FIG. 11 differs from the Gilbert-type multiplication circuit of FIG. 7 in that in the variable resistance circuit 30, (m + 1) resistors 50, ..., Between the emitter of the transistor 1 and the ground terminal. , 5m are connected in series, and (m + 1) resistors 60, ..., 6k, ..., 6m are connected in series between the emitter of the resistance transistor 2 and the ground terminal, and resistors 50 ,. ,,, Nodes N11, ..., N1k, ..., N1m and resistors 60 ,.
Nodes N21, ..., N2k, ..., N between 6k, ..., 6m
2m and FET71, ..., 7k, ..., 7m respectively
Is connected. Here, m is an integer of 3 or more. The gates of the FETs 71, ..., 7k, ..., 7m are
, 8k, ..., 8m are connected to the control terminal NG which receives the control voltage AGC, respectively. Figure 1
1 includes resistors 5k, 6k, 8k, 8k + 1 and a FET
Only 7k and 7k + 1 are shown. Where k is 0,
…, M. The configuration of the other parts of the Gilbert-type multiplication circuit of FIG. 11 is the same as the configuration of the Gilbert-type multiplication circuit of FIG. 7.

Even in the Gilbert-type multiplication circuit of this embodiment, distortion below a certain level can be realized.

As described above, in the above embodiment, by using the variable resistance circuit 30, a variable gain differential amplifier and a Gilbert type multiplication circuit having low noise characteristics and low distortion characteristics are realized with a simple circuit configuration. To be done.

In particular, the FETs 71, 7 of the variable resistance circuit 30
Since the common control voltage AGC is applied to 2, 7k and 7k + 1, the gain control can be easily performed.

In the above embodiment, bipolar transistors are used as the first to sixth transistors, but MOSFETs are used as the first to sixth transistors.
Other transistors such as MESFET (metal semiconductor field effect transistor) may be used.

In the above embodiment, the resistors 3 and 4 are used as the first and second loads, but MOSFETs, MESFETs, bipolar transistors, inductors, transformers, etc. are used as the first and second loads. Other elements may be used.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a variable gain differential amplifier according to a first embodiment of the present invention.

FIG. 2 is a diagram showing calculation results of control voltage dependence of distortion characteristics in the variable gain differential amplifier of the present embodiment of FIG. 1 and the variable gain differential amplifier of FIG.

FIG. 3 is a circuit diagram showing a configuration of a variable gain type differential amplifier according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a variable gain type differential amplifier according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a variable gain differential amplifier according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a variable gain differential amplifier according to a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a Gilbert-type multiplication circuit according to a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a Gilbert-type multiplication circuit according to a seventh embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a Gilbert-type multiplication circuit according to an eighth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a Gilbert-type multiplication circuit according to a ninth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of a Gilbert-type multiplication circuit according to a tenth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration of a conventional variable gain differential amplifier.

[Explanation of symbols]

1, 2, 21, 22, 23, 24 Transistors 3, 4, 50, 51, 52, 5k, 60, 61, 62,
6k, 80, 81, 82, 8k, 8k + 1 resistors 71, 72, 7k, 7k + 1 FET 30 variable resistance circuits NI1, NI2, NI3, NI4 input terminals NO1, NO2 output terminals NG1, NG2 control terminals NVC power supply terminals N11, N12, N21, N22 node RFin (+), RFin (-), RFin, LOin
(+), LOin (-), LOin input signals RFout (+), RFout (-), RFout, I
Fout (+), IFout (-), IFout output signal Vcc power supply voltage AGC control voltage

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5J066 AA01 AA12 CA21 CA41 FA10                       HA02 HA10 HA18 HA25 HA26                       HA39 KA06 KA12 MA21 ND01                       ND11 ND28 PD02 TA02                 5J090 AA01 AA12 CA21 CA41 FA10                       GN01 GN08 HA02 HA10 HA18                       HA25 HA26 HA39 KA06 KA12                       MA21 TA02                 5J100 LA10 QA01 QA03 SA00                 5J500 AA01 AA12 AC21 AC41 AF10                       AH02 AH10 AH18 AH25 AH26                       AH39 AK06 AK12 AM21 AT02                       DN01 DN11 DN28 DP02

Claims (10)

[Claims] 1. A variable impedance circuit, a first terminal for receiving a first input signal, a second terminal connected to a first potential via a first load, and the variable impedance circuit. First having a third terminal
And a first terminal for receiving a second input signal, a second terminal connected to the first potential via a second load, and a third terminal connected to the variable impedance circuit. A second transistor having the variable impedance circuit, wherein the variable impedance circuit includes one or more first resistance elements connected between the third terminal of the first transistor and a second potential; At least one second resistance element connected between the third terminal of the second transistor and the second potential; and at least one end of at least one first resistance element and at least one
And a common control voltage, which are respectively connected to one end of one second resistance element and between the other end of the at least one first resistance element and the other end of the at least one second resistance element. And a plurality of switching elements having control terminals for receiving the variable gain differential amplifier. 2. The one or more first resistance elements are a first resistance connected between the third terminal of the first transistor and a first node, and the first node. And a second resistor connected between a second node receiving the second potential and the second resistor, wherein the one or more second resistance elements are connected to the third terminal of the second transistor. A third resistor connected between the third node and a fourth node; and a fourth resistor connected between the third node and a fourth node receiving the second potential, A switching element of the first transistor connected between the third terminal of the first transistor and the third terminal of the second transistor.
2. The variable gain type differential amplifier according to claim 1, further comprising: a switching element of 1., and a second switching element connected between the first node and the third node. 3. The one or more first resistance elements are first resistances connected between the third terminal of the first transistor and a first node receiving the second potential. And a second resistance element connected between the third terminal of the second transistor and a second node receiving the second potential. A plurality of switching elements, the first switching element is connected between the third terminal of the first transistor and the third terminal of the second transistor.
2. The variable gain type differential amplifier according to claim 1, further comprising: a switching element according to claim 1, and a second switching element connected between the first node and the second node. 4. The one or more first resistance elements include a first resistor connected between the third terminal of the first transistor and a first node, and the first node. And a second resistor connected between the second node and a second node, and a third resistor connected between the second node and a third node receiving the second potential, The one or more second resistance elements include a fourth resistor connected between the third terminal of the second transistor and a fourth node, the fourth node and the fifth node. A fifth resistor connected between and, and a sixth resistor connected between the fifth node and a sixth node receiving the second potential, wherein the plurality of switching elements are A first switching element connected between the first node and the fourth node; Over de and the fifth second connected between a node of the variable gain differential amplifier according to claim 1, comprising a switching element. 5. The one or more first resistance elements include a first resistor connected between the third terminal of the first transistor and a first node, and the first node. And a second resistor connected between a second node receiving the second potential and the second resistor, wherein the one or more second resistance elements are connected to the third terminal of the second transistor. A third resistor connected between the third node and a fourth node; and a fourth resistor connected between the third node and a fourth node receiving the second potential, The switching element is a first switching element connected between the first node and the third node, and a second switching element connected between the second node and the fourth node. The variable gain differential amplifier according to claim 1, further comprising: 6. A first, second, third, fourth, fifth, and sixth transistor having a first terminal, a second terminal, and a third terminal, and a variable impedance circuit, The first terminal of the first transistor receives the first input signal, and the second terminal of the first transistor receives the first input signal via the first load.
The third terminal is connected to the second terminal of the fifth transistor, the first terminal of the second transistor receives a second input signal, and the second terminal is connected to the second input signal. Is connected to the first potential via a second load, the third terminal is connected to the second terminal of the fifth transistor, and the first terminal of the third transistor is connected to the second terminal of the fifth transistor. A terminal receives the second input signal, the second terminal is connected to the first potential via the first load, and the third terminal is the second terminal of the sixth transistor. A first terminal of the fourth transistor receives the first input signal, a second terminal of the fourth transistor is connected to the second potential via the second load, and A third terminal is connected to the second terminal of the sixth transistor, The first terminal of the fifth transistor receives a third input signal, the first terminal of the sixth transistor receives a fourth input signal, and the variable impedance circuit includes the fifth input signal. One or more first resistance elements connected to the third terminal of the transistor and a second potential; and one or more first resistance elements connected to the third terminal of the sixth transistor and the second potential. A second resistance element and at least one end of the at least one first resistance element and at least one
And a common control voltage, which are respectively connected to one end of one second resistance element and between the other end of the at least one first resistance element and the other end of the at least one second resistance element. A multiplying circuit having a plurality of switching elements having a control terminal for receiving. 7. The one or more first resistance elements are a first resistance connected between the third terminal of the fifth transistor and a first node, and the first node. And a second resistor connected between the second resistor receiving the second potential and the second node, wherein the one or more second resistance elements are connected to the third terminal of the sixth transistor. A third resistor connected between the third node and a fourth node; and a fourth resistor connected between the third node and a fourth node receiving the second potential, A switching element of the first transistor connected between the third terminal of the fifth transistor and the third terminal of the sixth transistor.
7. The multiplying circuit according to claim 6, further comprising: a switching element of 1), and a second switching element connected between the first node and the third node. 8. The at least one first resistance element is a first resistance connected between the third terminal of the fifth transistor and a first node receiving the second potential. And a second resistance element connected between the third terminal of the sixth transistor and a second node receiving the second potential. A plurality of switching elements, a first switching element connected between the third terminal of the fifth transistor and the third terminal of the sixth transistor.
7. The multiplying circuit according to claim 6, further comprising: a switching element according to claim 1, and a second switching element connected between the first node and the second node. 9. The one or more first resistance elements include a first resistor connected between the third terminal of the fifth transistor and a first node, and the first node. And a second resistor connected between the second node and a second node, and a third resistor connected between the second node and a third node receiving the second potential, The one or more second resistance elements include a fourth resistor connected between the third terminal of the sixth transistor and a fourth node, the fourth node and the fifth node. A fifth resistor connected between and, and a sixth resistor connected between the fifth node and a sixth node receiving the second potential, wherein the plurality of switching elements are A first switching element connected between the first node and the fourth node; Multiplier circuit according to claim 6, characterized in that it comprises a second switching element connected between the over-de and the fifth node. 10. The one or more first resistance elements include a first resistor connected between the third terminal of the fifth transistor and a first node, and the first node. And a second resistor connected between the second resistor receiving the second potential and the second node, wherein the one or more second resistance elements are connected to the third terminal of the sixth transistor. A third resistor connected between the third node and a fourth node; and a fourth resistor connected between the third node and a fourth node receiving the second potential, The switching element is a first switching element connected between the first node and the third node, and a second switching element connected between the second node and the fourth node. 7. The multiplication circuit according to claim 6, further comprising: