GB2356307A

GB2356307A - A low-noise wideband RF differential cascode amplifier with matched input impedance

Info

Publication number: GB2356307A
Application number: GB9926726A
Authority: GB
Inventors: David A Moore
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1999-11-11
Filing date: 1999-11-11
Publication date: 2001-05-16
Anticipated expiration: 2019-11-11
Also published as: GB9926726D0; GB2356307B; GB2356307A8

Abstract

A wideband RF amplifier has a differential cascode arrangement 14,16,18,20. Input matching resistors 34,36 are cross-coupled between the bases of the input transistors 14,16 and the emitters of the cascode output transistors 18,20. The amplifier provides increased gain, reduced noise and reduced intermodulation. It is suitable for use in the antenna booster/splitter section of a video cassette recorder (VCR).

Description

AMPLIFIER

Field of the Invention

This invention relates to amplifiers, and particularly to radio frequency (RF) amplifiers.

Background of the Invention

A low noise radio frequency (RF) amplifier must usually present a resistive input impedance of SOn or 750. However, typical amplifier designs do not naturally produce input resistances of that magnitude, and this problem is normally addressed in one of the following ways: a) If the RF amplifier has a naturally high input impedance, a parallel resistor can be employed to 20 produce an appropriate input resistance. Unfortunately, this substantially degrades noise performance. An otherwise noiseless amplifier would exhibit a 3dB noise figure using this technique. Similar problems arise when placing a 25 resistor in series with a very low input impedance amplifier. b) An inverting amplifier having a gain of JAI can be given an input resistance of Rs by placing a feedback resistor having a value of approximately 30 Rs (1+ JAI) between input and output. Using this method, the noise contribution of the resistor can be greatly reduced compared with the former approach. Unfortunately, the desired amplifier gain may be insufficient to effect a substantial noise reduction, while additional gain introduced solely to overcome this problem may give rise to problems with signal handling and linearity. Also, there will be poor isolation between the output and input of the amplifier.

c) Reactive elements can be used in tandem to provide a resistive input impedance over a band of frequencies, e.g., a series inductance in the emitter lead of a bipolar transistor is often used. While useful for discrete designs, this approach becomes impractical in the case of a silicon integrated circuit and is difficult to implement over a wide frequency range.

A broad band amplifier may be needed for applications such as the antenna booster/splitter function found in a video cassette recorder (VCR). Any such amplifier must handle all T.V. (and other) signals between 40MHz and 90OMHz. While only low gain is needed (3dB - 6dB), a good noise figure (6dB) is required as well as exceptionally high intercepts (IP3 = +15dBm, and IP2 = +43dBm). The amplifier must also exhibit very good reverse isolation, i.e., attenuation between output and input. It is difficult to meet these stringent requirements employing the known techniques while using a minimum of operating current.

It is therefore an object of the present invention to provide a differential amplifier in which the above problems may be overcome, or at least alleviated.

Brief Summary of the Invention

Accordingly, the invention provides an amplifier as claimed in claim 1.

Brief Description of the Drawing

One e mbodiment of the invention will now be more fully described, by way of example, with reference to the accompanying drawing, in which:

FIG. 1 shows a schematic circuit diagram of a low-noise RF amplifier incorporating the invention; and FIG. 2 shows a schematic circuit diagram of a low-noise RF amplifier of FIG. 1 illustrating certain voltages present during operation of the circuit.

Detailed Description

As shown in Fig. 1, a low-noise RF differential amplifier 10 suitable for use in the antenna booster/splitter section of a video cassette recorder (VCR) includes differential input terminals IN1 and IN2, and differential output terminals OP1 and OP2. A differential cascode stage 12 is formed by transistor pairs 14 & 16 and 18 & 20. The base electrodes of the transistors 14 and 16 are connected respectively to the differential input terminals IN1 and IN2. The transistors 14 and 16 have their emitter electrodes connected, via resistors 22 and 24 respectively, to a node 26. The transistors 14 and 16 have their collector electrodes connected respectively to emitter electrodes of the transistors 18 and 20. The transistors 18 and 20 have their collector electrodes connected, via resistors 28 and 30 respectively, to a rail 32. The collector electrodes of the transistors 18 and 20 are also connected respectively to the output terminals OP1 and OP2. The base electrodes of the transistors 18 and 20 are connected in common to the negative terminal of a bias voltage source Vb, whose positive terminal is connected to the rail 32.

The rail 32 is also connected to the positive terminal of a supply voltage source Vcc, whose negative terminal is connected to ground and (via a current source Ib) to the node 26.

As will be explained further below, the base electrode of the transistor 14 is connected, via a resistor 34, to the collector electrode of transistor 16. The base electrode of the transistor 16 is connected, via a resistor 36, to the collector electrode of transistor 14. The base electrodes of the transistors 14 and 16 are mutually connected via a resistor 38 (which is in practice constituted by the source resistance of an antenna, not shown, to which the circuit is connected). The values of the resistors are chosen such that resistors 34 and 36 have the same nominal value Rs/2, and the resistor 38 has a nominal value Rs which is twice that of each of the resistors 34 and 36. Further, the resistors 22 and 24 have the same nominal value RE, and the resistors 28 and 30 have the same nominal value RL.

It will be appreciated that in the differential amplifier 10, the differential cascode stage 12 provides inherently good isolation between output and input, very low second order distortion (owing to its symmetry), and high IP3 intercept produced by emitter degeneration. The input resistance of the amplifier is fundamentally as discussed in section a) above, except that instead of input resistors being conventionally taken from base electrodes of input transistors to a bias source, the two input resistors 34 and 36 cross-connect the base electrodes of the input transistors 14 and 16 to the emitter electrodes of the transistors 20 and 18 instead.

This yields two very important advantages:

Firstly, the current flowing in the two matched input resistors 34 and 36 is not wasted. It appears directly in the output and contributes to gain. Thus, the gain (Gm) of the circuit is increased by (Gm + 1/Rs)/Gm.

Secondly, there is some cancellation of noise generated by the resistors. Thus, noise current is reduced from Gm/2 to (Gm/2 - 1/2 Rs). Noise cancellation is total for the case where Gm/2 = 1/(2 Rs), i.e, where Gm = 1/Rs Also, this differential amplifier does not suffer any significant reduction in intermodulation performance, 5 Operation of the differential amplifier 10 can be understood by considering an input voltage Vin applied across the differential input terminals IN1 and IN2, as shown in FIG. 2. In the following analysis it will be assumed that transistor emitter resistances (re = KT/qIe) are zero.

The application of the differential input signal Vin results in an output current, Io, in the collector of either Q3 or Q4 given by Io = Vin (Gm + 1/Rs) and hence the output voltage at either OPI or OP2 will be given by Vo = Vin (Gm + 1/Rs) RL i.e., the current flowing in the input load resistors is added to the output current.

Next, consider a noise voltage, Vn, generated by one of the input load resistors. Applied across the total loop resistance of (Rs + 2 (Rs/2)), it will produce a voltage between the input terminals INI and IN2 of Vn/2 and a current in the collectors of Ql or Q2, and, hence in Q3 and Q4, of Vn/2 (Gm).

However, a noise current of Vn/(2 Rs) will also flow in the loop resistance, 2Rs, and hence in the emitters of Q3 and Q4, which is in antiphase to that in Ql or Q2. Hence the total noise current will be reduced to 7 Vn (Gm/2 - 1/(2.Rs)).

As discussed above, when Rs 1/Gm, complete cancellation of the bias resistor noise will occur It will be appreciated that, although one embodiment of the invention has been described in detail, various modifications and improvements can be made by a person skilled in the art without departing from the scope of 10 the present invention.

Claims

1. An amplifier comprising: first and second transistors each having base, collector and emitter electrodes, the first and second transistors being connected to receive across their base electrodes a differential input signal; and third and fourth transistors each having base, collector and emitter electrodes, the third and fourth transistors being connected in cascode arrangement with their emitter electrodes coupled respectively to the collector electrodes of the third and second transistors, to produce a outputs across the collector electrodes of the third and fourth transistors, characterised by: first resistance means coupled between the base electrode of the first transistor and the collector electrode of the second transistor; and second resistance means coupled between the base electrode of the second transistor and the collector electrode of the first transistor.

2. An amplifier as claimed in claim 1 wherein the first and second resistance means have substantially equal resistance values which are substantially half of the amplifier's source resistance.

3. An amplifier as claimed in claim 2 wherein the transconductance of the amplifier is substantially equal to the sum the amplifier's gain and half the reciprocal of the resistance value of the first or second resistance means.

4. An amplifier as claimed in claim 1, 2 or 3 wherein the amplifier is an RF amplifier.

S. An amplifier substantially as hereinbefore described with reference to the accompanying drawings.