CN112579517A - CPCIE main control board based on Feiteng platform - Google Patents

CPCIE main control board based on Feiteng platform Download PDF

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Publication number
CN112579517A
CN112579517A CN202011630331.5A CN202011630331A CN112579517A CN 112579517 A CN112579517 A CN 112579517A CN 202011630331 A CN202011630331 A CN 202011630331A CN 112579517 A CN112579517 A CN 112579517A
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China
Prior art keywords
port
cpcie
electrically connected
connector
chip
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CN202011630331.5A
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Chinese (zh)
Inventor
陈齐杰
李国利
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Hefei Zhuoyi Hengtong Information Security Co Ltd
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Hefei Zhuoyi Hengtong Information Security Co Ltd
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Priority to CN202011630331.5A priority Critical patent/CN112579517A/en
Publication of CN112579517A publication Critical patent/CN112579517A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention provides a CPCIE main control board based on a Feiteng platform. The CPCIE main control board based on the Feiteng platform comprises: the system comprises a Feiteng processor, a mega-chip bridge chip, a high cloud CPLD, a CPCIE connector, an SATA connector and a mSATA connector; the Feiteng processor is provided with a first PCIE x 4 port and a GPIO port, the first PCIE x 4 port is electrically connected with the mega-chip bridge chip, and the GPIO port is electrically connected with the high-cloud CPLD; the mega-chip bridge chip is provided with a first SATA port, a second SATA port and a third SATA port, the first SATA port is electrically connected with the CPCIE connector, the second SATA port is electrically connected with the SATA connector, and the third SATA port is electrically connected with the mSATA connector. The invention adopts devices made in China, has high product safety, strong autonomous controllability, abundant signal storage interfaces, high data storage capacity and strong product competitiveness.

Description

CPCIE main control board based on Feiteng platform
Technical Field
The invention relates to the technical field of computers, in particular to a CPCIE main control board based on a Feiteng platform.
Background
The Compact Peripheral Component Interconnect (CPCI) system has the features of Hot Swap, high openness, high reliability and robustness, which makes it very widely used in the industrial control field. As time goes on, the PCI bus in the CPCI system is replaced by the more advanced and faster high-speed serial computer expansion bus standard (PCIE), and the corresponding CPCI system is also replaced by the CPCIE system.
In an industrial automation control system, the application of industrial personal computer equipment is not separated. The industrial personal computer mainboard is like the brain of whole equipment, and the height of whole industrial personal computer performance, function often determines the main control board. The main control board communicates with the peripheral board card through a high-speed bus, receives data sent by the peripheral board card, analyzes and processes the data, and sends information and instructions to the peripheral board card to control the peripheral board card to work. The CPCIE main control board is a main control board that uses the PCIE bus to perform data transmission.
However, the chip platforms of the existing CPCIE master control board are basically produced by foreign enterprises, and the chip platforms of the foreign platforms are completely closed to us in the core technology, so that the core technical principle of the chip platforms cannot be deeply mastered, the technical risk and the potential safety hazard uncontrollable in maintenance exist in product use, the product is seriously imported, the product is seriously controlled, and the risk that the product cannot be produced due to the fact that the chip platforms are out of supply at any time exists. In recent years, through the arrangement of national science and technology development plans, the domestic computer software and hardware technology makes major breakthrough, such as more representative high-performance processors represented by dragon cores, Feiteng, Shenwei, Mega cores, crystal quenching and the like. In order to ensure autonomous controllability, safety and the like, some CPCIE main control board core boards adopting domestic chip platforms have appeared at present, but the CPCIE main control board core boards still have some defects, for example, a signal interface is single, various peripheral requirements cannot be met, functions are not rich enough, and diversified requirements of users cannot be met.
Disclosure of Invention
The invention aims to provide a CPCIE main control board based on a Feiteng platform, which has abundant storage signal interfaces, can enhance the data storage capacity of a product and improve the product competitiveness.
In order to achieve the above object, the present invention provides a CPCIE main control board based on a soar platform, including: the system comprises a Feiteng processor, a mega-chip bridge chip, a high cloud CPLD, a CPCIE connector, an SATA connector and a mSATA connector;
the Feiteng processor is provided with a first PCIE x 4 port and a GPIO port, the first PCIE x 4 port is electrically connected with the mega-chip bridge chip, and the GPIO port is electrically connected with the high-cloud CPLD;
the mega-chip bridge chip is provided with a first SATA port, a second SATA port and a third SATA port, the first SATA port is electrically connected with the CPCIE connector, the second SATA port is electrically connected with the SATA connector, and the third SATA port is electrically connected with the mSATA connector.
The Feiteng processor is further provided with a PCIE x 8 port, a second PCIE x 4 port and a PCIE x 1 port, wherein the PCIE x 8 port, the second PCIE x 4 port and the PCIE x 1 port are electrically connected with the CPCIE connector respectively.
The CPCIE main control board based on the Feiteng platform further comprises a first level shifter and a clock chip, the Feiteng processor is further provided with a first I2C port and a second I2C port, the first level shifter is electrically connected with the first I2C port and the CPCIE connector respectively, and the clock chip is electrically connected with the second I2C port.
The CPCIE main control board based on the Feiteng platform further comprises a first Debug connector and a second Debug connector, the Feiteng processor is further provided with a JTAG port and a first UART port, the first Debug connector is electrically connected with the JTAG port, and the second Debug connector is electrically connected with the first UART port.
The CPCIE main control board based on the Feiteng platform further comprises a second level shifter, an RS232 conversion chip and an SPI Flash, the Feiteng processor is further provided with a second UART port and a QSPI port, the second level shifter is electrically connected with the second UART port, the RS232 conversion chip is electrically connected with the second level shifter and the CPCIE connector respectively, and the SPI Flash is electrically connected with the QSPI port.
The CPCIE main control board based on the Feiteng platform further comprises a memory chip and a network card chip, the Feiteng processor is further provided with a memory port and a GMAC port, the memory chip is electrically connected with the memory port, and the network card chip is electrically connected with the GMAC port and the CPCIE connector respectively.
The CPCIE main control board based on the Feiteng platform further comprises: the fan, the power management module, the indicator light and the temperature sensor are respectively and electrically connected with the high cloud CPLD.
The CPCIE main control board based on the Feiteng platform further comprises USB connectors, the mega-chip bridge chip (2) is further provided with 6 USB2.0 ports, 2 of the 6 USB2.0 ports are electrically connected with the two USB connectors respectively, and the rest 4 ports are electrically connected with the CPCIE connectors.
The type of the Feiteng processor is Feiteng FT-2000/4, the type of the megachip bridge chip is megachip ZX-200, and the type of the high cloud CPLD is high cloud GW1N-4KLQFP 100.
The memory chip is a DDR4 memory chip, and the type of the network card chip is Yutai Citong PHY YT8521 SH.
The invention has the beneficial effects that: the invention provides a CPCIE main control board based on a Feiteng platform, which comprises: the system comprises a Feiteng processor, a mega-chip bridge chip, a high cloud CPLD, a CPCIE connector, an SATA connector and a mSATA connector; the Feiteng processor is provided with a first PCIE x 4 port and a GPIO port, the first PCIE x 4 port is electrically connected with the mega-chip bridge chip, and the GPIO port is electrically connected with the high-cloud CPLD; the mega-chip bridge chip is provided with a first SATA port, a second SATA port and a third SATA port, the first SATA port is electrically connected with the CPCIE connector, the second SATA port is electrically connected with the SATA connector, and the third SATA port is electrically connected with the mSATA connector. The invention adopts devices made in China, has high product safety, strong autonomous controllability, abundant signal storage interfaces, high data storage capacity and strong product competitiveness.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
fig. 1 is a schematic block diagram of a CPCIE main control board based on a soar platform according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 1, the present invention provides a CPCIE main control board based on a soar platform, including: a soar processor 1, a mega-chip bridge chip 2, a Complex Programming Logic Device (CPLD) 3, a CPCIE connector 4, a Serial Advanced Technology Attachment (SATA) connector 5, and a mini SATA (mini SATA, mSATA) connector 6;
the soar processor 1 has a first high-speed serial computer expansion bus (PCIE) × 4 port and a General-purpose input/output (GPIO) port, the first PCIE × 4 port is electrically connected to the mega-chip bridge chip 2, and the GPIO port is electrically connected to the high-cloud CPLD 3;
the mega-chip bridge chip 2 is provided with a first SATA port, a second SATA port and a third SATA port, the first SATA port is electrically connected with the CPCIE connector 4, the second SATA port is electrically connected with the SATA connector 5, and the third SATA port is electrically connected with the mSATA connector 6.
It should be noted that the CPCIE main control board based on the soar platform of the present invention is provided with the SATA connector 5 and the mSATA connector 6 at the same time, and can expand more SATA interfaces through the CPCIE connector 4, that is, the CPCIE main control board based on the soar platform of the present invention can expand multiple storage devices of multiple different storage signal interfaces at the same time, which can effectively improve the data storage capability of the product and expand the application range of the product.
Specifically, the FT processor 1 further has a PCIE × 8 port, a second PCIE × 4 port and a PCIE × 1 port, and the PCIE × 8 port, the second PCIE × 4 port and the PCIE × 1 port are electrically connected to the CPCIE connector 4 respectively.
Namely, the CPCIE main control board based on the Feiteng platform can be connected with PCIE multiplied by 8, PCIE multiplied by 4 and PCIE multiplied by 1 devices in an extensible way, PCIE expansion interfaces are rich, the device expansion capability is strong, and the CPCIE main control board has the characteristics of high bandwidth, high data transmission capability, shock resistance, corrosion resistance, stable and reliable working operation and the like.
Specifically, the CPCIE main control board for the soar platform further includes a first level shifter 7 and a clock chip 8, the soar processor 1 further includes a first Integrated Circuit bus (I2C) port and a second I2C port, the first level shifter 7 is electrically connected to the first I2C port and the CPCIE connector 4, and the clock chip 8 is electrically connected to the second I2C port.
Specifically, the model of the clock chip 8 can be selected from a domestic SD-3068 clock chip.
Further, the electrical connection between the CPCIE connector 4 and the first level shifter 7 may extend to an I2C interface.
Specifically, the CPCIE main control board for the FT platform further includes a first hardware Debug (Debug) connector 9 and a second Debug connector 10, the FT processor 1 further includes a Joint Test Action Group (JTAG) port and a first Universal Asynchronous Receiver/Transmitter (UART) port, the first Debug connector 9 is electrically connected to the JTAG port, and the second Debug connector 10 is electrically connected to the first UART port.
Specifically, the first Debug connector 9 and the second Debug connector 10 may be connected to the Debug module through external leads, and read the code running condition of the soar processor, so as to complete hardware debugging of the product and ensure the working stability of the product.
Specifically, the CPCIE main control board for the soar platform further includes a second level shifter 11, an RS232 conversion chip 12, and a Serial Peripheral Flash (SPI Flash)13, where the soar processor 1 further includes a second UART port and a 4-line SPI (Quad SPI Flash) port, the second level shifter 11 is electrically connected to the second UART port, the RS232 conversion chip 12 is electrically connected to the second level shifter 11 and the CPCIE connector 4, and the SPI Flash13 is electrically connected to the QSPI port.
Preferably, the RS232 conversion chip 12 is a domestic AT3232EUE RS232 conversion chip, and the CPCIE connector 4 is electrically connected to the RS232 conversion chip 12, so that 4 sets of RS232 interfaces can be expanded.
Specifically, the CPCIE main Control board for the soar platform further includes a memory chip 14 and a network card chip 15, the soar processor 1 further includes a memory port and a Gigabit Media Access Control (GMAC) port, the memory chip 14 is electrically connected to the memory port, and the network card chip 15 is electrically connected to the GMAC port and the CPCIE connector 4, respectively.
Preferably, the model is yutai dynasty PHY YT8521SH, the network card chip 15 can reach giga network speed, and compared with a hundred mega network card adopted by the existing CPCIE main control board, the network transmission speed is greatly improved. The CPCIE connector 4 is electrically connected to the network card chip 15, and can extend one gigabit network interface.
Specifically, the high cloud CPLD3 supports functions such as power management, indicator light control, fan control, and temperature acquisition, and accordingly, the CPCIE main control board based on the soar platform may further include: the high-cloud CPLD comprises a fan 16, a power management module 17, an indicator lamp 18 and a temperature sensor 19, wherein the fan 16, the power management module 17, the indicator lamp 18 and the temperature sensor 19 are respectively and electrically connected with the high-cloud CPLD 3.
Specifically, the CPCIE main control board for the soar platform further includes a Universal Serial Bus (USB) connector 20, the mega-chip bridge chip 2 further has 6 USB2.0 ports, 2 of the 6 USB2.0 ports are electrically connected to the two USB connectors 20, and the other 4 ports are electrically connected to the CPCIE connector 4. The CPCIE connector 4 is electrically connected with the 4 USB2.0 ports, and can expand 4 USB2.0 interfaces.
Specifically, the type of the Feiteng processor is Feiteng FT-2000/4, the type of the megachip bridge piece is megachip ZX-200, and the type of the high cloud CPLD is high cloud GW1N-4KLQFP 100.
Specifically, the memory chip 14 is a Double Data Rate (DDR 4) 4 th generation memory chip, the main frequency of the memory can reach 2133MHz, and the maximum memory can support 8GB storage, so that the memory performance is greatly improved compared with a DDR3 memory module adopted by the existing CPCIE main control board.
Therefore, the Feiteng platform-based CPCIE main control board has various different storage signal interface types, can meet the connection requirements of different storage modules, enlarges the use scene of products, has rich peripheral interfaces, and can meet the requirement of simultaneously connecting various peripherals, meanwhile, various chips adopted by the Feiteng platform-based CPCIE main control board are domestic chips, all devices meet the wide-temperature industrial level, can reliably and stably operate in the environment of-40-85 ℃, the whole product is completely independently controllable, has high safety, and can meet various use environments with higher requirements on safety and controllability.
In summary, the present invention provides a CPCIE main control board based on the soar platform, including: the system comprises a Feiteng processor, a mega-chip bridge chip, a high cloud CPLD, a CPCIE connector, an SATA connector and a mSATA connector; the Feiteng processor is provided with a first PCIE x 4 port and a GPIO port, the first PCIE x 4 port is electrically connected with the mega-chip bridge chip, and the GPIO port is electrically connected with the high-cloud CPLD; the mega-chip bridge chip is provided with a first SATA port, a second SATA port and a third SATA port, the first SATA port is electrically connected with the CPCIE connector, the second SATA port is electrically connected with the SATA connector, and the third SATA port is electrically connected with the mSATA connector. The invention adopts devices made in China, has high product safety, strong autonomous controllability, abundant signal storage interfaces, high data storage capacity and strong product competitiveness.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.

Claims (10)

1. A CPCIE master control board based on a Feiteng platform is characterized by comprising: the system comprises a Feiteng processor (1), a mega chip bridge chip (2), a high cloud CPLD (3), a CPCIE connector (4), an SATA connector (5) and a mSATA connector (6);
the Feiteng processor (1) is provided with a first PCIE x 4 port and a GPIO port, the first PCIE x 4 port is electrically connected with the mega-chip bridge chip (2), and the GPIO port is electrically connected with the high-cloud CPLD (3);
the mega-chip bridge chip (2) is provided with a first SATA port, a second SATA port and a third SATA port, the first SATA port is electrically connected with the CPCIE connector (4), the second SATA port is electrically connected with the SATA connector (5), and the third SATA port is electrically connected with the mSATA connector (6).
2. The FT platform-based CPCIE master control board according to claim 1, wherein the FT processor (1) further has a PCIE x 8 port, a second PCIE x 4 port and a PCIE x 1 port, and the PCIE x 8 port, the second PCIE x 4 port and the PCIE x 1 port are electrically connected to the CPCIE connector (4) respectively.
3. The FT platform-based CPCIE master control board according to claim 1, further comprising a first level shifter (7) and a clock chip (8), wherein the FT processor (1) further has a first I2C port and a second I2C port, the first level shifter (7) is electrically connected to the first I2C port and the CPCIE connector (4), respectively, and the clock chip (8) is electrically connected to the second I2C port.
4. The FT platform-based CPCIE master control board according to claim 1, further comprising a first Debug connector (9) and a second Debug connector (10), wherein the FT processor (1) further has a JTAG port and a first UART port, the first Debug connector (9) is electrically connected to the JTAG port, and the second Debug connector (10) is electrically connected to the first UART port.
5. The Feiteng platform-based CPCIE master control board according to claim 1, further comprising a second level shifter (11), an RS232 conversion chip (12) and an SPI Flash (13), wherein the Feiteng processor (1) further has a second UART port and a QSPI port, the second level shifter (11) is electrically connected to the second UART port, the RS232 conversion chip (12) is electrically connected to the second level shifter (11) and the CPCIE connector (4), respectively, and the SPI Flash (13) is electrically connected to the QSPI port.
6. The fizz platform-based CPCIE master control board of claim 1, further comprising a memory chip (14) and a network card chip (15), wherein the fizz processor (1) further has a memory port and a GMAC port, the memory chip (14) is electrically connected to the memory port, and the network card chip (15) is electrically connected to the GMAC port and the CPCIE connector (4), respectively.
7. The FT platform-based CPCIE master control board of claim 1, further comprising: the high-cloud CPLD comprises a fan (16), a power management module (17), an indicator lamp (18) and a temperature sensor (19), wherein the fan (16), the power management module (17), the indicator lamp (18) and the temperature sensor (19) are respectively and electrically connected with the high-cloud CPLD (3).
8. The FT platform-based CPCIE master control board according to claim 1, further comprising USB connectors (20), wherein the mega-bridge chip (2) further has 6 USB2.0 ports, 2 of the 6 USB2.0 ports are electrically connected to two USB connectors (20), and the other 4 ports are electrically connected to the CPCIE connectors (4).
9. The Feiteng platform based CPCIE master control board according to claim 1, wherein the model of the Feiteng processor is Feiteng FT-2000/4, the model of the mega-core bridge chip is mega-core ZX-200, and the model of the high-cloud CPLD is high-cloud GW1N-4KLQFP 100.
10. The FT platform-based CPCIE master control board according to claim 6, wherein the memory chip (14) is a DDR4 memory chip, and the network card chip (15) is Yutai Cheong PHY YT8521 SH.
CN202011630331.5A 2020-12-30 2020-12-30 CPCIE main control board based on Feiteng platform Pending CN112579517A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN207096979U (en) * 2017-09-02 2018-03-13 湖南长城银河科技有限公司 A kind of CPCI mainboards and computer based on Feiteng processor
CN207367115U (en) * 2017-11-09 2018-05-15 湖南长城银河科技有限公司 A kind of server master board and server based on Feiteng processor
CN207650794U (en) * 2017-11-15 2018-07-24 无锡军安电子科技有限公司 A kind of desktop mainboard based on Feiteng processor
CN210955055U (en) * 2020-02-18 2020-07-07 山东超越数控电子股份有限公司 Display control computer motherboard framework based on soar
CN211956463U (en) * 2020-03-12 2020-11-17 广州超云科技有限公司 I/O (input/output) bridge piece based on Feiteng processor
CN214202377U (en) * 2020-12-30 2021-09-14 合肥市卓怡恒通信息安全有限公司 CPCIE main control board based on Feiteng platform

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN207096979U (en) * 2017-09-02 2018-03-13 湖南长城银河科技有限公司 A kind of CPCI mainboards and computer based on Feiteng processor
CN207367115U (en) * 2017-11-09 2018-05-15 湖南长城银河科技有限公司 A kind of server master board and server based on Feiteng processor
CN207650794U (en) * 2017-11-15 2018-07-24 无锡军安电子科技有限公司 A kind of desktop mainboard based on Feiteng processor
CN210955055U (en) * 2020-02-18 2020-07-07 山东超越数控电子股份有限公司 Display control computer motherboard framework based on soar
CN211956463U (en) * 2020-03-12 2020-11-17 广州超云科技有限公司 I/O (input/output) bridge piece based on Feiteng processor
CN214202377U (en) * 2020-12-30 2021-09-14 合肥市卓怡恒通信息安全有限公司 CPCIE main control board based on Feiteng platform

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