CN112532030A - Surge current suppression circuit - Google Patents
Surge current suppression circuit Download PDFInfo
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- CN112532030A CN112532030A CN202011046844.1A CN202011046844A CN112532030A CN 112532030 A CN112532030 A CN 112532030A CN 202011046844 A CN202011046844 A CN 202011046844A CN 112532030 A CN112532030 A CN 112532030A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- Engineering & Computer Science (AREA)
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- Emergency Protection Circuit Devices (AREA)
- Direct Current Feeding And Distribution (AREA)
Abstract
The invention discloses a surge current suppression circuit, comprising: the method comprises the following steps: delay circuit, voltage stabilizing circuit, and suppression circuit. The suppression circuit comprises a field effect transistor and a power resistor and is used for suppressing the startup surge current; the electric stress and the thermal stress born by the field effect transistor at the moment of starting up are transferred to the power resistor, and the reliability of the power resistor is higher than that of the field effect transistor because the power resistor is a passive device. The embodiment of the invention also provides the electronic equipment. By adopting the embodiment of the invention, the problem that the insulating layer of the field effect tube is easy to be broken down in the long-term use process of the existing surge current suppression circuit is solved.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a surge current suppression circuit.
Background
The startup surge current suppression circuit of the power supply is usually realized by using a field effect tube. When the power-on device is started, the grid electrode of the field-effect tube is slowly charged through the delay circuit, and the field-effect tube works in a linear region at the moment, so that the startup surge current is restrained.
In practical use of the traditional circuit, the field effect tube bears current and voltage stress simultaneously when working in a linear region at the moment of starting up, and the superposition of the current and the voltage stress can cause a PN junction in the field effect tube to generate heat instantly. And because the time for heat accumulation is very short, the heat cannot be led out in an effective heat dissipation manner. In long-term use, the field effect transistor is damaged due to thermal stress, so that an insulating layer between a drain electrode and a source electrode of the field effect transistor is broken down, the drain electrode and the source electrode are short-circuited after the breakdown, the field effect transistor is equivalent to a lead with extremely low impedance, starting surge current cannot be inhibited, and the reliability of a power supply is low.
Disclosure of Invention
The invention aims to solve the problem that an insulating layer of a field effect tube is easy to break down in the long-term use process of the existing surge current suppression circuit, and provides the surge current suppression circuit and electronic equipment.
To achieve the above object, an embodiment of the present invention provides an inrush current suppression circuit, including: the circuit comprises a delay circuit, a voltage stabilizing circuit and a suppression circuit;
the positive end of the delay circuit is connected to the positive electrode of a power supply of an electrical system, and the negative end of the delay circuit, the negative end of the voltage stabilizing circuit and the negative end of the suppression circuit are connected to the negative electrode of the power supply of the electrical system; the positive end and the negative end of the delay circuit are input ends of the surge current suppression circuit, and the output end of the suppression circuit is the output end of the surge current suppression circuit;
the suppression circuit comprises a field effect transistor and a power resistor and is used for suppressing the startup surge current; the grid G of the field effect transistor is the positive terminal of the suppression circuit, and the source S of the field effect transistor is the negative terminal of the suppression circuit; a source S of the field effect transistor is connected with one end of the power resistor, a grid G of the field effect transistor is connected with the positive terminal of the voltage stabilizing circuit, and a drain D of the field effect transistor is connected with the other end of the power resistor; and the drain D of the field effect transistor is the output end of the suppression circuit.
As an improvement of the above scheme, the delay circuit includes a delay resistor and a delay capacitor, and is used for slowly charging the gate G of the field effect transistor;
one end of the delay resistor is a positive end of the delay circuit; the other end of the delay resistor is connected with the first end of the delay capacitor; and the second end of the delay capacitor is the negative end of the delay circuit.
As an improvement of the above scheme, the voltage stabilizing circuit comprises a voltage stabilizing resistor and a voltage stabilizing diode, and is used for stabilizing the voltage of the grid G of the field effect transistor;
the negative electrode of the voltage stabilizing diode is the positive electrode end of the delay circuit; the cathode of the voltage stabilizing diode is connected with one end of the voltage stabilizing resistor, and the anode of the voltage stabilizing diode is connected with the other end of the voltage stabilizing resistor; and the anode of the voltage stabilizing diode is the cathode end of the voltage stabilizing circuit.
As an improvement of the above scheme, the inrush current suppression circuit further includes a voltage reduction circuit; the voltage reduction circuit comprises a voltage reduction diode and a voltage reduction resistor and is used for discharging and reducing voltage of the time delay capacitor;
the cathode of the voltage reduction diode is the input end of the voltage reduction circuit, and the anode of the voltage reduction diode is connected with one end of the voltage reduction resistor; the other end of the voltage reduction resistor is a control end of the voltage reduction circuit;
the input end of the voltage reduction circuit is connected with the positive end of the delay circuit, and the control end of the voltage reduction circuit is connected with the first end of the delay capacitor.
As an improvement of the scheme, the field effect transistor is an N-channel field effect transistor.
An embodiment of the present invention further provides an electronic device, including the inrush current suppression circuit according to any one of the above embodiments.
Compared with the prior art, the surge current suppression circuit and the electronic equipment disclosed by the invention have the advantages that at the moment of starting up, the power supply voltage is applied to two ends of the filter capacitor, the power resistor limits the electric stress and the thermal stress born by the field effect tube at the moment of starting up in the traditional circuit of the surge current at the moment of starting up to be transferred to the power resistor, and the reliability of the power resistor is higher than that of the field effect tube because the power resistor is a passive device, so that the long-term reliability of the surge current suppression circuit and the whole power supply module is improved, and the later maintenance cost is reduced. In addition, after the grid voltage of the field effect transistor rises to the grid conduction threshold voltage, the field effect transistor works normally, and the grid voltage can be stabilized at the normal working voltage of the field effect transistor through the voltage stabilizing circuit, so that the field effect transistor with a larger safe working area is not required to be selected in the surge current suppression circuit, and the difficulty of selecting components is greatly reduced.
Drawings
Fig. 1 is a schematic diagram of an inrush current suppression circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another inrush current suppression circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a circuit for suppressing inrush current according to an embodiment of the present invention. The surge current suppression circuit comprises: a delay circuit 10, a voltage stabilizing circuit 11 and a suppression circuit 12.
The positive end of the delay circuit 10 is connected to the positive electrode of a power supply of an electrical system, and the negative end of the delay circuit 10, the negative end of the voltage stabilizing circuit 11 and the negative end of the suppression circuit 12 are connected to the negative electrode of the power supply of the electrical system; the positive terminal and the negative terminal of the delay circuit 10 are the input terminals of the inrush current suppression circuit 12, and the output terminal of the suppression circuit 12 is the output terminal of the inrush current suppression circuit.
The suppression circuit 12 comprises a field effect transistor V2 and a power resistor R3 and is used for suppressing the startup surge current; the grid G of the field-effect tube V2 is the positive terminal of the suppression circuit 12, and the source S of the field-effect tube V2 is the negative terminal of the suppression circuit; the source S of the field-effect transistor V2 is connected with one end of the power resistor, the grid G of the field-effect transistor V2 is connected with the positive end of the voltage stabilizing circuit 11, and the drain D of the field-effect transistor V2 is connected with the other end of the power resistor R3; the drain D of the fet V2 is the output of the suppression circuit 12.
In practical use of the traditional circuit, the field effect tube bears current and voltage stress simultaneously when working in a linear region at the moment of starting up, and the superposition of the current and the voltage stress can cause a PN junction in the field effect tube to generate heat instantly. And because the time for heat accumulation is very short, the heat cannot be led out in an effective heat dissipation manner. In long-term use, the field effect tube is damaged due to thermal stress, so that an insulating layer between a drain electrode and a source electrode of the field effect tube is broken down, the drain electrode and the source electrode are short-circuited after the breakdown, the field effect tube is equivalent to a lead with extremely low impedance, and the startup surge current cannot be inhibited.
After the surge current suppression circuit provided by the invention is applied to a power supply of an electrical system, at the moment of starting up, ViApplied across the filter capacitor C2, the power-on surge current is limited by the power resistor R3, as known from ohm's law: inrush current at startup
In general IwaveFor rated input current Ie3-5 times of the total weight of the compound, which can be known from ohm's law:
wherein, IeFor rated input current, P, of power supply using turn-on inrush current suppression circuitoη is the power supply efficiency, which is the rated output power of the power supply.
Gate voltage V of field effect transistor V2GSIs raised to VTHAt this time, V2 starts to operate in the saturation conduction region, and there is a low impedance between the drain and source, R3 is short-circuited, and current flows through the drain and source of V2. And the drain and source on-resistances R of V2D-S(on)The heat generated by conduction loss is slowly accumulated, so that the heat can be conducted away by using a conventional heat dissipation mode to ensure the long-term reliability of the LED lamp.
The main parameters of R3 are resistance, withstand voltage and instantaneous power. An alternative approach to R3 is given below by way of example:
when V2 is operating in the linear amplification region, current only charges C2 through R3. The voltage at the two ends of the C2 can be obtained by a capacitance charging and discharging formula
Therefore, the voltage V across R3R＝1-V(t) (4)
Therefore, the R3 instantaneous power is
The power resistor R3 may be selected according to the formulas (1) to (5).
Compared with the prior art, the surge current suppression circuit disclosed by the invention has the advantages that the power supply voltage V is generated at the moment of starting upiThe power resistor R3 is used for limiting the electric stress and the thermal stress born by the field effect transistor V2 in the traditional startup surge current circuit at the startup moment to be transferred to the power resistor R3, and the reliability of the power resistor R3 is higher than that of the field effect transistor V2 due to the fact that the power resistor R3 is a passive device, so that the long-term reliability of the surge current suppression circuit and the whole power module is improved, and the later maintenance cost is reduced. In addition, after the gate voltage of the field effect transistor V2 rises to the gate-on threshold voltage, the field effect transistor V2 works normally, and the gate voltage can be stabilized at the normal working voltage of the field effect transistor V2 by the voltage stabilizing circuit 12, so that the field effect transistor with a larger safe working area does not need to be selected in the surge current suppression circuit, and the difficulty of selecting components is greatly reduced.
Illustratively, the delay circuit 10 includes a delay resistor R1 and a delay capacitor C1, which is used to charge the gate G of the fet V2 slowly.
One end of the delay resistor R1 is the positive end of the delay circuit 10; the other end of the delay resistor R1 is connected with the first end of the delay capacitor C1; the second end of the delay capacitor C1 is the negative end of the delay circuit 10.
ViC1 is charged through R1, and the grid voltage V of the field effect transistor V2GSSlowly rises, VGSUp to the gate turn-on threshold voltage VTHIn the former case, V2 operates in a linear amplification region, where the drain and source are in high impedance, and current passes only through R3. The loss of the FET caused by the superposition of current and voltage stress during conduction is transferred to R3, and the reliability of the FET is higher than that of the FET because the power resistor is a passive device.
Illustratively, the voltage stabilizing circuit 11 comprises a voltage stabilizing resistor R2 and a voltage stabilizing diode V1, and is used for stabilizing the voltage of the gate G of the field effect transistor V2;
the cathode of the voltage stabilizing diode V1 is the anode end of the voltage stabilizing circuit 11; the cathode of the voltage stabilizing diode V1 is connected with one end of the voltage stabilizing resistor R2, and the anode of the voltage stabilizing diode V1 is connected with the other end of the voltage stabilizing resistor R2; the anode of the zener diode V1 is the cathode terminal of the voltage regulator circuit 11.
When V isGSIs raised to VTHThen, V2 works normally, V can be adjusted by resistor R2 and zener diode V1GSThe voltage is stabilized at the normal operating voltage of V2.
One method of choice for R1, R2, V1 and C1 is given below by way of example:
the main parameters of R1 are resistance, withstand voltage and power, and the main parameters of C1 are capacitance and withstand voltage.
According to the resistance value of R3 and the capacitance value of C2, the duration time t of the on-surge current is known by the formula of charging and discharging the capacitorwave＝3×R3×C2 (6)
R2 and V1 are selected according to the grid voltage resistance of V2, and V1 can be selected as a 15V voltage regulator tube.
Then, the voltage across R2
The R2 design should ensure that the input voltage fluctuation is VR2HoldingThe voltage is between the gate-on threshold voltage and the gate withstand voltage of V2 (generally 10V-15V can be selected). When R2 is damaged, V1 needs to be changed from ViBy supplying it with an operating current IZ (typically 5mA) via R1, then
C1 charging to VTHThe time t1 can be obtained from the equation (3), and the power of R1 can be obtained from the equation (5). R1 and C1 are selected so that t is t1＞twave。
In summary, the main parameters of R1, R2, V1 and C1 were determined.
Illustratively, the fet V2 is an N-channel fet.
An alternative method of V2 is given below by way of example:
the main parameter of V2 is the breakdown voltage V of drain and sourceDSSRated drain current IDDrain and source on-resistance RDS(on)And rated power PD. At ViWhen R3 is applied to C2, the maximum reverse voltage V borne by the drain and the source of V2D-S＝Vi. After V2 is completely conducted, it bears current I for a long timeD-S＝Ie. Therefore, when the main parameter of V2 is selected, a certain margin should be left in consideration of the temperature drift of the parameter, and the selection principle is as follows.
1) Breakdown voltage V of drain and sourceDSS＞1.5×VD-S；
2) Rated drain current ID＞3×Ie；
3) Drain and source on-resistance RDS(on)And rated power
And R isDS(on)It should be as low as possible.
Illustratively, referring to fig. 2, the inrush current suppression circuit further includes a voltage step-down circuit 14. The voltage reduction circuit comprises a voltage reduction diode V3 and a voltage reduction resistor R4 and is used for discharging and reducing the voltage of the time delay capacitor C1.
When the surge current suppression circuit in the embodiment is electrified repeatedly, the field effect transistor V2 is easy to break down due to heat accumulation; meanwhile, as the capacitor C1 cannot discharge and step down in time, the grid of the field effect transistor V2 is always conducted, and the field effect transistor V2 always works in a saturated conduction region, so that the startup surge current cannot be inhibited.
The voltage reducing circuit 14 is introduced in the embodiment, when the power-on is rapidly repeated, the voltage of C1 can be rapidly released through the voltage reducing diodes V3 and R4, and V isGSThe voltage is rapidly reduced to 0V, so that the capacitor C1 can achieve a time delay function during each time of startup time delay, and startup surge current is restrained.
An alternative method for V3 and R4 is given below by way of example:
the main parameter of V3 is reverse withstand voltage VRForward current IFAnd reverse recovery time trrThe main parameter of R4 is resistance. V3 has the maximum reverse withstand voltage V when the circuit works normallyiWhen the circuit is powered down, C1 quickly transfers V of V2 through V3 and R4GSDischarge rapidly to 0V. V3 requires a very short reverse recovery time when power is applied repeatedly at a fast rate. The selection principle is as follows:
1) v3 reverse withstand voltage VR＞2×Vi；
2) Forward current of V3
3) V3 selection ultrafast recovery diode with reverse recovery time trrTypically less than 50 ns;
in addition, considering the discharge current and the discharge time, R4 is generally selected to be 47 Ω.
An embodiment of the present invention further provides an electronic device, including the inrush current suppression circuit according to any one of the above embodiments.
In order to solve the problems in the background art, an embodiment of the present invention further provides an electronic device, including the inrush current suppression circuit according to any of the embodiments described above. For a specific working process of the inrush current suppression circuit, please refer to the working process of the inrush current suppression circuit described in the above embodiment, which is not described herein again.
Compared with the prior art, in the electronic equipment disclosed by the invention, at the moment of starting up, power supply voltage is applied to two ends of the filter capacitor, the electric stress and the thermal stress borne by the field effect tube in the surge current traditional circuit at the moment of starting up are limited by the power resistor to be transferred to the power resistor, and the reliability of the power resistor is higher than that of the field effect tube because the power resistor is a passive device, so that the long-term reliability of the surge current suppression circuit and the whole power supply module is improved, and the later maintenance cost is reduced. In addition, after the grid voltage of the field effect transistor rises to the grid conduction threshold voltage, the field effect transistor works normally, and the grid voltage can be stabilized at the normal working voltage of the field effect transistor through the voltage stabilizing circuit, so that the field effect transistor with a larger safe working area is not required to be selected in the surge current suppression circuit, and the difficulty of selecting components is greatly reduced.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that the above-described preferred embodiment should not be construed as limiting the present invention. The protection scope of the present invention shall be subject to the scope defined by the claims. It will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the spirit and scope of the invention, and these modifications and adaptations should be considered within the scope of the invention.
Claims (6)
1. An inrush current suppression circuit, comprising: the circuit comprises a delay circuit, a voltage stabilizing circuit and a suppression circuit;
the positive end of the delay circuit is connected to the positive electrode of a power supply of an electrical system, and the negative end of the delay circuit, the negative end of the voltage stabilizing circuit and the negative end of the suppression circuit are connected to the negative electrode of the power supply of the electrical system; the positive end and the negative end of the delay circuit are input ends of the surge current suppression circuit, and the output end of the suppression circuit is the output end of the surge current suppression circuit;
the suppression circuit comprises a field effect transistor and a power resistor and is used for suppressing the startup surge current; the grid G of the field effect transistor is the positive terminal of the suppression circuit, and the source S of the field effect transistor is the negative terminal of the suppression circuit; a source S of the field effect transistor is connected with one end of the power resistor, a grid G of the field effect transistor is connected with the positive terminal of the voltage stabilizing circuit, and a drain D of the field effect transistor is connected with the other end of the power resistor; and the drain D of the field effect transistor is the output end of the suppression circuit.
2. The inrush current suppression circuit of claim 1, wherein: the delay circuit comprises a delay resistor and a delay capacitor and is used for slowly charging the grid G of the field effect transistor;
one end of the delay resistor is a positive end of the delay circuit; the other end of the delay resistor is connected with the first end of the delay capacitor; and the second end of the delay capacitor is the negative end of the delay circuit.
3. The inrush current suppression circuit of claim 1, wherein: the voltage stabilizing circuit comprises a voltage stabilizing resistor and a voltage stabilizing diode and is used for stabilizing the voltage of the grid G of the field effect transistor;
the cathode of the voltage stabilizing diode is the anode end of the voltage stabilizing circuit; the cathode of the voltage stabilizing diode is connected with one end of the voltage stabilizing resistor, and the anode of the voltage stabilizing diode is connected with the other end of the voltage stabilizing resistor; and the anode of the voltage stabilizing diode is the cathode end of the voltage stabilizing circuit.
4. The inrush current suppression circuit of claim 2, wherein: the voltage reducing circuit is also included; the voltage reduction circuit comprises a voltage reduction diode and a voltage reduction resistor and is used for discharging and reducing voltage of the time delay capacitor;
the cathode of the voltage reduction diode is the input end of the voltage reduction circuit, and the anode of the voltage reduction diode is connected with one end of the voltage reduction resistor; the other end of the voltage reduction resistor is a control end of the voltage reduction circuit;
the input end of the voltage reduction circuit is connected with the positive end of the delay circuit, and the control end of the voltage reduction circuit is connected with the first end of the delay capacitor.
5. The inrush current suppression circuit of claims 1-4, wherein: the field effect transistor is an N-channel field effect transistor.
6. An electronic device comprising the inrush current suppression circuit according to any one of claims 1 to 4.
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| CN202011046844.1A CN112532030A (en) | 2020-09-28 | 2020-09-28 | Surge current suppression circuit |
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| CN202011046844.1A CN112532030A (en) | 2020-09-28 | 2020-09-28 | Surge current suppression circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140198549A1 (en) * | 2013-01-15 | 2014-07-17 | Agilent Technologies, Inc. | Energy dissipating device for dc power supplies |
| CN204068682U (en) * | 2014-08-23 | 2014-12-31 | 成都四威航空电源有限公司 | A kind of high-power low-loss surge restraint circuit |
| CN106026626A (en) * | 2016-06-29 | 2016-10-12 | 浪潮集团有限公司 | Surge current suppressor based on RC time delay circuit |
| CN110365200A (en) * | 2019-07-23 | 2019-10-22 | 珠海格力电器股份有限公司 | Circuit structure and PV air-conditioner system |
-
2020
- 2020-09-28 CN CN202011046844.1A patent/CN112532030A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140198549A1 (en) * | 2013-01-15 | 2014-07-17 | Agilent Technologies, Inc. | Energy dissipating device for dc power supplies |
| CN204068682U (en) * | 2014-08-23 | 2014-12-31 | 成都四威航空电源有限公司 | A kind of high-power low-loss surge restraint circuit |
| CN106026626A (en) * | 2016-06-29 | 2016-10-12 | 浪潮集团有限公司 | Surge current suppressor based on RC time delay circuit |
| CN110365200A (en) * | 2019-07-23 | 2019-10-22 | 珠海格力电器股份有限公司 | Circuit structure and PV air-conditioner system |
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Address after: 610000 No. 301, unit 2, building 7, No. 88, Tianchen Road, Chengdu high tech Zone, Chengdu, Sichuan Province Applicant after: Chengdu Juntao Technology Co.,Ltd. Applicant after: Shanghai Juntao Technology Co.,Ltd. Address before: 610000 No. 301, unit 2, building 7, No. 88, Tianchen Road, Chengdu high tech Zone, Chengdu, Sichuan Province Applicant before: Chengdu Juntao Technology Co.,Ltd. Applicant before: SHANGHAI JUNTAO POWER EQUIPMENT Co.,Ltd. |
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