CN214256123U - Surge current suppression circuit - Google Patents
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- CN214256123U CN214256123U CN202120323430.2U CN202120323430U CN214256123U CN 214256123 U CN214256123 U CN 214256123U CN 202120323430 U CN202120323430 U CN 202120323430U CN 214256123 U CN214256123 U CN 214256123U
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Abstract
The utility model discloses a surge current suppression circuit, which relates to the technical field of power switches, and comprises a primary anti-surge circuit, an anti-surge mode termination circuit, a transformer, an LLC secondary anti-surge circuit, a rectification filter circuit and a resistor R0; the primary anti-surge circuit comprises a gradual starting circuit, a resistor R5, a resistor R4, a resistor R3, a triode Q1, a triode Q2 and a MOS transistor Q4; the surge-proof mode termination circuit comprises a resistor R6, a resistor R7, a resistor R8, a voltage comparator, a voltage regulator tube D2 and a reference voltage V1; the LLC secondary anti-surge circuit comprises a transformer excitation inductor Lm, a resonance inductor Lr, a resonance capacitor Cr, an NTC thermistor and a relay; the rectifying and filtering circuit comprises a diode D3, a diode D4, a diode D5, a diode D6 and an electrolytic capacitor C0. The utility model discloses a surge current primary inhibition has reduced the impact of surge current to power supply device.
Description
Technical Field
The utility model belongs to the technical field of the switch technique and specifically relates to a surge current suppression circuit is related to.
Background
In the prior art, an output circuit of an LLC switching power supply generally adopts a capacitance filtering circuit, and at a moment of energization, since initial voltages on an output capacitor and a resonant capacitor are zero, an equivalent resistance value approaches to 0 Ω, an impedance value of an LLC resonant cavity is low, a surge current having a steady-state value of several tens of times is caused at a moment of capacitor charging, and particularly when the output capacitor and the resonant capacitor are increased, the surge impact current is larger. The overhigh surge current often causes the instantaneous Vds voltage of the power tube of the main circuit of the switching power supply to exceed the rated voltage, so that the power tube is broken down to cause short circuit and endanger other devices. Therefore, the inhibition of the startup surge current is the premise of ensuring the safety and reliability of the equipment.
In order to solve the problem of surge current caused by startup in the LLC switching power supply at the moment, the traditional method mostly adopts frequency conversion startup or PWM control, but the design of a controller for frequency conversion startup is relatively complex, if the startup frequency and a time constant are not well matched, the startup surge current is easily increased at the moment, and the startup in the PWM mode still has higher surge current for high-voltage input. The method is characterized in that a power resistor is used for suppressing surge current, the MOS tube is in short circuit with the power resistor after an output filter capacitor is fully charged, and working current flows through the MOS tube. The method provided by the invention can not simultaneously meet the requirements of simple design, low power consumption, high reliability, single applicability and no universality of the surge current suppression circuit.
Chinese patent CN201750601U provides a fet surge suppression high-power intelligent dimming multiple output power supply, which includes: a surge suppressing unit; an LLC resonance transformation unit; a synchronous rectification unit; more than one constant current output intelligent dimming unit; a power resistor in the surge suppressing unit is connected with the source electrode and the drain electrode of the field effect transistor in parallel, and the on-resistance of the field effect transistor is very small, so that the loss of a surge suppressing circuit is very low, and the overall efficiency of the power supply is improved. The utility model discloses an optimal design to LLC resonant network parameter obtains up to 95% output efficiency. When the constant-current output intelligent dimming unit circuit senses the infrared ray of a human body, the duty ratio of the output current is improved, and the average value of the output current is improved; on the contrary, when no one passes by, the duty ratio of the output current is reduced but the peak value is not reduced, so that the light emitting efficiency of the LED is ensured, and the problem that the light does not fall to the ground is avoided.
Chinese patent CN108963999A relates to the field of power electronics of airborne electronic devices, and in particular relates to an inrush current suppressor. The surge current suppressor is connected in series with a loop of an input power supply, and comprises: the power MOS tube is connected in series in a loop of the DC input negative terminal; the current measuring element is connected in a loop of the direct current input negative terminal in series and used for inputting the current of the power supply loop and converting the current into voltage; and the feedback circuit is respectively connected with the current measuring element and the power MOS tube, wherein when the voltage value detected by the current measuring element is greater than or equal to a first preset value, the power MOS tube is in a current limiting state. The surge current suppressor is advanced and reliable in principle, can realize the function of suppressing the start-up surge, and has the advantages of simple and reliable function realization, low power consumption, low cost, small occupied printed board area and light weight compared with the traditional mode.
The above patents all relate to the technical field of power switches, and firstly, the technical scheme of the patent CN201750601U is different from the scheme of the present application and the problem that light does not fall to the ground is solved; secondly main MOS pipe in patent CN108963999A had both worked in the saturation region and had work and non-saturation region, its loss greatly increased that generates heat, and the device life-span is shorter when efficiency is lower, uses parts such as multistage sampling, RC timing, opto-coupler isolation moreover for the whole complexity of circuit rises, and the cost increases. Based on the defects of the prior art, the surge current suppression circuit provided by the application effectively suppresses the surge current generated by circuit starting, greatly reduces the impact of the surge current on a power supply device, can timely terminate the anti-surge mode when equipment normally works, cannot influence the normal use of a power supply, and has the characteristics of low power consumption, simple circuit structure and high reliability. The application is applicable to various power supply topological structures because the application scene is combined with the power tube of the main circuit of the power supply.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a surge current suppression circuit.
In order to realize the utility model discloses a purpose, the utility model discloses a technical scheme as follows:
an inrush current suppression circuit comprises a primary anti-surge circuit, an anti-surge mode termination circuit, a transformer, an LLC secondary anti-surge circuit, a rectifier filter circuit and a resistor R0; the primary anti-surge circuit comprises a gradual starting circuit, a resistor R5, a resistor R4, a resistor R3, a triode Q1, a triode Q2 and a MOS transistor Q4; the gradual starting circuit comprises an electrolytic capacitor C1, a voltage regulator tube D1, a resistor R1, a resistor R2 and an MOS tube Q3; the surge-proof mode termination circuit comprises a resistor R6, a resistor R7, a resistor R8, a voltage comparator, a voltage regulator tube D2 and a reference voltage V1; the LLC secondary anti-surge circuit comprises a transformer excitation inductor Lm, a resonance inductor Lr, a resonance capacitor Cr, an NTC thermistor and a relay; the rectifying and filtering circuit comprises a diode D3, a diode D4, a diode D5, a diode D6 and an electrolytic capacitor C0; the LLC secondary anti-surge circuit is connected with the rectification filter circuit; the anti-surge mode termination circuit is connected with an output bus voltage of the rectifying and filtering circuit.
Further, the primary anti-surge circuit further comprises a power supply, the drain of a MOS (metal oxide semiconductor) tube Q4 in the primary anti-surge circuit is connected with the transformer, and the source of the MOS tube Q4 is grounded; the emitter of the triode Q1 is connected with the emitter of the triode Q2, the base of the triode Q1 is connected with the base of the triode Q2, the collector of the triode Q1 is connected with the drain of the MOS tube Q3 in the gradual starting circuit, and the collector of the triode Q2 is grounded; one end of the resistor R5 is connected with the base electrode of the triode Q1, the other end of the resistor R5 is connected with the gate drive, wherein one end of the resistor R5, the base electrode of the triode Q1 and the base electrode of the triode Q2 are connected together; one end of the resistor R3 is connected with an emitter of the triode Q1 and an emitter of the triode Q2, and the other end of the resistor R3 is connected with a grid electrode of the MOS transistor Q4; one end of the resistor R4 is connected with the grid of the MOS transistor Q4, and the other end of the resistor R4 is grounded.
Furthermore, an electrolytic capacitor C1, a resistor R1 and a resistor R2 in the gradual starting circuit form an RC delay circuit, wherein one end of the resistor R1 is connected with the anode of the electrolytic capacitor C1, the other end of the resistor R1 is connected with the anode of a power supply, one end of the resistor R2 is connected with the anode of the electrolytic capacitor, the other end of the resistor R2 is grounded, the anode of the electrolytic capacitor C1 is connected with the cathode of a voltage regulator tube D1, and the cathode of the electrolytic capacitor C1 is connected with the anode of a voltage regulator tube D1.
Further, the gate of the MOS transistor Q3 in the gradual starting circuit is connected with the anode of the electrolytic capacitor C1, the source of the MOS transistor Q3 is connected with the anode of the power supply, and the gradual starting circuit controls the primary anti-surge circuit and the LLC secondary anti-surge circuit, so that the switching power supply enters the anti-surge mode.
Furthermore, a voltage comparator in the anti-surge mode termination circuit is a voltage comparator LM339, a non-inverting input end of the voltage comparator LM339 is connected with one end of a resistor R8, an inverting input end of the voltage comparator LM339 is connected with a reference voltage V1, an output end of the voltage comparator LM339 is connected with a grid electrode of a primary anti-surge circuit MOS tube Q2, and a power supply end of the voltage comparator LM339 is connected with a +12V power supply.
Furthermore, one end of a resistor R8 in the anti-surge mode termination circuit is connected with an output bus voltage of the rectifying and filtering circuit, the other end of the resistor R8 is connected with a cathode of a voltage regulator tube D2, and the other end of the voltage regulator tube D2 is grounded; one end of the resistor R7 is connected with the output end of the voltage comparator LM339, and the other end of the resistor R7 is connected with the power supply end of the LM 339; one end of the resistor R6 is connected with one end of the resistor R8, the other end of the resistor R6 is grounded, and one end of the resistor R8, one end of the resistor R6, the non-inverting input end of the voltage comparator LM339 and the cathode of the voltage regulator tube D2 are connected together.
Furthermore, one end of a transformer excitation inductor Lm in the LLC secondary anti-surge circuit is connected to the left end of a resonant inductor Lr, the other end of the transformer excitation inductor Lm is connected to the cathode of a diode D6 in the rectifying and filtering circuit, and the right end of the resonant inductor Lr is connected to the left end of a thermistor NTC; the left end of the thermistor NTC is connected with one contact at the left end of the relay, and the right end of the thermistor NTC is connected with one contact at the right end of the relay; one end of the resonance capacitor Cr is connected with one contact at the right end of the relay, and the other end of the resonance capacitor Cr is connected with the anode of a diode D3 in the rectifying and filtering circuit; the right end of the resonant inductor Lr, the left end of the thermistor NTC and one contact of the left end of the relay are connected together, and one end of the resonant capacitor Cr, the right end of the thermistor NTC and one contact of the right end of the relay are connected together.
Further, a coil J2 end of the relay in the LLC secondary anti-surge circuit is connected with a coil J1 end of the primary anti-surge circuit, and the other end of the coil of the relay is grounded.
Further, the anode of an electrolytic capacitor C0 in the rectifying and filtering circuit is connected with the anode of the output bus voltage V0, and the cathode of an electrolytic capacitor C0 is connected with the cathode of the output bus voltage V0; one end of the resistor R0 is connected with the anode of the output bus voltage V0, and the other end of the resistor R0 is connected with the cathode of the output bus voltage V0.
Further, the delay time of the RC delay circuit in the gradual starting circuit is shown, where R is a resistance of a resistor R1, a resistance of a resistor R1 is preferably 10k Ω, C is a capacitance of an electrolytic capacitor C1, a value of a capacitor C1 is preferably 1000 μ F, C is represented by F, E is a voltage between the series resistor R2 and the electrolytic capacitor C1, and V is a voltage to be reached by the capacitor C1.
Further, the RC delay circuit controls the time required for the MOS transistor Q3 in the gradual starting circuit to be turned on, i.e. the time for suppressing the start surge current, wherein the values of the resistor R1 and the capacitor C1 need to be adjusted according to the start delay time required by the switching power supply.
Furthermore, the anti-surge mode termination circuit compares the voltage value of the output bus with the reference voltage through sampling, and terminates the anti-surge mode in time when the voltage of the output bus of the output filter circuit reaches a set value.
Compared with the prior art, the utility model discloses a technological effect specifically embodies:
(1) the utility model discloses at the power start-up instant, the circuit enters the current-limiting mode promptly, through the gradual acceleration start of gradually starting circuit to main circuit power tube to realize surge current elementary inhibition effect, reduced the impact of surge current to power supply device;
(2) the LLC secondary anti-surge circuit in the utility model also works in a current-limiting mode to prevent the generation of surge current, when the output bus voltage reaches a set value, the two-stage anti-surge mode is immediately turned off, the current stress and the power loss of a main power tube are reduced, the equipment normally works, and the two-stage anti-surge current circuit can effectively and reliably restrain the surge current and improve the reliability of the equipment;
(3) the utility model can stop the anti-surge mode in time when the equipment works normally, and the normal use of the power supply can not be influenced;
(4) the utility model has the characteristics of low power dissipation, circuit structure are simple, the reliability is high, and use the scene to combine together with power main circuit power tube, consequently can be applicable to among the multiple power topological structure.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention;
fig. 2 is a schematic flow diagram of a primary anti-surge circuit of the present invention;
fig. 3 is a schematic flow chart of the LLC secondary anti-surge circuit in the present invention;
fig. 4 is a schematic flow chart of the surge protection mode termination circuit of the present invention;
the reference numbers are as follows: 1. a primary anti-surge circuit; 11. gradually starting up the circuit; 2. an anti-surge mode termination circuit; 3, LLC secondary surge protection circuit; 4. and a rectification filter circuit.
Detailed Description
In order to make the objects and technical solutions of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the following embodiments.
Examples
An inrush current suppression circuit according to fig. 1 to 4 includes a primary anti-surge circuit 1, an anti-surge mode termination circuit 2, a transformer, an LLC secondary anti-surge circuit 3, a rectifier filter circuit 4, and a resistor R0; the primary anti-surge circuit 1 comprises a gradual starting circuit 11, a resistor R5, a resistor R4, a resistor R3, a triode Q1, a triode Q2 and a MOS transistor Q4; the gradual starting circuit 11 comprises an electrolytic capacitor C1, a voltage regulator tube D1, a resistor R1, a resistor R2 and a MOS tube Q3; the surge-proof mode termination circuit 2 comprises a resistor R6, a resistor R7, a resistor R8, a voltage comparator, a voltage regulator tube D2 and a reference voltage V1; the LLC secondary anti-surge circuit 3 comprises a transformer excitation inductor Lm, a resonance inductor Lr, a resonance capacitor Cr, an NTC thermistor and a relay; the rectifying and filtering circuit 4 comprises a diode D3, a diode D4, a diode D5, a diode D6 and an electrolytic capacitor C0; the LLC secondary anti-surge circuit 3 is connected with the rectification filter circuit 4; the anti-surge mode termination circuit 2 is connected with an output bus voltage of the rectifying and filtering circuit 4.
The primary anti-surge circuit 1 further comprises a power supply, the drain electrode of an MOS tube Q4 in the primary anti-surge circuit 1 is connected with the transformer, and the source electrode of an MOS tube Q4 is grounded; the emitter of the triode Q1 is connected with the emitter of the triode Q2, the base of the triode Q1 is connected with the base of the triode Q2, the collector of the triode Q1 is connected with the drain of the MOS tube Q3 in the gradual starting circuit 11, and the collector of the triode Q2 is grounded; one end of the resistor R5 is connected with the base electrode of the triode Q1, the other end of the resistor R5 is connected with the gate drive, wherein one end of the resistor R5, the base electrode of the triode Q1 and the base electrode of the triode Q2 are connected together; one end of the resistor R3 is connected with an emitter of the triode Q1 and an emitter of the triode Q2, and the other end of the resistor R3 is connected with a grid electrode of the MOS transistor Q4; one end of the resistor R4 is connected with the grid of the MOS transistor Q4, and the other end of the resistor R4 is grounded.
An electrolytic capacitor C1, a resistor R1 and a resistor R2 in the gradual starting circuit 11 form an RC delay circuit, wherein one end of the resistor R1 is connected with the anode of the electrolytic capacitor C1, the other end of the resistor R1 is connected with the anode of a power supply, one end of the resistor R2 is connected with the anode of the electrolytic capacitor, the other end of the resistor R2 is grounded, the anode of the electrolytic capacitor C1 is connected with the cathode of a voltage regulator tube D1, and the cathode of the electrolytic capacitor C1 is connected with the anode of the voltage regulator tube D1. The grid of the MOS tube Q3 in the gradual starting circuit 11 is connected with the anode of the electrolytic capacitor C1, the source of the MOS tube Q3 is connected with the anode of the power supply, and the gradual starting circuit 11 controls the primary anti-surge circuit 1 and the LLC secondary anti-surge circuit 3, so that the switching power supply enters an anti-surge mode.
The voltage comparator in the surge-proof mode termination circuit 2 is a voltage comparator LM339, the non-inverting input end of the voltage comparator LM339 is connected with one end of a resistor R8, the inverting input end of the voltage comparator LM339 is connected with a reference voltage V1, the output end of the voltage comparator LM339 is connected with the grid of a MOS tube Q2 of the primary surge-proof circuit 1, and the power supply end of the voltage comparator LM339 is connected with a +12V power supply. One end of a resistor R8 in the surge-proof mode termination circuit 2 is connected with an output bus voltage of the rectifying and filtering circuit 4, the other end of the resistor R8 is connected with a cathode of a voltage regulator tube D2, and the other end of the voltage regulator tube D2 is grounded; one end of the resistor R7 is connected with the output end of the voltage comparator LM339, and the other end of the resistor R7 is connected with the power supply end of the LM 339; one end of the resistor R6 is connected with one end of the resistor R8, the other end of the resistor R6 is grounded, and one end of the resistor R8, one end of the resistor R6, the non-inverting input end of the voltage comparator LM339 and the cathode of the voltage regulator tube D2 are connected together.
One end of a transformer excitation inductor Lm in the LLC secondary anti-surge circuit 3 is connected with the left end of a resonance inductor Lr, the other end of the transformer excitation inductor Lm is connected with the cathode of a diode D6 in the rectification filter circuit 4, and the right end of the resonance inductor Lr is connected with the left end of a thermistor NTC; the left end of the thermistor NTC is connected with one contact at the left end of the relay, and the right end of the thermistor NTC is connected with one contact at the right end of the relay; one end of the resonance capacitor Cr is connected with one contact at the right end of the relay, and the other end of the resonance capacitor Cr is connected with the anode of a diode D3 in the rectifying and filtering circuit 4; the right end of the resonant inductor Lr, the left end of the thermistor NTC and one contact of the left end of the relay are connected together, and one end of the resonant capacitor Cr, the right end of the thermistor NTC and one contact of the right end of the relay are connected together. And the coil J2 end of the relay in the LLC secondary anti-surge circuit 3 is connected with the coil J1 end of the primary anti-surge circuit 1, and the other end of the coil of the relay is grounded.
The anode of an electrolytic capacitor C0 in the rectifying and filtering circuit 4 is connected with the anode of an output bus voltage V0, and the cathode of an electrolytic capacitor C0 is connected with the cathode of an output bus voltage V0; one end of the resistor R0 is connected with the anode of the output bus voltage V0, and the other end of the resistor R0 is connected with the cathode of the output bus voltage V0.
The delay time of the RC delay circuit in the gradual starting circuit 11 is shown, where R is a resistance of a resistor R1, a resistance of a resistor R1 is preferably 10k Ω, C is a capacitance of an electrolytic capacitor C1, a value of a capacitor C1 is preferably 1000 μ F, C is represented by F, E is a voltage between the series resistor R2 and the electrolytic capacitor C1, and V is a voltage to be reached by the capacitor C1. The RC delay circuit controls the time required for conducting the MOS transistor Q3 in the gradual starting circuit 11, i.e. the time for suppressing the start surge current, wherein the values of the resistor R1 and the capacitor C1 need to be adjusted according to the start delay time required by the switching power supply. The anti-surge mode termination circuit 2 compares the voltage value of the output bus with the reference voltage through sampling, and terminates the anti-surge mode in time when the voltage of the output bus of the output filter circuit reaches a set value.
According to the general working principle shown in fig. 2-4, the gradual starting circuit 11 controls the primary anti-surge circuit 1 and the LLC secondary anti-surge circuit 3 simultaneously to make the switching power supply enter the starting anti-surge mode, so as to prevent the generation of surge current. After the power supply is started, the anti-surge mode is ended through the anti-surge mode termination circuit 2, and the switching power supply enters a normal working mode.
The initial voltage of the electrolytic capacitor C1 of the gradual start circuit 11 is 0V, the resistor R1 is short-circuited by C1, and at this time, the MOS transistor Q3 is in an off state, and cannot supply current to the emitter follower formed by the transistors Q1 and Q2, and at this time, the emitter follower cannot perform the function of "current spreading". The driving PWM drives the Q4 through R5-Q1-R3, and since the emitter follower does not carry out current expansion at the moment, the rising edge time is long, and the Q4 works in a saturation region with large internal resistance. As the power-up time increases, the capacitor C1 charges, the gate voltage of Q3 gradually rises to the threshold voltage, and thus Q3 gradually turns on. The input positive stage supplies small and large currents to the transistors Q1 and Q2 which form the emitter follower through Q3, so that the driving current of the PWM driving pair Q4 is gradually increased, and Q4 is finally and completely conducted. In the process, the MOS transistor Q4 works in a saturation region before the MOS transistor Q3 is turned off, the MOS transistor Q4 gradually enters a non-saturation region (is turned on completely) along with the gradual increase of the driving current, so that the gradual start process is ended, the circuit normally works, the internal resistance of the MOS transistor Q4 has a change process from large to small, and the process time is as follows: wherein R is the resistance of the resistor R1, C is the capacitance of the electrolytic capacitor C1, and the unit is F; e is the initial voltage of the electrolytic capacitor C1, and V is the voltage of the electrolytic capacitor C1 during normal operation.
The secondary surge current is because the initial impedance of the capacitor in the resonant cavity is 0, and the equivalent impedance of the resonant cavity is smaller than that of the resonant cavity in normal operation, so that the starting moment is larger surge current. In contrast, an NTC thermistor is connected in series with the resonant cavity to increase the initial equivalent impedance of the resonant cavity and play a role in limiting current. Along with the working time, the resonant capacitor is gradually charged to normal voltage, and meanwhile, the NTC thermistor gradually rises in temperature and gradually drops in resistance. Thereby avoiding surge current caused by instant short circuit of the capacitor at the moment of starting up.
The working principle of the anti-surge mode termination circuit 2 is as follows: the primary anti-surge circuit 1 and the LLC secondary anti-surge circuit 3 both increase the loss of the switching power supply during normal operation, and the device is easily damaged after long-time operation, so that the anti-surge mode needs to be withdrawn after the switching power supply is started. The resistor R5 and the resistor R6 acquire output bus voltage through voltage division, the output bus voltage is compared with the reference voltage V1 of the negative input end of the LM339, when the acquired voltage is larger than the reference voltage V1, the LM339 outputs high level, and the MOS transistor Q3 is directly turned on. Due to the conduction of the MOS tube Q3, an emitter follower formed by the triodes Q1 and Q2 in the primary anti-surge circuit 1 starts to perform a current expansion function, the MOS tube Q4 jumps to a complete conduction area from a linear area, and the primary anti-surge circuit 1 exits an anti-surge mode; meanwhile, a relay coil in the LLC secondary anti-surge circuit 3 reaches attracting current, the relay attracts the bypass NTC thermistor, and the LLC secondary anti-surge circuit 3 exits the anti-surge mode.
The above description is only for the embodiments of the present invention, and the description is specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several changes and modifications can be made, which all fall within the scope of the present invention.
Claims (9)
1. The surge current suppression circuit is characterized by comprising a primary anti-surge circuit, an anti-surge mode termination circuit, a transformer, an LLC secondary anti-surge circuit, a rectification filter circuit and a resistor R0; the primary anti-surge circuit comprises a gradual starting circuit, a resistor R5, a resistor R4, a resistor R3, a triode Q1, a triode Q2 and a MOS transistor Q4; the gradual starting circuit comprises an electrolytic capacitor C1, a voltage regulator tube D1, a resistor R1, a resistor R2 and an MOS tube Q3; the surge-proof mode termination circuit comprises a resistor R6, a resistor R7, a resistor R8, a voltage comparator, a voltage regulator tube D2 and a reference voltage V1; the LLC secondary anti-surge circuit comprises a transformer excitation inductor Lm, a resonance inductor Lr, a resonance capacitor Cr, an NTC thermistor and a relay; the rectifying and filtering circuit comprises a diode D3, a diode D4, a diode D5, a diode D6 and an electrolytic capacitor C0; the LLC secondary anti-surge circuit is connected with the rectification filter circuit; the anti-surge mode termination circuit is connected with an output bus voltage of the rectifying and filtering circuit.
2. The surge current suppression circuit according to claim 1, wherein the primary anti-surge circuit further comprises a power supply, and a drain of a MOS transistor Q4 in the primary anti-surge circuit is connected to the transformer, and a source of a MOS transistor Q4 is grounded; the emitter of the triode Q1 is connected with the emitter of the triode Q2, the base of the triode Q1 is connected with the base of the triode Q2, the collector of the triode Q1 is connected with the drain of the MOS tube Q3 in the gradual starting circuit, and the collector of the triode Q2 is grounded; one end of the resistor R5 is connected with the base electrode of the triode Q1, the other end of the resistor R5 is connected with the gate drive, wherein one end of the resistor R5, the base electrode of the triode Q1 and the base electrode of the triode Q2 are connected together; one end of the resistor R3 is connected with an emitter of the triode Q1 and an emitter of the triode Q2, and the other end of the resistor R3 is connected with a grid electrode of the MOS transistor Q4; one end of the resistor R4 is connected with the grid of the MOS transistor Q4, and the other end of the resistor R4 is grounded.
3. The surge current suppression circuit according to claim 1, wherein an electrolytic capacitor C1, a resistor R1 and a resistor R2 in the gradual starting circuit form an RC delay circuit, wherein one end of the resistor R1 is connected to the anode of the electrolytic capacitor C1, the other end of the resistor R1 is connected to the anode of a power supply, one end of the resistor R2 is connected to the anode of the electrolytic capacitor, the other end of the resistor R2 is grounded, the anode of the electrolytic capacitor C1 is connected to the cathode of a voltage regulator D1, and the cathode of the electrolytic capacitor C1 is connected to the anode of the voltage regulator D1.
4. The surge current suppression circuit according to claim 2, wherein the gate of the MOS transistor Q3 in the gradual start circuit is connected to the positive electrode of the electrolytic capacitor C1, the source of the MOS transistor Q3 is connected to the positive electrode of the power supply, and the gradual start circuit controls the primary anti-surge circuit and the LLC secondary anti-surge circuit, so that the switching power supply enters the anti-surge mode.
5. The surge current suppression circuit according to claim 1, wherein the voltage comparator in the surge-prevention mode termination circuit is a voltage comparator LM339, a non-inverting input terminal of the voltage comparator LM339 is connected to one end of a resistor R8, an inverting input terminal of the voltage comparator LM339 is connected to a reference voltage V1, an output terminal of the voltage comparator LM339 is connected to a gate of a primary surge-prevention circuit MOS transistor Q2, and a power supply terminal of the voltage comparator LM339 is connected to a +12V power supply.
6. The surge current suppression circuit according to claim 1, wherein one end of a resistor R8 in the surge mode termination circuit is connected with an output bus voltage of the rectifying and filtering circuit, the other end of a resistor R8 is connected with a cathode of a voltage regulator tube D2, and the other end of the voltage regulator tube D2 is grounded; one end of the resistor R7 is connected with the output end of the voltage comparator LM339, and the other end of the resistor R7 is connected with the power supply end of the LM 339; one end of the resistor R6 is connected with one end of the resistor R8, the other end of the resistor R6 is grounded, and one end of the resistor R8, one end of the resistor R6, the non-inverting input end of the voltage comparator LM339 and the cathode of the voltage regulator tube D2 are connected together.
7. The inrush current suppression circuit according to claim 1, wherein one end of a transformer magnetizing inductor Lm in the LLC secondary anti-inrush circuit is connected to the left end of a resonant inductor Lr, the other end of the transformer magnetizing inductor Lm is connected to the cathode of a diode D6 in the rectifying and filtering circuit, and the right end of the resonant inductor Lr is connected to the left end of a thermistor NTC; the left end of the thermistor NTC is connected with one contact at the left end of the relay, and the right end of the thermistor NTC is connected with one contact at the right end of the relay; one end of the resonance capacitor Cr is connected with one contact at the right end of the relay, and the other end of the resonance capacitor Cr is connected with the anode of a diode D3 in the rectifying and filtering circuit; the right end of the resonant inductor Lr, the left end of the thermistor NTC and one contact of the left end of the relay are connected together, and one end of the resonant capacitor Cr, the right end of the thermistor NTC and one contact of the right end of the relay are connected together.
8. The inrush current suppression circuit of claim 1, wherein the terminal of the coil J2 of the relay in the LLC secondary anti-inrush circuit is connected to the terminal J1 of the primary anti-inrush circuit, and the other terminal of the coil of the relay is grounded.
9. The surge current suppression circuit according to claim 1, wherein the positive pole of the electrolytic capacitor C0 in the rectifying and smoothing circuit is connected to the positive pole of the output bus voltage V0, and the negative pole of the electrolytic capacitor C0 is connected to the negative pole of the output bus voltage V0; one end of the resistor R0 is connected with the anode of the output bus voltage V0, and the other end of the resistor R0 is connected with the cathode of the output bus voltage V0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120323430.2U CN214256123U (en) | 2021-02-04 | 2021-02-04 | Surge current suppression circuit |
Applications Claiming Priority (1)
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| CN202120323430.2U CN214256123U (en) | 2021-02-04 | 2021-02-04 | Surge current suppression circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114825895A (en) * | 2022-06-27 | 2022-07-29 | 合肥博雷电气有限公司 | Input anti-surge slow starting circuit with overcurrent protection function |
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- 2021-02-04 CN CN202120323430.2U patent/CN214256123U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114825895A (en) * | 2022-06-27 | 2022-07-29 | 合肥博雷电气有限公司 | Input anti-surge slow starting circuit with overcurrent protection function |
| CN114825895B (en) * | 2022-06-27 | 2022-09-20 | 合肥博雷电气有限公司 | Input anti-surge slow starting circuit with overcurrent protection function |
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