WO2020114247A1

WO2020114247A1 - Control circuit for contactor

Info

Publication number: WO2020114247A1
Application number: PCT/CN2019/119576
Authority: WO
Inventors: 苏俊熙; 符威
Original assignee: 广州金升阳科技有限公司
Priority date: 2018-12-05
Filing date: 2019-11-20
Publication date: 2020-06-11
Also published as: CN109585223B; CN109585223A

Abstract

Disclosed in the present invention is a control circuit for a contactor, comprising a voltage detection circuit and a duty cycle control circuit. The voltage detection circuit first reduces a bus voltage to an appropriate range by means of a voltage dividing resistor, and then filters out an alternating current component by means of a low-pass filter. The remaining direct current component is used as an output of the voltage detection circuit, and the output voltage is recorded as VS. The duty cycle control circuit outputs a duty cycle D by means of detecting the output voltage VS, VS×D is recorded as KD, and KD is a constant that is set at an inner part of the duty cycle control circuit. In the present invention, setting KD as a constant may enable the contactor coil current to not change in a wide input range, so that when a PF value of a contactor power saver is increased, a bus capacitor and a sampling resistor therein may be removed, and the average value of the contactor coil current does not change within a wide voltage alternating current/direct current input voltage range.

Description

Contactor control circuit

Technical field

The invention relates to the field of AC contactors, in particular to a contactor control circuit with power factor correction function.

Background technique

The traditional contactor operating system is composed of coil, static iron core, armature and reaction spring. When the contactor coil is energized, there is suction between the static iron core and the armature. When the suction force is greater than the spring reaction force, the armature is attracted to the static iron core until it contacts the static iron core. At this time, the main contact is closed. This process is called suction.合process. The coil is continuously energized, the armature and the static iron core are kept in contact, and the main contact is kept closed, which is called the holding process. When the current in the coil is reduced or interrupted, the suction force of the static iron core on the armature decreases. When the suction force is less than the spring reaction force, the armature returns to the open position and the main contacts are separated. This process is called the release process. From an electrical point of view, the contactor coil can be equivalent to an inductance with a certain internal resistance.

The contactor is used to frequently connect and disconnect AC and DC circuits, and can control low-voltage electrical appliances from a long distance. The main control object is the electric motor, which can also be used to control electric loads such as electric heaters, welding machines and lighting lamps. At present, the use of contactors in the country is huge. When the medium and large-capacity contactors are in the holding state, the active power consumed by each unit is about 60W on average, and the power factor is only about 0.3. Reducing the energy consumption of contactors makes a significant contribution to energy saving and emission reduction.

At present, the existing contactor power saver adopts AC to DC, high current pull-in, and small current hold mode, which greatly reduces the electromagnetic coil iron loss, copper loss and short-circuit ring loss, which can reduce active power consumption by more than 90% . The chip controls the conduction duty cycle of the MOS tube to realize the control of large current pull-in and small current hold-in. However, these technologies have certain defects, which only solve the problem of active power consumption, but they are powerless to improve the power factor. Some power-saving technologies will also reduce the power factor. For example, in the patent with the application number 200510029373.2, the electromagnetic coil is powered by a pulse to make the electromagnetic coil work with a constant small current; working in this way will not only generate a lot of harmonics, but the effective value of the input current does not follow the input voltage , Resulting in a very low power factor, the actual PF value is less than 0.3 when making prototypes according to this technology. The patented technologies with application numbers 201210196762.4 and 201010040019.9 excite the electromagnetic coil near the zero-crossing of the input AC voltage, so that the input current and the output voltage are in a state similar to the opposite phase. The prototype is made according to this technology, and the power factor is less than 0.1.

In order to promote the use of contactors with power savers, manufacturers are hoping that the use and appearance of traditional contactors will not change much. Then the power saver must be placed in the contactor shell, which has high requirements on the volume of the power saver. According to the above-mentioned published patents, the main power device of the contactor power saver includes a rectifier bridge, a bus capacitor, a MOS tube, a freewheeling diode, and a current sampling resistor. The above devices are not all necessary, and the power control device can be further reduced by improving the control method, while the original performance is not changed or improved. Further increase the market competitiveness of power savers.

Since the traditional contactor does not have a control circuit, the coil current will follow the input voltage, so the input voltage range of the traditional contactor is very narrow. The typical input range is 80%*Um～110%Um. And now manufacturers have put forward new requirements for contactor power savers, and proposed a wide voltage AC and DC universal contactor. For example, the requirements of four wide-voltage AC/DC universal contactors such as 24V to 48V, 48V to 120V, 100V to 250V, and 250V to 500V are proposed.

Summary of the invention

The technical problem solved by the present invention is to provide a contactor control circuit in view of the above-mentioned defects and new market requirements in the prior art. By improving the control method, while increasing the PF value of the contactor power saver, Remove the bus capacitance and sampling resistance in the contactor power saver, and the average value of the contactor coil current is constant within a wide voltage AC and DC input voltage range.

To solve the above technical problems, the technical solutions provided by the present invention are as follows:

A contactor control circuit, including a voltage detection circuit and a duty cycle control circuit; the voltage detection circuit first reduces the bus voltage to a suitable range through a voltage-dividing resistor, the voltage-dividing ratio is recorded as K _V , and then passes through a low-pass filter The AC component is filtered, and the remaining DC component is used as the output of the voltage detection circuit. The output voltage is recorded as V _S ; the duty cycle control circuit detects the output voltage V _S , and the output duty ratio D, V _S ×D is recorded as K _D , K _D is a constant set in the duty control circuit.

As a specific embodiment of the voltage detection circuit, it includes: a resistor R1, a resistor R2 and a capacitor C1. The resistor R1 and the resistor R2 are connected in series to be connected in parallel with both ends of the rectified bus voltage. One end of the capacitor C1 and the resistor R1 are The connection point of the resistor R2 is connected, and serves as the output terminal of the voltage detection circuit, outputs the output voltage V _S , and the other end of the capacitor C1 is grounded.

As a first specific embodiment of the duty cycle control circuit, it includes: an operational amplifier U1, a MOS transistor Q2, a resistor R _D1 , a switch K1, a switch K2, a switch K3, a capacitor CD ₁ , a capacitor _{CD 2} , and an inverter U2 , Comparator U3, RS flip-flop U4, clock generator, pull-in holding switching circuit, constant current source M1 and constant current source M2; pull-in holding switching circuit is used to control the switch K1 and switch K2 in the pull-in phase Disconnected, in the holding phase, the control switch K2 is turned on and K1 is disconnected; the positive input terminal of the operational amplifier U1 is used to input the output voltage V _S , the negative input terminal of the operational amplifier U1 and one end of the resistor R _D1 and the MOS tube The drain of Q2 is connected, and the output of the operational amplifier U1 is connected to the gate of the MOS transistor Q2; the other end of the resistor R _D1 is grounded; the input of the constant current source M1 is used to input the supply voltage V _DD , the output of the constant current source M1 The terminal is connected to the drain of the MOS transistor Q2; the input terminal of the constant current source M2 is used to input the supply voltage V _DD , the first switch terminal of the switch K1, the switch K2, and the switch K3 is connected to the output terminal of the constant current source M2 and the comparator U3 Is connected to the positive input terminal, the second switch terminal of switch K1 is grounded through capacitor _CD1 , the second switch terminal of switch K2 is grounded through capacitor _CD2 , and the second switch terminal of switch K3 is grounded; the control terminal of switch K1 is The first output terminal of the holding switch circuit is connected, the control terminal of the switch K2 is connected to the second output terminal of the pull-in switch circuit; the control terminal of the switch K3 is connected to the output of the inverter U2; the negative input terminal of the comparator U3 Input the comparison threshold voltage V _TH , the output of the comparator U3 is connected to the R input of the RS flip-flop U4, the S input of the RS flip-flop U4 is connected to the clock generator, and the output of the RS flip-flop U4 is connected to the inverter U2 At the same time, it is also the output terminal of the duty ratio control circuit, and outputs the signal for controlling the opening and closing of the main power switch tube in the contactor.

As a second specific embodiment of the duty ratio control circuit, it includes: an operational amplifier U1, a MOS transistor Q2, a resistor R _D1 , a resistor R _D2 , a switch K1, a switch K2, a switch K3, a capacitor C _D1 , and an inverter U2 , Comparator U3, RS flip-flop U4, clock generator, pull-in holding switching circuit, constant current source M1 and constant current source M2; pull-in holding switching circuit is used to control switch K1 and switch K2 in the pull-in phase Disconnect, in the holding phase, control switch K2 is turned on and K1 is disconnected; the positive input terminal of op amp U1 is used to input the output voltage V _S , and the negative input terminal of op amp U1 is connected to the first and second switches of switch K1 and switch K2, respectively. A switch terminal is connected to the drain of the MOS transistor Q2, the output terminal of the operational amplifier U1 is connected to the gate of the MOS transistor Q2; the second switch terminal of the switch K1 is grounded through the resistor R _D1 , and the second switch terminal of the switch K2 is connected through the resistor R _{D2 is} grounded, the control end of switch K1 is connected to the first output end of the pull-in holding switching circuit, the control end of switch K2 is connected to the second output end of the pull-in holding switching circuit; the input end of the constant current source M1 is used to Input power supply voltage V _DD , the output end of the constant current source M1 is connected to the drain of the MOS transistor Q2; the input end of the constant current source M2 is used to input the power supply voltage V _DD , the output end of the constant current source M2 and the positive of the comparator U3 One end of an input terminal, a first switch terminal of the switch K3, and the capacitor C _D1 is connected to the other end connected to the output capacitor C _D1, the switch of the second switch terminal is grounded K3, K3 switching control terminal of the inverter U2; Comparative The negative input terminal of the comparator U3 inputs the comparison threshold voltage V _TH , the output terminal of the comparator U3 is connected to the R input terminal of the RS flip-flop U4, the S input terminal of the RS flip-flop U4 is connected to the clock generator, and the output of the RS flip-flop U4 The terminal is connected to the inverter U2 and is also the output terminal of the duty cycle control circuit, and outputs a signal for controlling the opening and closing of the main power switch tube in the contactor.

Through the above description of the basic principles of this solution, the solution of the present invention can obtain the following beneficial effects:

1. The duty cycle does not follow the bus voltage fluctuation, and the bus capacitance can be removed.

2. The input current will follow the input voltage and the PF value will be high.

3. The coil current is indirectly controlled by sampling the input voltage, and the current sampling resistor can be removed.

4. The average value of the coil current is constant under a wide input voltage, and the input AC and DC are universal.

BRIEF DESCRIPTION

Figure 1 is the main power circuit and equivalent circuit of the contactor power saver;

2 is a circuit schematic diagram of the first embodiment;

Figure 3 key node waveforms of the first embodiment;

4 is a circuit schematic diagram of the second embodiment.

detailed description

The ideas of the invention of this application are as follows:

The main power circuit of the existing contactor power saver is shown in the left diagram in FIG. 1 and is mainly composed of a contactor coil L1, a diode D1 and a MOS tube Q1. The peak value of the bus voltage is U _M , and the duty cycle of the drive signal is D. If the duty cycle is constant, if only the current parameter of the contactor coil L1 is concerned, then the left diagram in Figure 1 can be equivalent to the right diagram, where the bus voltage peak value in the right diagram is U _M *D.

If the bus capacitance is removed, the rectified voltage is a bun wave. After the Fourier decomposition of the bun wave, the components above 100 Hz are already very small, so the formula of the bun wave can be approximated as:

U _IN (t) = U _M ·| sinω ₀ t|≈ U _M · (0.6365+0.424·cos2ω ₀ t)

Among them, U _M is the peak value of the input voltage, ω ₀ is the angular frequency corresponding to the 50 Hz power frequency.

Let the internal resistance of the contactor coil L1 be R _COIL and the coil inductance L _COIL . Using this bus voltage U _IN (t) to excite the contactor coil L1, then the DC and AC components of the contactor coil L1 can be obtained.

For 0HZ (DC component), the coil impedance is R _COIL ; for 100 Hz, the coil impedance is:

Coil DC component:

Coil AC component:

In the same way, it is also easy to obtain. When the input is DC voltage U _DC , the current of the coil is:

When the input is DC, the coil current:

The voltage detection circuit of the invention is a voltage dividing filter circuit, and the input of the voltage detection circuit is connected to the rectified bus voltage. The voltage detection circuit first reduces the bus voltage to a suitable range through a voltage divider resistor, the voltage division ratio is recorded as K _V , and then the AC component is filtered through a low-pass filter, and the remaining DC component is used as the output of the voltage detection circuit. The voltage is recorded as V _S. The formula of the steamed bun has been analyzed above, so it is easy to obtain. The output voltage of the voltage detection circuit is:

When the input is AC, the output voltage of the detection circuit:

V _{S_AC} = 0.6365·K _V · U _M (4)

When the input is DC, the output voltage of the detection circuit:

V _{S_DC} = K _V · U _DC (5)

The duty ratio control circuit of the present invention outputs the duty ratio D by detecting the output voltage V _{S of the} voltage detection circuit. The relationship between V _S and D is:

V _S ·D=K _D (6)

Where K _D is a constant determined internally in the duty cycle control circuit, it can make the current of the contactor coil L1 unchanged within a wide input range. Substituting formula (4) and formula (6) into formula (1) and formula (2), the AC component and DC component of the coil when the input is AC can be obtained. Substituting equation (5) and equation (6) into equation (3), the coil current of the coil when the input is DC can be obtained.

When the input is AC, the DC component of the coil:

When the input is AC, the AC component of the coil:

When the input is DC, the coil current:

Through the above current formula, it can be seen that after the control scheme of the present invention, the coil current is independent of the input voltage, which means that the coil current is constant in a wide input voltage range. The average current of the coil is the same for AC input and DC input.

Because the output of the voltage detection circuit is approximately a DC voltage signal, the output duty cycle of the duty cycle control circuit is also constant throughout the power frequency period. This control is somewhat similar to the PFC control principle. According to the formula △I=V _IN ·T _ON /L _COIL , T _ON does not follow the bus voltage fluctuation, then the input current follows the input voltage, then the PF value of this control method will be relatively high.

In order to better understand the improvements made by the present invention relative to the prior art, specific embodiments of the present invention will be described in detail.

First embodiment

2 is a schematic diagram of a contactor control circuit according to the first embodiment of the present invention, including a voltage detection circuit and a duty control circuit.

The voltage detection circuit includes a resistor R1, a resistor R2, and a capacitor C1. The resistor R1 and the resistor R2 are connected in series and connected in parallel across the rectified bus voltage. One end of the capacitor C1 is connected to the connection point of the resistor R1 and the resistor R2, and serves as the output end of the voltage detection circuit, and the other end of the capacitor C1 is grounded. The function of the voltage detection circuit is to divide and filter, reduce the bus voltage to an appropriate value and extract its DC component.

The duty control circuit of the first embodiment includes an operational amplifier U1, a MOS transistor Q2, a resistor R _D1 , a switch K1, a switch K2, a switch K3, a capacitor CD ₁ , a capacitor _{CD 2} , an inverter U2, a comparator U3, RS Trigger U4, clock generator, pull-in and holding switching circuit, constant current source M1, constant current source M2. The positive input terminal of the operational amplifier U1 is connected to the output of the voltage detection circuit, the negative input terminal of the operational amplifier U1 is connected to one end of the resistor R _D1 and the drain of the MOS transistor Q2, and the output terminal of the operational amplifier U1 is connected to the gate of the MOS transistor Q2 Connected. The other end of the resistor R _D1 is grounded. The input terminal of the constant current source M1 is connected to the voltage V _DD , and the output terminal of the constant current source M1 is connected to the drain of the MOS transistor Q2. The input terminal of the constant current source M2 is connected to the voltage V _DD , the first switch terminal of the switch K1, the switch K2, and the switch K3 is connected to the output terminal of the constant current source M2 and the positive input terminal of the comparator U3, and the second switch of the switch K1 The terminal is grounded through the capacitor _CD1 , the second switch terminal of the switch K2 is grounded through the capacitor _CD2 , and the second switch terminal of the switch K3 is grounded. The control terminal of the switch K1 is connected to the first output terminal of the pull-in holding switching circuit, and the control terminal of the switch K2 is connected to the second output end of the pull-in holding switching circuit. The control terminal of the switch K3 is connected to the output of the inverter U2. The negative input of the comparator U3 is connected to the voltage V _TH , the output of the comparator U3 is connected to the R input of the RS flip-flop U4, the S input of the RS flip-flop U4 is connected to the clock generator, and the output of the RS flip-flop U4 The terminal is connected to the inverter U2 and is also the output terminal of the duty cycle control circuit, outputting the GATE signal.

Voltage V _DD : It is the power supply voltage, and the voltage value is stable.

Voltage V _TH : For comparing threshold voltage, the voltage value is stable.

V _CD voltage: During the pull-in phase, switch K1 is turned on and K2 is off, and the V _CD voltage is the voltage on the capacitor _CD1 ; during the hold phase, the switch K2 is turned on and K1 is turned off, and the V _CD voltage is the voltage on the capacitor _CD2 . The voltage waveform of V _CD is a sawtooth wave, and the slope of the sawtooth wave mainly follows the capacitance value of capacitor _CD1 , the capacitance value of capacitor _CD2 , and the input voltage.

GATE signal: the signal to control the opening and closing of the main power switch tube Q1 in the contactor.

The function of the pull-in and hold-up switching circuit is to control the switch K1 to turn on the switch K2 during the pull-in phase, and to control the switch K2 to turn on and K1 to turn off during the pull-in phase. After the control circuit is powered on, it enters the pull-in phase. After a fixed delay, it enters the hold-in phase and maintains this phase until the next power-off restart. This function is easily realized with semiconductor logic circuits. The other embodiments are the same.

The working principle of this embodiment is explained as follows with reference to FIG. 3. According to the principle of negative feedback of the operational amplifier U1 and the virtual end and virtual break of the input terminal, the negative input terminal voltage of the operational amplifier U1 is equal to the output voltage V _{S of the} voltage detection circuit. The current of the constant current source M1 is equal to:

I _D1 = V _S /R _D1

The constant current source M1 and the constant current source M2 form a mirror current source, and the ratio of the mirror current is K _I , then the output current of the constant current source M2 is:

I _D2 = I _D1 /K _I.

Capacitor C _D1 determines the duty cycle in the pull-in phase, capacitor C _D2 determines the duty cycle in the hold phase, the multiple of the capacitance value of capacitor C _D1 and capacitor C _D2 is the multiple of the pull-in hold current. As shown in FIG. 3, the switch K1 is turned on during the pull-in phase, and the switch K2 is turned off, and the V _CD voltage is the voltage on the capacitor _CD1 ; during the holding phase, the switch K1 is turned off and the switch K2 is turned on, and the V _CD voltage Is the voltage across capacitor _CD2 . The current I _{D2 is} given to the capacitor C _D1 or the capacitor C _D2 . The capacitor voltage rises linearly. When the capacitor voltage rises to the V _TH value, the comparator U3 outputs a high level. At this time, the RS flip-flop U4 outputs a low level, and at the same time K3 The voltage on the closed capacitor _CD1 or capacitor _CD2 is reset to zero. Wait until the next cycle clock generator sends out a high-level signal to control RS flip-flop U4 to output a high level. The on-time of duty cycle GATE is:

Pull-in stage:

Holding stage:

When the bus voltage becomes higher, the charging current I _D2 for capacitor C _D1 or capacitor C _D2 becomes larger, the voltage on the capacitor reaches the voltage value V _TH faster, and the duty ratio becomes smaller; otherwise, when the bus voltage becomes lower, The duty cycle will become larger. The relationship between the bus voltage and the output duty ratio is inversely proportional. In this embodiment, the duty ratios of the pull-in phase and the hold-in phase are set by setting the sizes of the capacitor _CD1 and the capacitor _CD2 .

Second embodiment

The circuit schematic diagram of the second embodiment is shown in FIG. 4. The basic principle of the second embodiment is the same as that of the first embodiment. Except that the second embodiment is to control the charging current I _D2 through the resistor R _D1 and the resistor R _D2, and set the duty cycle pull stage sorption stage. The voltage detection circuit of the second embodiment is the same as the first embodiment. The connection relationship of the duty control circuit of the second embodiment is as follows.

The duty control circuit of the second embodiment includes an operational amplifier U1, a MOS transistor Q2, a resistor R _D1 , a resistor R _D2 , a switch K1, a switch K2, a switch K3, a capacitor C _D1 , an inverter U2, a comparator U3, RS Trigger U4, clock generator, pull-in and holding switching circuit, constant current source M1, constant current source M2. The positive input terminal of the operational amplifier U1 is connected to the output of the voltage detection circuit, the negative input terminal of the operational amplifier U1 is respectively connected to the first switch terminal of the switch K1, the switch K2, and the drain of the MOS transistor Q2, and the output terminal of the operational amplifier U1 is connected to The gate of the MOS transistor Q2 is connected. The second switch end of the switch K1 is grounded through the resistor R _D1 , the second switch end of the switch K2 is grounded through the resistor R _D2 , the control end of the switch K1 is connected to the first output end of the pull-in and hold switching circuit, and the control end of the switch K2 It is connected to the second output terminal of the pull-in and hold-up switching circuit. The input terminal of the constant current source M1 is connected to the voltage V _DD , and the output terminal of the constant current source M1 is connected to the drain of the MOS transistor Q2. Input M2 and the constant current source is connected to voltage V _DD, the output terminal of the constant current source M2 positive input terminal of the comparator, a first switch terminal of the switch K3, U3 is connected to one end of the capacitor C _D1 and the other end of the capacitor C _D1 Ground, the second switch terminal of switch K3 is grounded, and the control terminal of switch K3 is connected to the output of inverter U2. The negative input terminal of the comparator U3 is connected to the voltage V _TH , the output terminal of the comparator U3 is connected to the R input terminal of the RS flip-flop U4, the S input terminal of the RS flip-flop U4 is connected to the clock generator, and the output of the RS flip-flop U4 The terminal is connected to the inverter U2 and is also the output terminal of the duty cycle control circuit, outputting the GATE signal.

Voltage V _TH : For comparing threshold voltage, the voltage value is stable.

V _CD voltage: V _CD voltage is the voltage on the capacitor _CD1 . The voltage waveform of V _CD is a sawtooth wave, and the slope of the sawtooth wave mainly follows the resistance R _D1 resistance, resistance R _D2 resistance, and input voltage.

The key node waveform of the second embodiment is the same as that of the first embodiment, and can also be illustrated by FIG. 3. The V _CD voltage is the voltage across the capacitor _CD1 . In the pull-in phase, the switch K1 is turned on, the switch K2 is turned off, and the current flows through R _D1 ; in the holding phase, the switch K1 is turned off, the switch K2 is turned on, and the current flows through R _D2 . The value of the resistor R _D1 is larger than that of R _D2 , and the current flowing through the resistor R _D1 is smaller than that of the resistor R _D2 . In the pull-in phase, the current charging capacitor C _D1 is small, the voltage of capacitor C _D1 rises slowly, and the duty cycle is large; in the holding phase, the charging current of capacitor C _D1 is large, and the duty cycle is small. When the bus voltage becomes higher, the current charging capacitor C _D1 becomes larger, the voltage on the capacitor reaches the voltage value V _TH faster, and the duty ratio becomes smaller; otherwise, when the bus voltage becomes lower, the duty ratio becomes Big. The relationship between the bus voltage and the output duty ratio is inversely proportional. In this embodiment, by setting the resistance values of the resistors R _D1 and R _D2 , the duty ratios of the pull-in stage and the hold stage are set respectively.

The above are only the preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be regarded as limiting the present invention, and the protection scope of the present invention should be subject to the scope defined by the claims. For those of ordinary skill in the art, without departing from the spirit and scope of the present invention, a number of improvements and retouches can be made, and these improvements and retouches should also be regarded as the scope of protection of the present invention.

Claims

A contactor control circuit, which is characterized by including a voltage detection circuit and a duty cycle control circuit; the voltage detection circuit first reduces the bus voltage to a suitable range through a voltage-dividing resistor, the voltage-dividing ratio is recorded as K V , and then passes the low The pass filter filters out the AC component, and the remaining DC component is used as the output of the voltage detection circuit. The output voltage is recorded as V S ; the duty cycle control circuit detects the output voltage V S to output the duty cycle D, V S ×D Recorded as K D , K D is a constant set in the duty cycle control circuit.
The contactor control circuit according to claim 1, wherein the voltage detection circuit comprises: a resistor R1, a resistor R2 and a capacitor C1, the resistor R1 and the resistor R2 are connected in series to be connected in parallel with both ends of the rectified bus voltage, and the capacitor C1 One end of is connected to the connection point of the resistor R1 and the resistor R2, and serves as the output end of the voltage detection circuit, outputs the output voltage V S , and the other end of the capacitor C1 is grounded.
The contactor control circuit according to claim 1, characterized in that the duty cycle control circuit comprises: an operational amplifier U1, a MOS transistor Q2, a resistor R D1 , a switch K1, a switch K2, a switch K3, a capacitor CD1 , a capacitor CD2 , Inverter U2, comparator U3, RS flip-flop U4, clock generator, pull-in holding switching circuit, constant current source M1 and constant current source M2; pull-in holding switching circuit is used to control the switch in the pull-in phase The K1 conduction switch K2 is off, and the control switch K2 is turned on and K1 is off during the holding phase; the positive input terminal of the operational amplifier U1 is used to input the output voltage V S , and the negative input terminal of the operational amplifier U1 and the resistor R D1 Is connected to the drain of the MOS transistor Q2, the output of the operational amplifier U1 is connected to the gate of the MOS transistor Q2; the other end of the resistor R D1 is grounded; the input of the constant current source M1 is used to input the supply voltage V DD , constant The output terminal of the current source M1 is connected to the drain of the MOS transistor Q2; the input terminal of the constant current source M2 is used to input the power supply voltage V DD , the first switch terminal of the switch K1, the switch K2 and the switch K3 and the output of the constant current source M2 The terminal is connected to the positive input terminal of the comparator U3, the second switch terminal of the switch K1 is grounded through the capacitor CD1 , the second switch terminal of the switch K2 is grounded through the capacitor CD2 , and the second switch terminal of the switch K3 is grounded; the control of the switch K1 The terminal is connected to the first output terminal of the pull-in holding switching circuit, the control terminal of the switch K2 is connected to the second output terminal of the pull-in holding switching circuit; the control terminal of the switch K3 is connected to the output of the inverter U2; the comparator The negative input terminal of U3 inputs the comparison threshold voltage V TH , the output terminal of the comparator U3 is connected to the R input terminal of the RS flip-flop U4, the S input terminal of the RS flip-flop U4 is connected to the clock generator, and the output terminal of the RS flip-flop U4 It is also connected to the inverter U2 and is also the output terminal of the duty cycle control circuit, which outputs the signal to turn on and off the main power switch in the control contactor.
The contactor control circuit according to claim 1, wherein the duty cycle control circuit includes: an operational amplifier U1, a MOS transistor Q2, a resistor R D1 , a resistor R D2 , a switch K1, a switch K2, a switch K3, and a capacitor C D1 , Inverter U2, comparator U3, RS flip-flop U4, clock generator, pull-in holding switching circuit, constant current source M1 and constant current source M2; pull-in holding switching circuit is used to control the switch in the pull-in phase K1 is turned on and switch K2 is turned off. During the holding phase, switch K2 is turned on and K1 is turned off; the positive input terminal of op amp U1 is used to input the output voltage V S , and the negative input terminal of op amp U1 is respectively connected to switch K1 Connected to the first switch terminal of switch K2 and the drain of MOS transistor Q2, the output terminal of op amp U1 is connected to the gate of MOS transistor Q2; the second switch terminal of switch K1 is grounded through resistor R D1 , the second switch K2 The switch terminal is grounded through the resistor R D2 , the control terminal of the switch K1 is connected to the first output terminal of the pull-in holding switching circuit, the control terminal of the switch K2 is connected to the second output terminal of the pull-in holding switching circuit; the constant current source M1 The input terminal is used to input the power supply voltage V DD , the output terminal of the constant current source M1 is connected to the drain of the MOS transistor Q2; the input terminal of the constant current source M2 is used to input the power supply voltage V DD , the output terminal of the constant current source M2 is positive input of comparator U3, the end of the first capacitor C D1 and a switch terminal of switch K3 is connected to other end of the capacitor C D1, the switch of the second switch terminal is grounded K3, K3 switching control terminal of the inverter U2 The output of the comparator is connected; the negative input terminal of the comparator U3 inputs the comparison threshold voltage V TH , the output terminal of the comparator U3 is connected to the R input terminal of the RS flip-flop U4, and the S input terminal of the RS trigger U4 is connected to the clock generator, RS The output terminal of the flip-flop U4 is connected with the inverter U2 and is also the output terminal of the duty ratio control circuit, and outputs a signal for controlling the opening and closing of the main power switch tube in the contactor.