CN112509617A

CN112509617A - Sensitive amplifier circuit

Info

Publication number: CN112509617A
Application number: CN202011199570.XA
Authority: CN
Inventors: 李兆桂; 冯国友
Original assignee: Praran Semiconductor Shanghai Co ltd
Current assignee: Praran Semiconductor Shanghai Co ltd
Priority date: 2020-10-30
Filing date: 2020-10-30
Publication date: 2021-03-16
Anticipated expiration: 2040-10-30

Abstract

The invention discloses a sensitive amplifier circuit, which comprises an amplifying circuit and a biasing circuit, wherein the biasing circuit is used for ensuring that the amplifying circuit amplifies the voltage on the amplifying circuit without distortion, the voltage amplified without distortion is loaded to a drain electrode of a memory CELL, and the voltage loaded to the drain electrode of the memory CELL is constant. The sensitive amplifier circuit can offset the difference of drain voltage of the storage unit caused by different application voltages, and improves the output consistency of the storage unit with different application voltages.

Description

Sensitive amplifier circuit

Technical Field

The invention relates to the technical field of semiconductor circuits, in particular to a sensitive amplifier circuit.

Background

In the existing sensitive amplifier circuit, the voltage VBL actually loaded to the CELL end of the memory CELL is not constant due to the influence of the impedance voltage drop of the switching tube NM2, and particularly, the on-resistance change of the NM2 tube in wide voltage application is different under different working voltages of the inverted VBL, so that the actual CELL current is influenced, and the reading margin is reduced or the reading error is caused.

Disclosure of Invention

The invention aims to provide a sensitive amplifier circuit, which is characterized in that by optimizing the bias voltage of a sensitive amplifier, an NMOS (N-channel metal oxide semiconductor) tube NM6 is partially adopted by a bias circuit to compensate the voltage drop of a control switch NMOS tube NM2 at a CELL end, so that the constant voltage of a drain electrode of the CELL tube is ensured under the condition of wide voltage application.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a sensitive amplifier circuit comprises an amplifying circuit and a biasing circuit, wherein the biasing circuit is used for ensuring that the amplifying circuit amplifies the voltage on the amplifying circuit without distortion, the voltage amplified without distortion is loaded to a drain electrode of a memory CELL CELL, and the voltage loaded to the drain electrode of the memory CELL CELL is constant.

Further, the amplifying circuit comprises a PMOS tube PM1, NMOS tubes NM2, NM 3; the source of PM1 is connected to voltage VDD, the gate of PM1 is connected to voltage VSABIAS, the drain of PM1 is connected to the drain of NM3, the source of NM3 is connected to the drain of NM2, the gate of NM2 is connected to power supply VDD, the source of NM2 is connected to the drain of memory CELL CELL, the gate of memory CELL CELL is connected to voltage VWL, and the source of memory CELL CELL is grounded.

Further, the bias circuit comprises PMOS tubes PM2, PM3, NMOS tubes NM1, NM4, NM5, NM 6; the source of PM2 is connected to voltage VDD, the gates of PM2 and NM6 are connected to bias voltage VBLPBIAS, the drain of PM2 is connected to the source of PM3, the gates of PM3 and NM4 are connected to control terminal ENB, the drains of PM3, NM4, NM5, NM5 and NM1 are connected to the gate of NM3, the sources of NM4 and NM6 are grounded, the sources of NM5 and NM1 are connected to the drain of NM6, and the gate of NM1 is connected to the drain of NM 2.

Further, when the control terminal ENB is at a high level, the PM3 is turned off, the NM3 is turned on, the bias voltage VLIM is pulled to a low level, and the sense amplifier does not operate.

Further, when the control terminal ENB is at a low level, NM4 is turned off, PM3 is turned on, and the bias current of the bias tube PM2 controlled by the input VBLBIAS signal pulls up the VLIM until the on currents of NM1 and NM5 are equal to the current of the bias current tube PM2, where VLIM is the bias voltage of the subsequent amplifier, and the sense amplifier circuit enters a normal operating state.

Further, the gate of NM6 is connected to bias voltage VBLPBIAS, which counteracts the substrate bias effect of NM2 and compensates the on-resistance of NM2 under different voltages.

Compared with the prior art, the invention has at least one of the following advantages:

the invention discloses a novel voltage-compensated sensitive amplifier circuit which can offset the difference of drain voltage of a storage unit caused by different application voltages and improve the output consistency of the storage unit with different application voltages.

Drawings

Fig. 1 is a schematic structural diagram of a sense amplifier circuit according to an embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying fig. 1 and the detailed description. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise scale for the purpose of facilitating and distinctly aiding in the description of the embodiments of the present invention. To make the objects, features and advantages of the present invention comprehensible, reference is made to the accompanying drawings. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the implementation conditions of the present invention, so that the present invention has no technical significance, and any structural modification, ratio relationship change or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or field device that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or field device. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or field device that comprises the element.

Referring to fig. 1, the sense amplifier circuit provided in this embodiment includes an amplifying circuit and a bias circuit, where the bias circuit is configured to ensure that the amplifying circuit amplifies a voltage across the amplifying circuit without distortion, and the voltage amplified without distortion is applied to a drain of a memory CELL, where the voltage applied to the drain of the memory CELL is constant.

In this embodiment, the amplifying circuit includes a PMOS transistor PM1, an NMOS transistor NM2, NM 3; the source of PM1 is connected to voltage VDD, the gate of PM1 is connected to voltage VSABIAS, the drain of PM1 is connected to the drain of NM3, the source of NM3 and the drain of NM2 are connected to VBL1 end, the gate of NM2 is connected to power VDD, the source of NM2 and the drain of memory CELL are connected to VBL end, the gate of memory CELL is connected to voltage VWL, and the source of memory CELL is grounded.

In this embodiment, the bias circuit includes PMOS transistors PM2, PM3, NMOS transistors NM1, NM4, NM5, and NM 6; the source of PM2 is connected to voltage VDD, the gates of PM2 and NM6 are connected to bias voltage VBLPBIAS, the drain of PM2 is connected to the source of PM3, the gates of PM3 and NM4 are connected to control terminal ENB, the drains of PM3, NM4, NM5, NM5 and NM1 are connected to the gate of NM3, the sources of NM4 and NM6 are grounded, the sources of NM5 and NM1 are connected to the drain of NM6, and the gate of NM1 is connected to VBL 1.

In this embodiment, when the control end ENB is at a high level, the PM3 is turned off, the NM3 is turned on, the bias voltage VLIM is pulled to a low level, and the sense amplifier does not operate; when the control end ENB is at a low level, NM4 is turned off, PM3 is turned on, and the bias current of the bias tube PM2 controlled by the input VBLBIAS signal pulls up VLIM until the on-currents of NM1 and NM5 are equal to the current of the bias current tube PM2, where VLIM is the bias voltage of the post-amplifier, and the sense amplifier circuit enters a normal operating state. The bias voltage of the sense amplifier circuit can better switch the drain voltage VB1 of the control tube NM2 to be a constant output voltage.

In this embodiment, the gate of NM6 is not directly connected to VDD but to the bias voltage VBLPBIAS of PMOS transistor, and the substrate bias effects of NM6 and NM2 of the same type cancel each other out, so that the impedance changes of the two MOS transistors (NM2 and NM6) are close to each other, the voltage VBL finally loaded to the drain of the memory CELL is ensured to be equal under different working voltages, and the output consistency of the memory CELL at different application voltages is improved.

The sense amplifier circuit in the embodiment is used in a read circuit of a current memory chip, and the voltage difference of the voltage VBL of the 2.1V and 3.6V voltage parts of the original structure is reduced from 250mV to below 30 mV.

While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.

Claims

1. A sensitive amplifier circuit is characterized by comprising an amplifying circuit and a biasing circuit, wherein the biasing circuit is used for ensuring that the amplifying circuit amplifies voltage on the amplifying circuit without distortion, the voltage amplified without distortion is loaded to a drain electrode of a memory CELL CELL, and the voltage loaded to the drain electrode of the memory CELL CELL is constant.

2. The sense amplifier circuit of claim 1 wherein the amplification circuit comprises PMOS transistors PM1, NMOS transistors NM2, NM 3;

the source of PM1 is connected to voltage VDD, the gate of PM1 is connected to voltage VSABIAS, the drain of PM1 is connected to the drain of NM3, the source of NM3 is connected to the drain of NM2, the gate of NM2 is connected to power supply VDD, the source of NM2 is connected to the drain of memory CELL CELL, the gate of memory CELL CELL is connected to voltage VWL, and the source of memory CELL CELL is grounded.

3. The sense amplifier circuit of claim 2 wherein the bias circuit includes PMOS transistors PM2, PM3, NMOS transistors NM1, NM4, NM5, NM 6;

the source of PM2 is connected to voltage VDD, the gates of PM2 and NM6 are connected to bias voltage VBLPBIAS, the drain of PM2 is connected to the source of PM3, the gates of PM3 and NM4 are connected to control terminal ENB, the drains of PM3, NM4, NM5, NM5 and NM1 are connected to the gate of NM3, the sources of NM4 and NM6 are grounded, the sources of NM5 and NM1 are connected to the drain of NM6, and the gate of NM1 is connected to the drain of NM 2.

4. The sense amplifier circuit of claim 3 wherein when the control terminal ENB is high, PM3 is off, NM3 is on, the bias voltage VLIM is pulled low, and the sense amplifier is inactive.

5. The sense amplifier circuit as claimed in claim 3 or 4, wherein when the control terminal ENB is low, NM4 is turned off, PM3 is turned on, and the bias current of the bias tube PM2 controlled by the input VBLBIAS signal pulls up VLIM until the on-currents of NM1 and NM5 are equal to the current of the bias current tube PM2, where VLIM is the bias voltage of the subsequent amplifier, and the sense amplifier circuit enters a normal operation state.

6. The sense amplifier circuit of claim 3, wherein the gate connection bias voltage VBLPBIAS of NM6 is offset by the substrate bias effect of NM2 to compensate the on-resistance of NM2 under different voltages.