CN103956186A - Sense amplifier and flash memory device - Google Patents
Sense amplifier and flash memory device Download PDFInfo
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- CN103956186A CN103956186A CN201410197238.8A CN201410197238A CN103956186A CN 103956186 A CN103956186 A CN 103956186A CN 201410197238 A CN201410197238 A CN 201410197238A CN 103956186 A CN103956186 A CN 103956186A
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Abstract
The invention discloses a sense amplifier and a flash memory device. The sense amplifier comprises a bias circuit and an amplifying circuit, wherein one end of the bias circuit is connected with a power supply, and the other end of the bias circuit is connected with the first end of the amplifying circuit; the bias circuit is used for outputting a first bias voltage to the amplifying circuit during working of the sense amplifier and outputting a second bias voltage to the amplifying circuit when the sense amplifier does not work; the second bias voltage is between a grounding voltage and the first bias voltage; the second end of the amplifying circuit is connected with the power supply; the third end of the amplifying circuit is used for outputting a stable voltage. According to the invention, the energy consumption is lowered when the sense amplifier does not work, the target voltage establishing speed can be increased during working of the sense amplifier, and the working performance of the sense amplifier is improved.
Description
Technical field
The present invention relates to technical field of memory, be specifically related to a kind of sense amplifier and flash memory device.
Background technology
Sense amplifier (Sense amplifier) is very important circuit in storer, it is mainly used in by the state recognition of the data bit of storing in storage unit out, sense amplifier is when normal work, need constant bias voltage, this bias voltage can be provided by bias-voltage generating circuit, in actual applications, in the time of need to making as much as possible sense amplifier not work, there is the low power consumption of trying one's best, and can fast and stable when sense amplifier is worked to target voltage.
Fig. 1 is the circuit diagram of sense amplifier in prior art.As shown in Figure 1, at described first input end EN input low level, at the second input end IVREF input low level, the one PMOS pipe P1 cut-off, the one NMOS pipe N1 and the 2nd PMOS pipe P2 conducting, sense amplifier is not worked, bias voltage (NBIAS) is pulled to ground voltage, to reduce the power consumption of described sense amplifier, at described first input end EN input high level, at the second input end IVREF input low level, the one PMOS pipe P1 and described the 2nd PMOS pipe P2 conducting, the one NMOS pipe N1 cut-off, described sense amplifier carries out work, yet, described bias voltage from ground voltage need to be longer while coming back to target voltage Time Created, affect the reading speed of flash memories.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of sense amplifier and flash memory device, to solve sense amplifier, sets up the slow-footed problem of target voltage.
First aspect, the embodiment of the present invention provides a kind of sense amplifier, and described sense amplifier comprises biasing circuit and amplifying circuit,
One end of described biasing circuit is connected with power supply, the other end of described biasing circuit is connected with the first end of described amplifying circuit, described biasing circuit is for when described sense amplifier is worked, to described amplifying circuit, export the first bias voltage, when described sense amplifier is not worked, to described amplifying circuit, export the second bias voltage, described the second bias voltage is between ground voltage and described the first bias voltage;
The second end of described amplifying circuit is connected with power supply, and the 3rd end of described amplifying circuit is for the voltage of stable output.
Further, described biasing circuit comprises: first input end, the second input end, phase inverter, a PMOS pipe, the 2nd PMOS pipe, a NMOS pipe, the 3rd PMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe;
The input end of described phase inverter is connected with described first input end, and the output terminal of described phase inverter is connected with the grid of a described PMOS pipe; The source electrode of a described PMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe, the drain electrode of a described PMOS pipe is connected with the source electrode of described the 2nd NMOS pipe, the grid of described the 2nd PMOS pipe is connected with described the second input end, and the source electrode of described the 2nd PMOS pipe is connected with power supply;
A described grid for NMOS pipe and the output terminal of described phase inverter are connected, the source electrode of a described NMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe, the drain electrode of a described NMOS pipe is connected with the grid of described the 2nd NMOS pipe, the grid of described the 3rd PMOS pipe is connected with described the second input end, and the source electrode of described the 3rd PMOS pipe is connected with power supply;
The source electrode of described the 2nd NMOS pipe is connected with the drain electrode of a described PMOS pipe, and the grid of described the 2nd NMOS pipe is connected with the drain electrode of a described NMOS pipe, the grounded drain of described the 2nd NMOS pipe;
Described the 3rd source electrode of NMOS pipe and the other end of described biasing circuit are connected, the other end of described biasing circuit is the mid point of the drain electrode of a described NMOS pipe and the grid of described the 2nd NMOS pipe, the grid of described the 3rd NMOS pipe is connected with the 3rd end of described amplifying circuit, the grounded drain of described the 3rd NMOS pipe.
Further, described amplifying circuit comprises the 3rd input end, the 4th PMOS pipe and the 4th NMOS pipe,
The grid of described the 4th PMOS pipe is connected with described the 3rd input end, and the source electrode of described the 4th PMOS pipe is connected with power supply, and the drain electrode of described the 4th PMOS pipe is connected with the source electrode of described the 4th NMOS pipe;
Described the 4th grid of NMOS pipe and the other end of described biasing circuit are connected, and the drain electrode of described the 4th NMOS pipe is connected with the grid of described the 3rd NMOS pipe.
Further, described the 3rd input end is inputted constant low level, makes described the 4th PMOS pipe in conducting state.
Further, when described first input end input high level, during described the second input end input low level, a described PMOS pipe and described the 2nd PMOS pipe conducting, a described NMOS pipe cut-off, exports the first bias voltage according to the electric current that flows through described the 2nd PMOS pipe to described amplifying circuit;
When described first input end input low level, during described the second input end input low level, a described PMOS pipe cut-off, a described NMOS pipe and described the 3rd PMOS pipe conducting, export the second bias voltage according to the electric current that flows through described the 3rd PMOS pipe to described amplifying circuit.
Further, according to described the 2nd PMOS pipe and the ratio of described the 3rd PMOS pipe, determine the difference of described the second bias voltage and described the first bias voltage.
Further, described the 2nd PMOS pipe with the ratio of described the 3rd PMOS pipe is:
The number M of the 2nd PMOS pipe is multiplied by the value that the breadth length ratio of the 2nd PMOS pipe and the number N of the 3rd PMOS pipe are multiplied by the breadth length ratio of the 3rd PMOS pipe, and wherein, M and N are respectively the integer that is greater than 1.
Second aspect, the embodiment of the present invention provides a kind of flash memory device, and described flash memory device comprises storage unit and sense amplifier, and described storage unit is connected with described sense amplifier, wherein, described sense amplifier comprises the sense amplifier described in first aspect.
Further, described flash memory device also comprises the 5th NMOS pipe, the 3rd end of described the 5th source electrode of NMOS pipe and the amplifying circuit of described sense amplifier is connected, the drain electrode of described the 5th NMOS pipe is connected with described flash memories, the grid of described the 5th NMOS pipe is connected with power supply, and described the 5th NMOS pipe is for flash memories described in gating.
The sense amplifier that the embodiment of the present invention provides and flash memory device, when working, sense amplifier exports the first bias voltage to amplifying circuit, when not working, sense amplifier exports the second bias voltage to amplifying circuit, described the second bias voltage is between ground voltage and described the first bias voltage, when not worked, amplifier consumes energy low, amplifier when work can Speed-up Establishment target voltage speed, improved the serviceability of sense amplifier.
Accompanying drawing explanation
To the person of ordinary skill in the art is more clear that above-mentioned and other feature and advantage of the present invention by describe exemplary embodiment of the present invention in detail with reference to accompanying drawing below, in accompanying drawing:
Fig. 1 is the circuit diagram of sense amplifier in prior art;
Fig. 2 is the circuit structure diagram of a kind of sense amplifier of first embodiment of the invention;
Fig. 3 is the circuit structure diagram of a kind of flash memory device of second embodiment of the invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, in accompanying drawing, only show part related to the present invention but not full content.
Figure 2 illustrates the first embodiment of the present invention.
Fig. 2 is according to the circuit structure diagram of a kind of sense amplifier of first embodiment of the invention, and described sense amplifier comprises: biasing circuit 11 and amplifying circuit 12.
Wherein, one end of biasing circuit 11 is connected with power vd D, the other end of biasing circuit 11 is connected with the first end of amplifying circuit 12, described biasing circuit 11 is not for when sense amplifier is worked, to described amplifying circuit, export the first bias voltage, when described sense amplifier is not worked, to described amplifying circuit, export the second bias voltage, described the second bias voltage is between ground voltage and described the first bias voltage.
The second end of described amplifying circuit 12 is connected with power vd D, and the 3rd end of described amplifying circuit is for the voltage of stable output.
When described sense amplifier work, described biasing circuit 11 need to provide a first stable bias voltage to described amplifying circuit 12, described biasing circuit 11 is not when sense amplifier is worked, to described amplifying circuit 12 output the second bias voltages, described the second bias voltage is between ground voltage and the first bias voltage, target voltage in prior art when sense amplifier is worked need to be changed to target voltage from ground voltage, the biasing circuit of the sense amplifier that therefore the present embodiment provides only need increase few power consumption, but in the time of improving sense amplifier work, set up the speed of target voltage.
Concrete preferred, described biasing circuit 11 can comprise first input end EN, the second input end IVREF, phase inverter INVO, a PMOS pipe P1, the 2nd PMOS pipe P2, a NMOS pipe N1, the 3rd PMOS pipe P3, the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3.
Wherein, the input end of described phase inverter is connected with described first input end EN, and the output terminal of described phase inverter is connected with the grid of a described PMOS pipe P1; The source electrode of a described PMOS pipe P1 is connected with the drain electrode of described the 2nd PMOS pipe P2, the drain electrode of a described PMOS pipe P1 is connected with the source electrode of described the 2nd NMOS pipe N2, the grid of described the 2nd PMOS pipe P2 is connected with described the second input end IVREF, and the source electrode of described the 2nd PMOS pipe P2 is connected with power vd D; The grid of a described NMOS pipe N1 is connected with the output terminal of described phase inverter INVO, the source electrode of a described NMOS pipe N1 is connected with the drain electrode of described the 3rd PMOS pipe P3, the drain electrode of a described NMOS pipe N1 is connected with the grid of described the 2nd NMOS pipe N2, the grid of described the 3rd PMOS pipe P3 is connected with described the second input end IVREF, and the source electrode of described the 3rd PMOS pipe P3 is connected with power vd D; The source electrode of described the 2nd NMOS pipe N2 is connected with the drain electrode of a described PMOS pipe P1, and the grid of described the 2nd NMOS pipe N2 is connected with the drain electrode of a described NMOS pipe N1, the grounded drain of described the 2nd NMOS pipe N2; The source electrode of described the 3rd NMOS pipe N3 is connected with the other end of described biasing circuit 11, the other end of described biasing circuit 11 is the mid point of the drain electrode of a described NMOS pipe N1 and the grid of described the 2nd NMOS pipe N2, the other end of described biasing circuit is used for to described amplifying circuit 12 output offset voltages, described the 3rd NMOS pipe grid of N3 and the 3rd end of described amplifying circuit 12 are connected, the grounded drain of described the 3rd NMOS pipe N3.
Described amplifying circuit 12 comprises the 3rd input end SAIN, the 4th PMOS pipe P4 and the 4th NMOS pipe N4.
Wherein, the grid of described the 4th PMOS pipe P4 is connected with described the 3rd input end SAIN, the source electrode of described the 4th PMOS pipe P4 is connected with power vd D, the drain electrode of described the 4th PMOS pipe P4 is connected with the source electrode of described the 4th NMOS pipe N4, the grid of described the 4th NMOS pipe N4 is connected with the other end of described biasing circuit 11, and the drain electrode of described the 4th NMOS pipe N4 is connected with the grid of described the 3rd NMOS pipe N3.
Described biasing circuit 11 provides the first bias voltage to described amplifying circuit 12 when sense amplifier is worked, described the first bias voltage is through the output terminal output of amplifying circuit 12, the output terminal of described amplifying circuit 12 preferably can connect a flash memory, thereby reads the data of storing in flash memory cell.
In the present embodiment, when described first input end EN input high level, during described the second input end IVREF input low level, a described PMOS pipe P1 and described the 2nd PMOS pipe P2 conducting, a described NMOS pipe N1 cut-off, exports the first bias voltages according to the electric current that flows through described the 2nd PMOS pipe P2 to described amplifying circuit 12.
When described first input end EN input low level, during described the second input end IVREF input low level, a described PMOS pipe P1 cut-off, a described NMOS pipe N1 and described the 3rd PMOS pipe P3 conducting, export the second bias voltage according to the electric current that flows through described the 3rd PMOS pipe P3 to described amplifying circuit.
The electric current that flows through the 2nd PMOS pipe P2 and the 3rd PMOS pipe P3 is relevant with the number of the breadth length ratio of described the 2nd PMOS pipe P2 and the 3rd PMOS pipe P3 and the pipe of described the 2nd PMOS pipe P2 and the 3rd PMOS pipe P3 respectively, described sense amplifier flows through the electric current that equals to flow through described the 3rd PMOS pipe of described biasing circuit 11 while not working, breadth length ratio and number one timing as described the 2nd PMOS pipe P2, the breadth length ratio of described the 3rd PMOS pipe P3 is less, number is fewer, the electric current that flows through the 3rd PMOS pipe P3 is less, the second bias voltage of setting up when described sense amplifier is not worked is less, power consumption when described sense amplifier is not worked is less.
According to described the 2nd PMOS pipe and the ratio of described the 3rd PMOS pipe, determine the difference of described the second bias voltage and described the first bias voltage.
The ratio that described the 2nd PMOS manages P2 and described the 3rd PMOS pipe P3 is: the number M of the 2nd PMOS pipe P2 is multiplied by the breadth length ratio of the 2nd PMOS pipe P2 and the number N of the 3rd PMOS pipe P3 is multiplied by the value that the 3rd PMOS manages the breadth length ratio of P3, wherein, M and N are respectively the integer that is greater than 1.
For example: the number of described the 2nd PMOS pipe is 2, the breadth length ratio of described the 2nd PMOS pipe is 2:1, and the number of described the 3rd PMOS pipe is 1, and the breadth length ratio of described the 3rd PMOS pipe is 2:1, and described the 2nd PMOS pipe is 2:1 with the ratio of described the 3rd PMOS pipe.
When breadth length ratio and the number of tubes of described the 2nd PMOS pipe P2 more approaching with breadth length ratio and number of tubes that described the 3rd PMOS manages P3, the first bias voltage of setting up when the second bias voltage of setting up when sense amplifier is not worked and sense amplifier work is more approaching, the speed of setting up target voltage during the work of described sense amplifier is faster, but simultaneously sense amplifier not the power consumption of need of work consumption also increase.Therefore, need to design the ratio that the 2nd PMOS pipe P2 and described the 3rd PMOS manage P3, when sense amplifier is not worked, only increase few power consumption, and speed that can Speed-up Establishment target voltage when sense amplifier is worked.
The ratio of managing P2 and described the 3rd PMOS pipe P3 as described the 2nd PMOS is larger, power consumption when described sense amplifier is not worked is less, and the speed of setting up target voltage when described sense amplifier work is faster, the bias current that ought flow through described the 2nd PMOS pipe P2 is larger, the bias current that flows through described the 3rd PMOS pipe P3 is less, it is faster that sense amplifier is set up the speed of target voltage, and power consumption when sense amplifier is not worked is less.
The sense amplifier that first embodiment of the invention provides, when sense amplifier is worked, described biasing circuit is exported the first bias voltage to described amplifying circuit, when sense amplifier is not worked, described biasing circuit is exported the second bias voltage to described amplifying circuit, and described the second bias voltage is between ground voltage and the first bias voltage, while making like this sense amplifier not work, only need to increase few energy consumption, and can complete target voltage by Rapid Establishment when sense amplifier is worked, thereby accelerated the precharge speed of sense amplifier.
Figure 3 illustrates the second embodiment of the present invention.
Fig. 3 is according to the circuit structure diagram of a kind of flash memory device of second embodiment of the invention, and described flash memory device comprises storage unit 21 and sense amplifier 22, and described storage unit 21 is connected with described sense amplifier 22 by bit line.
Wherein, described sense amplifier 22 comprises biasing circuit 221 and amplifying circuit 222.One end of described biasing circuit 221 is connected with power vd D, the other end of biasing circuit 221 is connected with the first end of amplifying circuit 222, described biasing circuit 221 is not for when sense amplifier is worked, to described amplifying circuit 222 output the first bias voltages, when described sense amplifier is not worked, to described amplifying circuit 222 output the second bias voltages, described the second bias voltage is between ground voltage and described the first bias voltage.
The second end of described amplifying circuit 222 is connected with power vd D, and the 3rd end of described amplifying circuit is for the voltage of stable output.
Concrete preferred, described biasing circuit 221 can comprise (sign about each device please refer to Fig. 2): first input end EN, the second input end IVREF, phase inverter INVO, a PMOS pipe P1, the 2nd PMOS pipe P2, a NMOS pipe N1, the 3rd PMOS pipe P3, the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3.
Wherein, the input end of described phase inverter is connected with described first input end EN, and the output terminal of described phase inverter is connected with the grid of a described PMOS pipe P1; The source electrode of a described PMOS pipe P1 is connected with the drain electrode of described the 2nd PMOS pipe P2, the drain electrode of a described PMOS pipe P1 is connected with the source electrode of described the 2nd NMOS pipe N2, the grid of described the 2nd PMOS pipe P2 is connected with described the second input end IVREF, and the source electrode of described the 2nd PMOS pipe P2 is connected with power vd D; The grid of a described NMOS pipe N1 is connected with the output terminal of described phase inverter INVO, the source electrode of a described NMOS pipe N1 is connected with the drain electrode of described the 3rd PMOS pipe P3, the drain electrode of a described NMOS pipe N1 is connected with the grid of described the 2nd NMOS pipe N2, the grid of described the 3rd PMOS pipe P3 is connected with described the second input end IVREF, and the source electrode of described the 3rd PMOS pipe P3 is connected with power vd D; The source electrode of described the 2nd NMOS pipe N2 is connected with the drain electrode of a described PMOS pipe P1, and the grid of described the 2nd NMOS pipe N2 is connected with the drain electrode of a described NMOS pipe N1, the grounded drain of described the 2nd NMOS pipe N2; The source electrode of described the 3rd NMOS pipe N3 is connected with the other end of described biasing circuit 221, the other end of described biasing circuit 221 is the mid point of the drain electrode of a described NMOS pipe N1 and the grid of described the 2nd NMOS pipe N2, the other end of described biasing circuit is used for to described amplifying circuit 222 output offset voltages, described the 3rd NMOS pipe grid of N3 and the 3rd end of described amplifying circuit 222 are connected, the grounded drain of described the 3rd NMOS pipe N3.
Described amplifying circuit 222 comprises the 3rd input end SAIN, the 4th PMOS pipe P4 and the 4th NMOS pipe N4.
Wherein, the grid of described the 4th PMOS pipe P4 is connected with described the 3rd input end SAIN, the source electrode of described the 4th PMOS pipe P4 is connected with power vd D, the drain electrode of described the 4th PMOS pipe P4 is connected with the source electrode of described the 4th NMOS pipe N4, the grid of described the 4th NMOS pipe N4 is connected with the other end of described biasing circuit 221, and the drain electrode of described the 4th NMOS pipe N4 is connected with the grid of described the 3rd NMOS pipe N3.
Described biasing circuit 221 can be so that when described sense amplifier work, to described amplifying circuit 222 output the first bias voltages, when described sense amplifier is not worked, to described amplifying circuit 222 output the second bias voltages, described the second bias voltage is between ground voltage and described the first bias voltage.
Particularly, when described first input end EN input high level, during described the second input end IVREF input low level, a described PMOS pipe P1 and described the 2nd PMOS pipe P2 conducting, a described NMOS pipe N1 cut-off, exports the first bias voltages according to the electric current that flows through the 2nd PMOS pipe P2 to described amplifying circuit 222.
When described first input end EN input low level, during described the second input end IVREF input low level, a described PMOS pipe P1 cut-off, a described NMOS pipe N1 and described the 3rd PMOS pipe P3 conducting, export the second bias voltages according to the electric current that flows through the 3rd PMOS pipe P3 to described amplifying circuit 222.
The difference of described the second bias voltage and described the first bias voltage is determined according to the ratio of described the 2nd PMOS pipe P2 and described the 3rd PMOS pipe P3.
The ratio that described the 2nd PMOS manages P2 and described the 3rd PMOS pipe P3 is: the number M of the 2nd PMOS pipe P2 is multiplied by the breadth length ratio of the 2nd PMOS pipe P2 and the number N of the 3rd PMOS pipe P3 is multiplied by the value that the 3rd PMOS manages the breadth length ratio of P3, wherein, M and N are respectively the integer that is greater than 1.
The ratio of managing P2 and described the 3rd PMOS pipe P3 as described the 2nd PMOS is larger, the bias current that ought flow through described the 2nd PMOS pipe P2 is larger, the bias current that flows through described the 3rd PMOS pipe P3 is less, power consumption when described sense amplifier is not worked is less, and the speed of setting up target voltage during described sense amplifier work is faster, it is faster that sense amplifier is set up the speed of target voltage, and power consumption when sense amplifier is not worked is less.
In the preferred embodiment of the present embodiment, described flash memory device also comprises the 5th NMOS pipe N5, the 3rd end of described the 5th NMOS pipe source electrode of N5 and the amplifying circuit of described sense amplifier 222 is connected, the drain electrode of described the 5th NMOS pipe N5 is connected with described storage unit 21, the grid of described the 5th NMOS pipe is connected with power supply, and described the 5th NMOS pipe is for storage unit described in gating.
The flash memory device that second embodiment of the invention provides, when sense amplifier is worked, described biasing circuit is exported the first bias voltage to described amplifying circuit, when sense amplifier is not worked, described biasing circuit is exported the second bias voltage to described amplifying circuit, described the second bias voltage is between ground voltage and the first bias voltage, when sense amplifier is not worked, only need to increase few energy consumption, and when sense amplifier is worked, the very fast speed of setting up of target voltage, thus the reading speed of sense amplifier accelerated.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, to those skilled in the art, the present invention can have various changes and variation.All any modifications of doing, be equal to replacement, improvement etc., within protection scope of the present invention all should be included within spirit of the present invention and principle.
Claims (9)
1. a sense amplifier, is characterized in that, described sense amplifier comprises biasing circuit and amplifying circuit,
One end of described biasing circuit is connected with power supply, the other end of described biasing circuit is connected with the first end of described amplifying circuit, described biasing circuit is for when described sense amplifier is worked, to described amplifying circuit, export the first bias voltage, when described sense amplifier is not worked, to described amplifying circuit, export the second bias voltage, described the second bias voltage is between ground voltage and described the first bias voltage;
The second end of described amplifying circuit is connected with power supply, and the 3rd end of described amplifying circuit is for the voltage of stable output.
2. sense amplifier according to claim 1, it is characterized in that, described biasing circuit comprises: first input end, the second input end, phase inverter, a PMOS pipe, the 2nd PMOS pipe, a NMOS pipe, the 3rd PMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe;
The input end of described phase inverter is connected with described first input end, and the output terminal of described phase inverter is connected with the grid of a described PMOS pipe; The source electrode of a described PMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe, the drain electrode of a described PMOS pipe is connected with the source electrode of described the 2nd NMOS pipe, the grid of described the 2nd PMOS pipe is connected with described the second input end, and the source electrode of described the 2nd PMOS pipe is connected with power supply;
A described grid for NMOS pipe and the output terminal of described phase inverter are connected, the source electrode of a described NMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe, the drain electrode of a described NMOS pipe is connected with the grid of described the 2nd NMOS pipe, the grid of described the 3rd PMOS pipe is connected with described the second input end, and the source electrode of described the 3rd PMOS pipe is connected with power supply;
The source electrode of described the 2nd NMOS pipe is connected with the drain electrode of a described PMOS pipe, and the grid of described the 2nd NMOS pipe is connected with the drain electrode of a described NMOS pipe, the grounded drain of described the 2nd NMOS pipe;
Described the 3rd source electrode of NMOS pipe and the other end of described biasing circuit are connected, the other end of described biasing circuit is the mid point of the drain electrode of a described NMOS pipe and the grid of described the 2nd NMOS pipe, the grid of described the 3rd NMOS pipe is connected with the 3rd end of described amplifying circuit, the grounded drain of described the 3rd NMOS pipe.
3. sense amplifier according to claim 1, is characterized in that, described amplifying circuit comprises the 3rd input end, the 4th PMOS pipe and the 4th NMOS pipe;
The grid of described the 4th PMOS pipe is connected with described the 3rd input end, and the source electrode of described the 4th PMOS pipe is connected with power supply, and the drain electrode of described the 4th PMOS pipe is connected with the source electrode of described the 4th NMOS pipe;
Described the 4th grid of NMOS pipe and the other end of described biasing circuit are connected, and the drain electrode of described the 4th NMOS pipe is connected with the grid of described the 3rd NMOS pipe.
4. sense amplifier according to claim 3, is characterized in that, described the 3rd input end is inputted constant low level, makes described the 4th PMOS pipe in conducting state.
5. sense amplifier according to claim 1, is characterized in that,
When described first input end input high level, during described the second input end input low level, a described PMOS pipe and described the 2nd PMOS pipe conducting, a described NMOS pipe cut-off, exports the first bias voltage according to the electric current that flows through described the 2nd PMOS pipe to described amplifying circuit;
When described first input end input low level, during described the second input end input low level, a described PMOS pipe cut-off, a described NMOS pipe and described the 3rd PMOS pipe conducting, export the second bias voltage according to the electric current that flows through described the 3rd PMOS pipe to described amplifying circuit.
6. sense amplifier according to claim 5, is characterized in that, determines the difference of described the second bias voltage and described the first bias voltage according to described the 2nd PMOS pipe and the ratio of described the 3rd PMOS pipe.
7. sense amplifier according to claim 6, is characterized in that, described the 2nd PMOS pipe with the ratio of described the 3rd PMOS pipe is:
The number M of the 2nd PMOS pipe is multiplied by the ratio that the breadth length ratio of the 2nd PMOS pipe and the number N of the 3rd PMOS pipe are multiplied by the breadth length ratio of the 3rd PMOS pipe, and wherein, M and N are respectively the integer that is greater than 1.
8. a flash memory device, it is characterized in that, described flash memory device comprises flash memory cell and sense amplifier, and described storage unit is connected with described sense amplifier, wherein, described sense amplifier comprises the sense amplifier as described in any one in claim 1-7.
9. flash memory device according to claim 8, it is characterized in that, described flash memory device also comprises the 5th NMOS pipe, the 3rd end of described the 5th source electrode of NMOS pipe and the amplifying circuit of described sense amplifier is connected, the drain electrode of described the 5th NMOS pipe is connected with described flash memories, the grid of described the 5th NMOS pipe is connected with power supply, and described the 5th NMOS pipe is for storage unit described in gating.
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| CN201410197238.8A CN103956186B (en) | 2014-05-12 | 2014-05-12 | Sense amplifier and flash memory device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107404291A (en) * | 2017-01-13 | 2017-11-28 | 上海韦玏微电子有限公司 | Biasing circuit and low-noise amplifier |
| CN112509617A (en) * | 2020-10-30 | 2021-03-16 | 普冉半导体(上海)股份有限公司 | Sensitive amplifier circuit |
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| CN101546604A (en) * | 2009-04-29 | 2009-09-30 | 深圳市远望谷信息技术股份有限公司 | Sensitive amplifier applied to EEPROM |
| CN203870979U (en) * | 2014-05-12 | 2014-10-08 | 北京兆易创新科技股份有限公司 | Sense amplifier and flash memory storage device |
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| US20020075724A1 (en) * | 2000-12-20 | 2002-06-20 | Micron Technology, Inc. | Non-volatile memory with power standby |
| JP2002269991A (en) * | 2001-03-13 | 2002-09-20 | Nec Microsystems Ltd | Sense amplifier circuit |
| US20040125670A1 (en) * | 2002-09-17 | 2004-07-01 | Stmicroelectronics S.R.L. | Circuit for biasing an input node of a sense amplifier with a pre-charge stage |
| US20060018169A1 (en) * | 2004-07-21 | 2006-01-26 | Dialog Semiconductor Gmbh | Dynamical biasing of memory sense amplifiers |
| CN101546604A (en) * | 2009-04-29 | 2009-09-30 | 深圳市远望谷信息技术股份有限公司 | Sensitive amplifier applied to EEPROM |
| CN203870979U (en) * | 2014-05-12 | 2014-10-08 | 北京兆易创新科技股份有限公司 | Sense amplifier and flash memory storage device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107404291A (en) * | 2017-01-13 | 2017-11-28 | 上海韦玏微电子有限公司 | Biasing circuit and low-noise amplifier |
| CN107404291B (en) * | 2017-01-13 | 2020-09-11 | 上海韦玏微电子有限公司 | Bias circuit and low noise amplifier |
| CN112509617A (en) * | 2020-10-30 | 2021-03-16 | 普冉半导体(上海)股份有限公司 | Sensitive amplifier circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103956186B (en) | 2017-05-24 |
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |