CN112507650A - Equal-length design method of DDR wiring and related assembly - Google Patents
Equal-length design method of DDR wiring and related assembly Download PDFInfo
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- CN112507650A CN112507650A CN202011302374.0A CN202011302374A CN112507650A CN 112507650 A CN112507650 A CN 112507650A CN 202011302374 A CN202011302374 A CN 202011302374A CN 112507650 A CN112507650 A CN 112507650A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Abstract
The invention discloses an isometric design method of DDR wiring and a related assembly, comprising the steps of determining the maximum length difference value between the DDR internal encapsulation lengths of signal wires in the same isometric group; determining the transmission time length of the signal on the signal line with the length equal to the maximum length difference on the PCB made of different materials; and carrying out difference processing on the time difference between the equal-length allowable time delay and the transmission time length so as to design the length of the signal line based on the obtained difference value. Therefore, the transmission errors introduced by the PCBs made of different materials can be evaluated, the allowance consumed by the transmission errors is removed in the equal-length allowable time delay, and then when the length of the signal wire is set according to the equal-length allowable time delay obtained in the mode, the signal wire can meet the equal-length setting requirements of the PCBs made of different materials, the signal transmission quality is improved, the PCBs made of different materials can share the DDR design, and the design difficulty of the signal wire is not excessively increased.
Description
Technical Field
The invention relates to the technical field of board card wiring, in particular to an isometric design method of DDR wiring and a related assembly.
Background
In conventional digital system designs, high speed interconnect phenomena are often negligible because they have a weak impact on the performance of the system. However, with the continuous development of computer technology, among the factors determining the performance of the system, the phenomenon of high-speed interconnection is playing a leading role, often resulting in some unpredictable problems, and greatly increasing the complexity of system design. Therefore, in the high-speed link design, each module is optimized as much as possible, the design feasibility and risk points are evaluated in advance by means of a simulation tool, the design is optimized according to the simulation result, the success rate of the system design is improved, and the research and development period is shortened.
In the DDR (Double Data Rate) link design process of the server system, equal length design of signal lines is particularly important. The length of the signal line comprises two parts of the chip internal packaging length and the PCB (Printed Circuit Board) Board wiring length, the equal length requirement of the signal line is that the total length meets the equal length rule, when the DDR chip internal packaging length is inconsistent, the PCB Board wiring length needs to be optimized, and the sum of the two parts of wiring lengths meets the equal length requirement. When the link does not meet the equal-length design requirement, the signal quality is deteriorated, some unforeseeable problems are often caused, and the system design risk is greatly increased.
In practical application, although the design requirements of equal length of signal lines can be met in most cases through a winding mode, the equal length of the winding mode has certain limitations for some special application scenarios. Specifically, the purpose of making the signal lines with equal length is to control the time delay, but the propagation speeds of the signal lines in different medium environments are different, for example, when the system board card is used with different PCB materials, the transmission speeds of the signals are different, even if the signal lines meet the requirements of the length and the like, the delay requirements may not be met, and the DDR design may not be suitable for PCB boards of different materials.
Disclosure of Invention
The invention aims to provide an isometric design method of DDR wiring and a related assembly, so that a signal line can meet isometric setting requirements of PCBs (printed circuit boards) made of different materials, the signal transmission quality is improved, compared with the condition that the isometric allowable time delay is set to be very small, PCBs made of different materials can share DDR design, and the design difficulty of the signal line cannot be increased excessively.
In order to solve the technical problem, the invention provides an isometric design method of DDR wiring, which comprises the following steps:
determining the maximum length difference value between the DDR internal encapsulation lengths of the signal lines in the same equal length group;
determining the transmission time length of the signal on the signal line with the length equal to the maximum length difference on the PCB made of different materials;
and carrying out difference processing on the time difference between the equal-length allowable time delay and the transmission time length so as to design the length of the signal line based on the obtained difference value.
Preferably, determining the maximum difference between the DDR internal package lengths of the signal lines within the same equal length group comprises:
respectively determining the maximum value and the minimum value of the DDR internal encapsulation length of each signal line in the same equal-length group;
and performing difference processing on the maximum value and the minimum value of the DDR internal encapsulation lengths of the signal lines to obtain the maximum length difference value between the DDR internal encapsulation lengths of the signal lines in the same equal-length group.
Preferably, determining the transmission time length of the signal on the signal line with the length equal to the maximum length difference on the PCB board made of different materials includes:
and determining the transmission time length of the signal on the signal line with the length equal to the maximum length difference on the PCB with different dielectric constants.
Preferably, the time difference between the equal-length allowed time delay and the transmission time length is subjected to difference processing, and the difference processing includes:
determining the maximum transmission time and the minimum transmission time in PCBs made of different materials;
carrying out difference processing on the maximum transmission time length and the minimum transmission time length in the PCBs made of different materials to obtain the maximum time difference of the transmission time lengths;
and carrying out difference processing on the maximum time difference between the equal-length allowed time delay and the transmission time length.
In order to solve the above technical problem, the present invention further provides an isometric design system for DDR wiring, including:
the maximum length difference determining unit is used for determining the maximum length difference between the DDR internal packaging lengths of the signal lines in the same equal length group;
the transmission duration determining unit is used for determining the transmission duration of the signals on the signal lines with the length equal to the maximum length difference on the PCB made of different materials;
and the equal-length allowable delay adjusting unit is used for carrying out difference processing on the time difference between the equal-length allowable delay and the transmission time length so as to design the length of the signal line based on the obtained difference value.
Preferably, the maximum length difference value determination unit includes:
the length maximum value determining unit is used for respectively determining the maximum value and the minimum value of the DDR internal encapsulation length of each signal line in the same equal-length group;
and the length difference unit is used for carrying out difference processing on the maximum value and the minimum value of the DDR internal encapsulation lengths of the signal lines to obtain the maximum length difference value between the DDR internal encapsulation lengths of the signal lines in the same equal length group.
Preferably, the transmission duration determining unit is specifically configured to determine a transmission duration of the signal on the signal line with the length equal to the maximum length difference on the PCB board with different dielectric constants.
Preferably, the equal-length allowable delay adjusting unit includes:
the transmission time length maximum value determining unit is used for determining the maximum transmission time length and the minimum transmission time length in the PCBs made of different materials;
the time length difference making unit is used for making difference processing on the maximum transmission time length and the minimum transmission time length in the PCBs made of different materials to obtain the maximum time difference of the transmission time lengths;
and the equal-length allowed time delay difference making unit is used for making difference processing on the maximum time difference between the equal-length allowed time delay and the transmission time length.
In order to solve the above technical problem, the present invention further provides an isometric design apparatus for DDR wiring, including:
a memory for storing a computer program;
and the processor is used for realizing the steps of the equal-length design method of the DDR wiring when executing the computer program.
In order to solve the above technical problem, the present invention further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the equal-length design method for DDR wiring are implemented.
The invention provides an isometric design method of DDR wiring and a related assembly, comprising the steps of determining the maximum length difference value between the DDR internal encapsulation lengths of signal wires in the same isometric group; determining the transmission time length of the signal on the signal line with the length equal to the maximum length difference on the PCB made of different materials; and carrying out difference processing on the time difference between the equal-length allowable time delay and the transmission time length so as to design the length of the signal line based on the obtained difference value. Therefore, the transmission errors introduced by the PCBs made of different materials can be evaluated, the allowance consumed by the transmission errors is removed in the equal-length allowable time delay, and then when the length of the signal wire is set according to the equal-length allowable time delay obtained in the mode, the signal wire can meet the equal-length setting requirements of the PCBs made of different materials, the signal transmission quality is improved, the PCBs made of different materials can share the DDR design, and the design difficulty of the signal wire is not excessively increased.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a process flow diagram of an isometric design method for DDR wiring according to the present invention;
fig. 2 is a schematic diagram of a simplified DDR routing topology provided by the present invention;
FIG. 3 is a schematic structural diagram of an isometric design system for DDR wiring according to the present invention;
fig. 4 is a schematic structural diagram of an isometric design apparatus for DDR wiring according to the present invention.
Detailed Description
The core of the invention is to provide an isometric design method of DDR wiring and related components, so that a signal line can meet isometric setting requirements of PCBs (printed circuit boards) made of different materials, the signal transmission quality is improved, the PCBs made of different materials can share DDR design, and the design difficulty of the signal line cannot be excessively increased.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a process flow chart of an isometric design method for DDR wiring according to the present invention.
The equal length design method comprises the following steps:
s11: determining the maximum length difference value between the DDR internal encapsulation lengths of the signal lines in the same equal length group;
s12: determining the transmission time length of the signal on the signal line with the length equal to the maximum length difference on the PCB made of different materials;
s13: and carrying out difference processing on the time difference between the equal-length allowable time delay and the transmission time length so as to design the length of the signal line based on the obtained difference value.
Specifically, in practical applications, signal lines on the board may be grouped, and the signal lines in the same group need to receive signals and transmit signals at the same time. In practical application, when the time delay between the signal lines in the equal length group is smaller than the allowed time delay of the equal length, the signal lines in the equal length group are considered to meet the equal length rule. Wherein the equal length allowable delay may be, but is not limited to, 5 ps.
In addition, considering that the DDR internal package lengths of the signal lines in the same equal-length group are fixed and may be different when the chip leaves the factory, in order to meet the equal-length rule, only starting from the signal lines on the PCB, specifically, by means of winding on the PCB, length compensation is performed on the shorter signal lines on the PCB, so that the sum of the DDR internal package lengths of the signal lines in the same group and the routing length of the PCB board card is consistent. The PCB with different materials can affect the signal transmission speed of the signal wire, therefore, the signal on the signal wire with the same compensation length can generate different transmission time lengths when being transmitted on the PCB with different materials, namely, the same compensation length, but the transmission time length of the signal wire with the compensation length on the PCB A is different from the transmission time length on the PCB B, so that the signal wires of the group can meet the equal length rule when being arranged on the PCB A and the PCB B, but the time delay requirement can be met when being arranged on the PCB A, the time delay requirement can not be met when being arranged on the PCB B, or the time delay requirement can be met when being arranged on the PCB B, and the time delay requirement can not be met when being arranged on the PCB A. As can be seen, if the material of the PCB is not considered in the DDR design, the PCBs with different materials may not share the DDR design.
In order to solve the above technical problem, in the present application, first, the DDR internal package lengths of the signal lines in the same equal length group are determined and the maximum length difference between the DDR internal package lengths is obtained, where the maximum length difference is also the maximum length difference between two corresponding signal lines on the PCB, it should be noted that, here, the maximum length difference is calculated because the signal lines with the length being the maximum length difference need to be compensated for the corresponding signal lines on the PCB, and transmission durations of signals on the signal lines with the length being the maximum length difference on PCBs made of different materials are different, which may affect delays of the signal lines on PCBs made of different materials. In order to eliminate the influence of the maximum length difference value signal line on the time delay on the PCBs made of different materials, after the maximum length difference value is obtained, the transmission time length of the signal on the signal line with the length equal to the maximum length difference value on the PCBs made of different materials is obtained, so that the time difference between the transmission time lengths of the signal on the signal line with the length equal to the maximum length difference value on the PCBs made of different materials can be obtained, finally, the time difference between the equal length allowable time delay and the transmission time length is subjected to difference processing, the allowance of the time difference offset of the transmission time length is removed in the equal length allowable time delay, and the length of the signal line can be designed based on the equal length allowable time delay with the transmission time length subtracted in the.
In addition, the PCB boards of different materials can be selected according to actual requirements, for example, the PCB boards of some common materials. It should be noted that, taking A, B, C, D as an example of transmission durations of signals on the signal lines with the length equal to the maximum length difference from large to small of 4 PCBs made of different materials, the time difference may be a time difference between the maximum transmission duration and the minimum transmission duration of the PCBs made of different materials, that is, a-D, or a time difference between two other transmission durations, that is, a-C. If the signal line length is a-D, then the DDR design can be shared by the PCBs of different materials when the signal line length is designed based on the equal length allowed delay obtained by subtracting the transmission duration, and if the signal line length is a-C, then the DDR design can be shared by some PCBs of different materials.
Therefore, the transmission errors introduced by the PCBs made of different materials can be evaluated, the allowance consumed by the transmission errors is removed in the equal-length allowable time delay, and then when the length of the signal line is set according to the equal-length allowable time delay obtained in the mode, the signal line can meet the equal-length setting requirements of the PCBs made of different materials, the signal transmission quality is improved, and compared with the small method for directly setting the equal-length allowable time delay (when the equal-length allowable time delay is set to be very small, although the DDR design can be shared by the PCBs made of different materials, the compensation amount of the signal line on the PCB can be increased, the winding difficulty on the PCB is increased, even due to space limitation, the DDR design after tightening can not be met), the PCBs made of different materials can share the design, and the design difficulty of the signal line cannot be excessively increased.
On the basis of the above-described embodiment:
as a preferred embodiment, determining the maximum difference between the DDR internal package lengths of the signal lines within the same equal length group comprises:
respectively determining the maximum value and the minimum value of the DDR internal encapsulation length of each signal line in the same equal-length group;
and performing difference processing on the maximum value and the minimum value of the DDR internal encapsulation lengths of the signal lines to obtain the maximum length difference value between the DDR internal encapsulation lengths of the signal lines in the same equal-length group.
Specifically, as mentioned above, the maximum length difference is the maximum length difference between two corresponding signal lines on the PCB, for example, the length difference between the DDR internal package lengths of the a and B signal lines in the same equal length group is the maximum length difference, and then the length difference between the a and B signal lines on the PCB is also the maximum length difference. Taking the DDR internal package length of the a signal line is greater than the DDR internal package length of the B signal line as an example, the signal line with the maximum length difference is subsequently compensated for the B signal line on the PCB board. To achieve equal lengths of the a and B signal lines.
In order to obtain the maximum difference between the DDR internal package lengths of the signal lines in the same equal length group, in this embodiment, first, the maximum value and the minimum value of the DDR internal package lengths of the signal lines in the same equal length group are determined, and then the minimum value is subtracted from the maximum value of the DDR internal package lengths of the signal lines, so as to obtain the maximum length difference between the DDR internal package lengths of the signal lines in the same equal length group.
Therefore, the maximum length difference between the DDR internal encapsulation lengths of the signal lines in the same equal-length group can be simply and reliably obtained through the method, and the influence of PCBs made of different materials on the transmission time of the signals on the signal lines with the maximum length difference can be conveniently eliminated in the follow-up process.
As a preferred embodiment, determining the transmission time length of the signal on the signal line with the length equal to the maximum length difference on the PCB board made of different materials includes:
and determining the transmission time length of the signal on the signal line with the length equal to the maximum length difference on the PCB with different dielectric constants.
Specifically, the main parameter influencing the transmission speed of the signal on the PCB is the dielectric constant of the PCB, so that the PCB made of different materials is embodied by the PCB with different dielectric constants.
Referring to table 1, table 1 shows Dk (Dielectric Constant) values of PCBs made of different materials according to the present invention.
TABLE 1 Dk values of PCBs of different materials
As a preferred embodiment, the time difference between the equal-length allowed time delay and the transmission time length is subjected to difference processing, which includes:
determining the maximum transmission time and the minimum transmission time in PCBs made of different materials;
carrying out difference processing on the maximum transmission time length and the minimum transmission time length in the PCBs made of different materials to obtain the maximum time difference of the transmission time lengths;
and carrying out difference processing on the maximum time difference between the equal-length allowed time delay and the transmission time length.
Specifically, after the transmission time length of the signal on the signal line with the degree equal to the maximum length difference value on the PCBs made of different materials is obtained, in order to enable the DDR design to be applicable to all the PCBs, in the present application, the maximum transmission time length and the minimum transmission time length in the PCBs made of different materials are determined, and the maximum transmission time length is subtracted from the minimum transmission time length to obtain the maximum time difference of the transmission time lengths, and then the maximum time difference of the transmission time lengths is subtracted from the equal-length allowable time length, that is, the margin consumed by the transmission error is removed from the equal-length allowable time length. Then, when the length of the signal line is set according to the equal-length allowable delay obtained in the manner, the signal line can meet the equal-length setting requirements of the PCBs made of different materials, so that the signal transmission quality is improved, and compared with the very small time when the equal-length allowable delay is directly set, the PCBs made of different materials can share the DDR design, and the design difficulty of the signal line cannot be excessively increased.
The present application is described below with a specific example:
referring to fig. 2, fig. 2 is a schematic diagram of a simplified DDR routing topology provided in the present invention, and fig. 2 only uses one line as an example.
DDR signals sent from a Central Processing Unit (CPU) reach a terminal through package wiring L1 and wiring L2 on the PCB. Given an allowable time delay of 5ps for equal length, the PCB board of the present system may use four grades of materials in the manufacturing process, see table 1 above. The package manual of the chip is queried to list the DDR internal package lengths within a certain equal length group as shown in table 2.
TABLE 2 DDR internal package length of each signal line in the same equal length group
The maximum length difference of the package lengths in the 8 signal lines in the same length group, that is, the difference between DQ1 and DQ7, is calculated to be 131 mils, which means that the difference between the on-board traces corresponding to the two signal lines is also the maximum. Two materials with the largest Dk value difference among the PCB alternative materials are selected, the corresponding transmission speeds are calculated through simulation on the premise that the line width is adjusted to ensure that the impedance is consistent, and the calculation results of the material A and the material C are shown in Table 3.
TABLE 3 impedance and transmission velocity Chart for Material A and Material C
According to the maximum length difference and the transmission speed of the PCBs made of the two materials, the time corresponding to the signal line with the maximum trace length compensated by the material a and the material C is deduced, please refer to table 4.
TABLE 4 Transmission duration corresponding to the signal line with the maximum trace length compensated by Material A and Material C
Wherein, the 131mil is 160.8ps/inch is 21.06ps, and the 131mil is 144.3ps/inch is 18.9 ps.
It can be seen that the transmission durations of the signals on the signal lines with the maximum length difference on the material a and the material C are respectively 21.06ps and 18.9ps, and there is a maximum time difference of the transmission durations of 21.06ps-18.9ps ═ 2.16ps, and this time difference will consume the margins of equal length in the equal length group, that is, the margins of the equal length allowed time delay. In order to enable the PCBs of A, B, C and D4 made of different materials to meet the equal-length design requirement of 5ps in the group, the time difference needs to be considered in advance during design, that is, during the equal-length design, the control rule needs to be tightened as follows: the allowed time delay of the equal length is 5-2.16 ps-2.84 ps, and the requirement of sharing DDR design by multi-grade plates can be met through the reasonable strict management and control rule.
In summary, the DDR internal length of the package and the material characteristics of the PCB need to be investigated at the early stage of DDR design, transmission errors introduced by different grades of materials are evaluated, and management and control rules are reasonably optimized so that different grades of PCBs can share the DDR design. Therefore, the signal line can meet the equal-length design requirements of different materials, and the design difficulty cannot be excessively increased.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an isometric design system for DDR wiring according to the present invention.
The equal length design system comprises:
a maximum length difference determining unit 31 configured to determine a maximum length difference between DDR internal package lengths of signal lines in the same equal length group;
a transmission duration determining unit 32, configured to determine a transmission duration of a signal on a signal line with a length equal to the maximum length difference on PCB boards of different materials;
the equal-length allowable delay adjusting unit 33 is configured to perform difference processing on the time difference between the equal-length allowable delay and the transmission time length, so as to design the length of the signal line based on the obtained difference.
As a preferred embodiment, the maximum length difference value determining unit 31 includes:
the length maximum value determining unit is used for respectively determining the maximum value and the minimum value of the DDR internal encapsulation length of each signal line in the same equal-length group;
and the length difference unit is used for carrying out difference processing on the maximum value and the minimum value of the DDR internal encapsulation length of the signal lines to obtain the maximum length difference value between the DDR internal encapsulation lengths of the signal lines in the same equal length group.
As a preferred embodiment, the transmission time length determination unit 32 is specifically configured to determine the transmission time length of the signal on the signal line having the length equal to the maximum length difference on the PCB boards having different dielectric constants.
As a preferred embodiment, the equal-length allowable delay adjusting unit 33 includes:
the transmission time length maximum value determining unit is used for determining the maximum transmission time length and the minimum transmission time length in the PCBs made of different materials;
the time length difference making unit is used for making difference processing on the maximum transmission time length and the minimum transmission time length in the PCBs made of different materials to obtain the maximum time difference of the transmission time lengths;
and the equal-length allowed time delay difference making unit is used for making difference processing on the maximum time difference between the equal-length allowed time delay and the transmission time length.
For the introduction of the system with equal length design for DDR wiring according to the present invention, please refer to the above method embodiment, which is not described herein again.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an isometric design apparatus for DDR wiring according to the present invention.
The equal length design device comprises:
a memory 41 for storing a computer program;
and the processor 42 is used for implementing the steps of the equal-length design method of the DDR wiring when executing the computer program.
For the introduction of the equal-length design apparatus for DDR wiring provided by the present invention, please refer to the above method embodiment, and the present invention is not described herein again.
The invention also provides a computer readable storage medium, on which a computer program is stored, and when being executed by a processor, the computer program realizes the steps of the equal-length design method for DDR wiring.
For the introduction of a computer-readable storage medium provided by the present invention, please refer to the above method embodiments, which are not repeated herein.
It should be noted that, in the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An isometric design method for DDR wiring is characterized by comprising the following steps:
determining the maximum length difference value between the DDR internal encapsulation lengths of the signal lines in the same equal length group;
determining the transmission time length of the signal on the signal line with the length equal to the maximum length difference on the PCB made of different materials;
and carrying out difference processing on the time difference between the equal-length allowable time delay and the transmission time length so as to design the length of the signal line based on the obtained difference value.
2. The method for isometric design of DDR wiring of claim 1 wherein determining the maximum difference between DDR internal package lengths for signal lines within the same isometric group comprises:
respectively determining the maximum value and the minimum value of the DDR internal encapsulation length of each signal line in the same equal-length group;
and performing difference processing on the maximum value and the minimum value of the DDR internal encapsulation lengths of the signal lines to obtain the maximum length difference value between the DDR internal encapsulation lengths of the signal lines in the same equal-length group.
3. The method for isometric design of DDR wiring of claim 1, wherein determining the transmission duration of the signal on the signal line with the length equal to the maximum length difference on the PCBs of different materials comprises:
and determining the transmission time length of the signal on the signal line with the length equal to the maximum length difference on the PCB with different dielectric constants.
4. The method for isometric design of DDR wiring according to any one of claims 1 to 3, wherein the step of differencing the time difference between the isometric allowable delay and the transmission duration comprises:
determining the maximum transmission time and the minimum transmission time in PCBs made of different materials;
carrying out difference processing on the maximum transmission time length and the minimum transmission time length in the PCBs made of different materials to obtain the maximum time difference of the transmission time lengths;
and carrying out difference processing on the maximum time difference between the equal-length allowed time delay and the transmission time length.
5. An isometric design system for DDR wiring, comprising:
the maximum length difference determining unit is used for determining the maximum length difference between the DDR internal packaging lengths of the signal lines in the same equal length group;
the transmission duration determining unit is used for determining the transmission duration of the signals on the signal lines with the length equal to the maximum length difference on the PCB made of different materials;
and the equal-length allowable delay adjusting unit is used for carrying out difference processing on the time difference between the equal-length allowable delay and the transmission time length so as to design the length of the signal line based on the obtained difference value.
6. The isometric design system of DDR wiring of claim 5, wherein the maximum length difference determination unit includes:
the length maximum value determining unit is used for respectively determining the maximum value and the minimum value of the DDR internal encapsulation length of each signal line in the same equal-length group;
and the length difference unit is used for carrying out difference processing on the maximum value and the minimum value of the DDR internal encapsulation lengths of the signal lines to obtain the maximum length difference value between the DDR internal encapsulation lengths of the signal lines in the same equal length group.
7. The isometric design system for DDR wiring of claim 5, wherein the transmission time length determination unit is specifically configured to determine the transmission time length of the signal on the signal line with the length equal to the maximum length difference on the PCB boards with different dielectric constants.
8. The isometric design system of DDR wiring of any one of claims 5 to 7 wherein the isometric delay tolerant adjustment unit comprises:
the transmission time length maximum value determining unit is used for determining the maximum transmission time length and the minimum transmission time length in the PCBs made of different materials;
the time length difference making unit is used for making difference processing on the maximum transmission time length and the minimum transmission time length in the PCBs made of different materials to obtain the maximum time difference of the transmission time lengths;
and the equal-length allowed time delay difference making unit is used for making difference processing on the maximum time difference between the equal-length allowed time delay and the transmission time length.
9. An equal-length design device for DDR wiring is characterized by comprising:
a memory for storing a computer program;
a processor for implementing the steps of the method for isometric design of DDR wiring according to any one of claims 1 to 4 when executing said computer program.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, implements the steps of the isometric design method for DDR wiring according to any one of claims 1 to 4.
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