CN105930601A - DDR (Double Data Rate) time sequence and delay skew simulation evaluation method based on lookup table - Google Patents
DDR (Double Data Rate) time sequence and delay skew simulation evaluation method based on lookup table Download PDFInfo
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- G06F30/00—Computer-aided design [CAD]
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- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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Abstract
The invention discloses a DDR (Double Data Rate) time sequence and delay skew simulation evaluation method based on a lookup table. The time sequence simulation evaluation method comprises the following steps: step 1), performing time sequence simulation in advance on signal lines of various signal transmission component types and delay physical property types, and obtaining a unit length delay lookup table of the signal lines; step 2), dividing signal lines of signals to be analyzed into signal line sub segments, and determining the delay physical property type and line length of each signal line sub segment; step 3), obtaining the signal delay of each signal line sub segment by the lookup table; and step 4), summarizing the delays of various signal line sub segments and obtaining a total delay of the signals to be analyzed; the delay skew simulation evaluation method subtracts the total delay of two signals to be analyzed and calculates the delay skews of the two signals to be analyzed. The DDR time sequence and delay skew simulation evaluation method based on the lookup table provided by the invention can simply and quickly perform simulation evaluation on the DDR signal delay and skew, and provide fast and accurate time sequence evaluation and design reference for the DDR signal design in view of the influences of different signal transmission components and delay physical properties.
Description
Technical field
The present invention relates to DDR time stimulatiom technology, be specifically related to a kind of DDR sequential based on look-up table and time delay deflection Simulation Evaluation method.
Background technology
Along with the development of microelectric technique, the performance of microprocessor is more and more higher.In order to improve memory bandwidth, reduce the performance gap between processor and memorizer, Double Data Rate synchronous DRAM (Double Data Rate
Synchronous Dynamic Random Access Memory, DDR SDRAM) it is widely used in the rambus design of electronic communication system.As typical parallel bus structure, DDR technology improves memory access speed and bandwidth, meets the demand of high speed data transfer.But, the continuous renewal of DDR technology is regenerated so that the sequence problem in system design becomes to highlight all the more, not only system design is proposed stern challenge, even becomes and limit the bottleneck that DDR transfer rate improves further.
In order to the sequential of DDR design in electronic product is estimated, need after design completes, carry out DDR time stimulatiom, to confirm whether it meets the general timing requirements of specification regulation and the special timing requirements of DDR controller producer proposition.According to the most general simulation flow, firstly the need of extracting chip package and printed circuit board (PCB) (Printed Circuit Board, PCB) the DDR signal transmission line model on, then the driver model of DDR signal, transmission line model, adapter model and receptor model are coupled together according to corresponding topological structure, input certain pumping signal from drive side afterwards and solve, the time delay of the measuring receiver termination collection of letters number after completing.This emulation mode is closest to practical situation, and precision is the highest, but the most loaded down with trivial details, and on chip package and PCB, transmission line model extracts, topological structure connects and time stimulatiom solves and will take considerable time.Particularly when the model of emulation is complicated, signal is more, no matter it is that transmission line model extracts, topological structure connects or time stimulatiom solves required workload and the time is the most in exponential increase, possibly even up to a couple of days or several weeks, long emulation progress reduces the meaning of emulation.
The method calculated by line length is carried out the method for DDR sequential assessment and there is bigger error.This is due to the fact that: first, the speed that signal is propagated in transmission line, not only relevant to length, also relevant to the material behavior of medium and conductor.The dielectric constant of medium and fissipation factor, the electrical conductivity of conductor and surface roughness etc. all can affect signal velocity.Secondly, the spread speed of signal is also had an impact by the geometric properties of transmission line and medium, such as the thickness of medium, the wiring configuration (single-ended, difference) etc. of transmission line.If neglecting these factors, simply by line length computation delay, it is impossible to obtain accurate result.The particularly signal to high transfer rate, bigger error may cause the assessment result of mistake.
In sum, DDR time stimulatiom needs to realize claimed below: one, simple and quick, it is possible to obtain simulation result in the short period of time；Two, there is certain precision, it is possible to reflect the impact of different condition and factor.Existing method cannot realize above-mentioned both sides demand simultaneously.
Summary of the invention
The technical problem to be solved in the present invention: for the problems referred to above of prior art, there is provided a kind of and DDR signal time delay and deflection to including on chip package and PCB can carry out Simulation Evaluation quickly and easily, simultaneously it can be considered that unlike signal transmission part and the impact on signal sequence of the time delay physical characteristic, in order to provide sequential assessment fast and accurately and the DDR sequential based on look-up table of design reference and time delay deflection Simulation Evaluation method to DDR signal design.
In order to solve above-mentioned technical problem, the technical solution used in the present invention is:
The present invention provides a kind of DDR time stimulatiom appraisal procedure based on look-up table, and step includes:
1) holding wire for various signal transmission component types carries out time stimulatiom in advance, obtain the holding wire unit length time delay look-up table of various signal transmission component type, the corresponding relation between signal transmission component type correspondence time delay physical characteristic type that the list item of described holding wire unit length time delay look-up table includes specifying, unit length cabling time delay；
2) holding wire being analysed to signal is holding wire subsegment according to signal transmission component Type division, determines time delay physical characteristic type and the line length of each holding wire subsegment；
3) according to time delay physical characteristic type and the line length of each holding wire subsegment, compare described holding wire unit length time delay look-up table, obtain the signal lag of each holding wire subsegment；
4) carry out suing for peace by the time delay of each holding wire subsegment and obtain total time delay of signal to be analyzed.
Preferably, when in described step 1), holding wire for various signal transmission component types carries out time stimulatiom, for signal transmission component type include chip package base plate, PCB main board card and DIMM daughter card.
Preferably, described signal transmission component type also includes the middle board on adapter, chip soldered ball, signal transmission path between PCB main board card and DIMM daughter card.
Preferably, when in described step 1), holding wire for various signal transmission component types carries out time stimulatiom, various time delay physical characteristic types for each signal transmission component type carry out time stimulatiom respectively, each signal transmission component type at least one list item corresponding in described holding wire unit length time delay look-up table, and each list item include specifying signal transmission component type correspondence time delay physical characteristic type, corresponding relation between unit length cabling time delay.
Preferably, described time delay physical characteristic type include holding wire be top layer microstrip line, holding wire be two kinds of cabling types of internal layer strip line.
Preferably, described time delay physical characteristic type also includes dielectric material or the conductor material type that holding wire uses.
Preferably, described time delay physical characteristic type also includes physical dimension type and the surface roughness type of holding wire.
Preferably, described physical dimension type refers to the thickness type of holding wire medium or conductor.
Preferably, the detailed step of described step 3) includes:
3.1) according to the time delay physical characteristic type Control holding wire unit length time delay look-up table of each holding wire subsegment, the unit length time delay of each holding wire subsegment is determined；
3.2) signal lag of each holding wire subsegment is calculated according to function expression shown in formula (1)；
DelayAi=LengthAi·DAi
(1)
In formula (1),DelayAiRepresent signal to be analyzediThe signal lag of individual holding wire subsegment,LengthAiRepresent signal to be analyzediThe line length of individual holding wire subsegment,DAiRepresent signal to be analyzediThe unit length time delay of individual holding wire subsegment.
The present invention also provides for a kind of DDR sequential time delay deflection Simulation Evaluation method based on look-up table, and step includes:
I) use aforementioned DDR time stimulatiom appraisal procedure based on look-up table, obtain total time delay of two-way signal to be analyzed respectively；
II) total time delay of signal to be analyzed for two-way is subtracted each other, obtain the time delay deflection between two-way signal to be analyzed.
Present invention DDR based on look-up table time stimulatiom appraisal procedure has an advantage that unlike signal transmission part and time delay physical characteristic type can be emulated before formal Simulation Evaluation starts by the present invention, and completes the relevant information in holding wire unit length time delay look-up table；When Simulation Evaluation starts, only the time delay physical characteristic type of each signal transmission component of signal to be analyzed and line length need to be added up, control signal line unit length time delay look-up table obtains data, simply calculates and i.e. can get corresponding signal lag and time delay skew results.Need to carry out model extraction with general emulation, topology is built, sequential solves and compared with the whole process of Time delay measurement, substantially increases simulation efficiency, shortens progress and the complexity of emulation；Compared with the appraisal procedure only calculated by line length, not only allowing for the line length impact on time delay, also contemplate medium and the material of conductor and geometrical property simultaneously, therefore results contrast is accurate, also bigger error will not be caused, it is ensured that the precision of Simulation Evaluation for higher signal transmission rate.Present invention incorporates general Whole Process Simulation and the advantage of line length calculating appraisal procedure, simulation velocity and precision are compromised.Additionally, due to the result of look-up table only need to once emulate, so that it may be used for multiple times, be highly convenient for iteration optimization.
Present invention DDR based on look-up table sequential time delay deflection Simulation Evaluation method is the application in signal calculated time delay and two paths of signals time delay deflection of present invention DDR based on the look-up table time stimulatiom appraisal procedure, it comprises whole technological means of present invention DDR based on look-up table time stimulatiom appraisal procedure, the most also there is the aforementioned advantages of present invention DDR based on look-up table time stimulatiom appraisal procedure, therefore do not repeat them here.
Accompanying drawing explanation
Fig. 1 is the basic procedure schematic diagram of the embodiment of the present invention one method.
Fig. 2 is the cabling schematic diagram of signal to be analyzed in the embodiment of the present invention one.
Fig. 3 is the form schematic diagram of holding wire unit length time delay look-up table in the embodiment of the present invention one.
Fig. 4 is the line length form schematic diagram of each holding wire subsegment determined in the embodiment of the present invention one.
Detailed description of the invention
Embodiment one:
As it is shown in figure 1, the step of the present embodiment DDR based on look-up table time stimulatiom appraisal procedure includes:
1) holding wire for various signal transmission component types carries out time stimulatiom in advance, obtain the holding wire unit length time delay look-up table of various signal transmission component type, the corresponding relation between signal transmission component type correspondence time delay physical characteristic type that the list item of described holding wire unit length time delay look-up table includes specifying, unit length cabling time delay；
2) holding wire being analysed to signal is holding wire subsegment according to signal transmission component Type division, determines time delay physical characteristic type and the line length of each holding wire subsegment；
3) according to time delay physical characteristic type and the line length of each holding wire subsegment, compare described holding wire unit length time delay look-up table, obtain the signal lag of each holding wire subsegment；
4) carry out suing for peace by the time delay of each holding wire subsegment and obtain total time delay of signal to be analyzed.
In the present embodiment, when in step 1), holding wire for various signal transmission component types carries out time stimulatiom, for signal transmission component type include chip package base plate, PCB main board card and DIMM daughter card.1., chip package base plate seeing Fig. 2, for the holding wire B of a certain road signal on DDR storage chip A, its cabling includes three kinds of signal transmission component types:；2., PCB main board card；3., DIMM daughter card.It should be noted that, due to design, the reason of each side such as manufacturing process, the holding wire of chip package base plate, the holding wire of PCB main board card, medium and conductor material behavior that the holding wire three of DIMM daughter card is used are the most different, but certainly, even if aforementioned three kinds of holding wires can also use two kinds of even same medium and conductor materials as required, it is readily adaptable for use in the present embodiment DDR based on look-up table time stimulatiom appraisal procedure equally, simply the classification quantity of signal transmission component type may be otherwise varied, and then cause the signal transmission component type in holding wire unit length time delay look-up table to reduce, but its ultimate principle is essentially identical with the present embodiment, therefore do not repeat them here.Additionally, the present embodiment uses 3 D electromagnetic field solver (such as HFSS, 3D-FEM etc.) carry out time stimulatiom.
In the present embodiment, when in step 1), holding wire for various signal transmission component types carries out time stimulatiom, for signal transmission component type also include adapter and chip soldered ball, in addition to chip package base plate, PCB main board card, DIMM daughter card, three kinds of different signal transmission components of middle board between PCB main board card and DIMM daughter card on adapter, chip soldered ball, signal transmission path are also considered, intactly to consider the transmission details of DDR clock signal, so that it is guaranteed that the accuracy of DDR time stimulatiom assessment.It should be noted that, on adapter, chip soldered ball, signal transmission path, the middle board these three signal transmission component between PCB main board card and DIMM daughter card is not the option that must select, such as during calculating two paths of signals time delay deflection, the delay factor of above-mentioned three kinds of signal transmission components can be cancelled out each other, result is not produced impact, such that it is able to do not consider adapter and the impact on signal lag of the two kinds of signal transmission components of chip soldered ball.
In the present embodiment, when in step 1), holding wire for various signal transmission component types carries out time stimulatiom, various time delay physical characteristic types for each signal transmission component type carry out time stimulatiom respectively, each signal transmission component type at least one list item corresponding in described holding wire unit length time delay look-up table, and each list item include specifying signal transmission component type correspondence time delay physical characteristic type, corresponding relation between unit length cabling time delay.Certainly, time delay physical characteristic classification of type is the most detailed, then the time stimulatiom for this signal will be the most accurate, follow-up when control signal line unit length time delay look-up table, it is possible to obtain more accurate delay product.
In the present embodiment, time delay physical characteristic type include holding wire be top layer microstrip line, holding wire be two kinds of cabling types of internal layer strip line, see Fig. 3, each signal transmission component correspondence holding wire is that top layer microstrip line (being simply expressed as " microstrip line " in Fig. 3), internal layer strip line (being simply expressed as " strip line " in Fig. 3) have a project, and the unit of project data is ps/mm.It should be noted that, for the purpose of simplifying the description, only listing chip package base plate, PCB main board card and three kinds of type of dielectric material of DIMM daughter card in Fig. 3 to illustrate, in the case of expressing completely, holding wire unit length time delay look-up table should also include adapter, chip soldered ball two row.It should be noted that, for the purpose of simplifying the description, Fig. 3 only lists holding wire be top layer microstrip line, holding wire be two kinds of time delay physical characteristic types of internal layer strip line, in the case of expressing completely, holding wire unit length time delay look-up table should also include the row using the holding wire of other dielectric material, conductor material or physical dimension.
In the present embodiment, time delay physical characteristic type also includes physical dimension type of dielectric material that holding wire uses or conductor material type, holding wire etc. and surface roughness type.In the present embodiment, physical dimension type refers to the thickness type of holding wire medium or conductor.Seeing Fig. 3 and Fig. 4, dielectric material or conductor material type and be divided into again low loss dielectric, middle lossy medium and high lossy medium, surface roughness type includes low roughness, middle roughness and high roughness.It should be noted that can be separate between above-mentioned different type, it is also possible to be to be mutually combined, it specifically can be different owing to the manufacturing process of the signal transmission component type of required consideration is different.Such as in the present embodiment, chip package base plate at least includes microstrip line, strip line, three kinds of time delay physical characteristic types of low loss dielectric strip line, and PCB main board card at least includes microstrip line, low roughness microstrip line, three kinds of time delay physical characteristic types of strip line.
Step 2 in the present embodiment) determine the line length of each holding wire subsegment after, form shown in Fig. 4 can be obtained, each project represents the line length that under a certain signal transmission component type, a certain time delay physical characteristic type is corresponding, and unit is mm.It should be noted that the form of Fig. 4 is the most in simplified form, eliminate the row of the holding wire using other dielectric material, conductor material or physical dimension.
In the present embodiment, the detailed step of step 3) includes:
3.1) according to the type of wiring control signal line unit length time delay look-up table of each holding wire subsegment, the unit length time delay of each holding wire subsegment is determined；
3.2) signal lag of each holding wire subsegment is calculated according to function expression shown in formula (1)；
DelayAi=LengthAi·DAi
(1)
In formula (1),DelayAiRepresent signal to be analyzediThe signal lag of individual holding wire subsegment,LengthAiRepresent signal to be analyzediThe line length of individual holding wire subsegment,DAiRepresent signal to be analyzediThe unit length time delay of individual holding wire subsegment.
The present embodiment step 1) carries out before assessment starts and completes, and is not counted in assessment progress, assessment progress is not produced impact such that it is able to be greatly enhanced the efficiency of DDR sequential assessment.And when carrying out the assessment of DDR sequential, the present embodiment uses the method for holding wire unit length time delay look-up table, can only analyze type of wiring and the i.e. available more accurate simulation result of line length, replace conventional DDR signal time stimulatiom to need to carry out loaded down with trivial details setting every time, solve the problem that conventional simulation efficiency is low, as one quick DDR signal time stimulatiom method, can be widely applied to EDA field.
Embodiment two:
Different from embodiment one, the present embodiment is on the basis of embodiment one, further by based on look-up table for embodiment one DDR time stimulatiom appraisal procedure in the application calculated in two paths of signals time delay deflection.
The present embodiment DDR based on look-up table sequential time delay deflection Simulation Evaluation method, step includes: I) use the aforementioned DDR time stimulatiom appraisal procedure based on look-up table of the present invention, obtain total time delay of two-way signal to be analyzed respectively；II) total time delay of signal to be analyzed for two-way is subtracted each other, obtain the time delay deflection between two-way signal to be analyzed (unit is ps).
In addition, in the present embodiment method, do not consider on adapter, chip soldered ball, signal transmission path the impact on signal lag of the three kinds of signal transmission components of middle board between PCB main board card and DIMM daughter card, this is because in time delay deflection between signal calculated, these factors can be cancelled out each other, and result is not produced impact.
The above is only the preferred embodiment of the present invention, and protection scope of the present invention is not limited merely to above-described embodiment, and all technical schemes belonged under thinking of the present invention belong to protection scope of the present invention.It should be pointed out that, for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, these improvements and modifications also should be regarded as protection scope of the present invention.
Claims (10)
1. a DDR time stimulatiom appraisal procedure based on look-up table, it is characterised in that step includes:
1) holding wire for various signal transmission component types carries out time stimulatiom in advance, obtain the holding wire unit length time delay look-up table of various signal transmission component type, the corresponding relation between signal transmission component type correspondence time delay physical characteristic type that the list item of described holding wire unit length time delay look-up table includes specifying, unit length cabling time delay；
2) holding wire being analysed to signal is holding wire subsegment according to signal transmission component Type division, determines time delay physical characteristic type and the line length of each holding wire subsegment；
3) according to time delay physical characteristic type and the line length of each holding wire subsegment, compare described holding wire unit length time delay look-up table, obtain the signal lag of each holding wire subsegment；
4) carry out suing for peace by the time delay of each holding wire subsegment and obtain total time delay of signal to be analyzed.
DDR time stimulatiom appraisal procedure based on look-up table the most according to claim 1, it is characterized in that, when in described step 1), holding wire for various signal transmission component types carries out time stimulatiom, for signal transmission component type include chip package base plate, PCB main board card and DIMM daughter card.
DDR time stimulatiom appraisal procedure based on look-up table the most according to claim 2, it is characterized in that, described signal transmission component type also includes the middle board on adapter, chip soldered ball, signal transmission path between PCB main board card and DIMM daughter card.
DDR time stimulatiom appraisal procedure based on look-up table the most according to claim 3, it is characterized in that, when in described step 1), holding wire for various signal transmission component types carries out time stimulatiom, various time delay physical characteristic types for each signal transmission component type carry out time stimulatiom respectively, each signal transmission component type at least one list item corresponding in described holding wire unit length time delay look-up table, and each list item includes the signal transmission component type correspondence time delay physical characteristic type specified, corresponding relation between unit length cabling time delay.
DDR time stimulatiom appraisal procedure based on look-up table the most according to claim 4, it is characterised in that described time delay physical characteristic type include holding wire be top layer microstrip line, holding wire be two kinds of cabling types of internal layer strip line.
DDR time stimulatiom appraisal procedure based on look-up table the most according to claim 5, it is characterised in that described time delay physical characteristic type also includes dielectric material or the conductor material type that holding wire uses.
DDR time stimulatiom appraisal procedure based on look-up table the most according to claim 6, it is characterised in that described time delay physical characteristic type also includes physical dimension type and the surface roughness type of holding wire.
DDR time stimulatiom appraisal procedure based on look-up table the most according to claim 7, it is characterised in that described physical dimension type refers to the thickness type of holding wire medium or conductor.
9. according to the DDR time stimulatiom appraisal procedure based on look-up table described in any one in claim 1～8, it is characterised in that the detailed step of described step 3) includes:
3.1) according to the time delay physical characteristic type Control holding wire unit length time delay look-up table of each holding wire subsegment, the unit length time delay of each holding wire subsegment is determined；
3.2) signal lag of each holding wire subsegment is calculated according to function expression shown in formula (1)；
DelayAi=LengthAi·DAi
(1)
In formula (1),DelayAiRepresent signal to be analyzediThe signal lag of individual holding wire subsegment,LengthAiRepresent signal to be analyzediThe line length of individual holding wire subsegment,DAiRepresent signal to be analyzediThe unit length time delay of individual holding wire subsegment.
10. a DDR sequential time delay deflection Simulation Evaluation method based on look-up table, it is characterised in that step includes:
I) use the DDR time stimulatiom appraisal procedure based on look-up table described in any one in claim 1～9, obtain total time delay of two-way signal to be analyzed respectively；
II) total time delay of signal to be analyzed for two-way is subtracted each other, obtain the time delay deflection between two-way signal to be analyzed.
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| CN112989753A (en) * | 2021-01-28 | 2021-06-18 | 深圳市一博科技股份有限公司 | Packaging model for improving DDR simulation precision and modeling method thereof |
| CN112989753B (en) * | 2021-01-28 | 2024-05-03 | 深圳市一博科技股份有限公司 | Packaging model for improving DDR simulation precision and modeling method thereof |
| CN114915568A (en) * | 2021-02-09 | 2022-08-16 | 大唐移动通信设备有限公司 | Method and device for determining performance of signal transmission line and storage medium |
| CN114915568B (en) * | 2021-02-09 | 2024-04-09 | 大唐移动通信设备有限公司 | Method and device for determining performance of signal transmission line and storage medium |
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