CN103257309B - Ddr series pcb plate timing compensation method, system and terminal - Google Patents
Ddr series pcb plate timing compensation method, system and terminal Download PDFInfo
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- CN103257309B CN103257309B CN201210037806.9A CN201210037806A CN103257309B CN 103257309 B CN103257309 B CN 103257309B CN 201210037806 A CN201210037806 A CN 201210037806A CN 103257309 B CN103257309 B CN 103257309B
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Abstract
The present invention is applicable to signal transacting field, provides a kind of ddr series pcb plate timing compensation method, system and terminal.Described method comprises step: the timing skew time testing out the synchronizing signal of the fabric swatch design of pcb plate; Test out the timing skew time of synchronizing signal on actual pcb plate; According to the timing skew time of the synchronizing signal that the fabric swatch of the timing skew pcb time calibration plate of synchronizing signal on actual pcb plate designs; In conjunction with the timing skew time of synchronizing signal on the delay time of the single delay circuit of actual measurement and actual pcb plate, determine the minimum single delay circuit number of the main control end that need arrange; In conjunction with timing skew time of synchronizing signal of the fabric swatch design of the pcb plate after the minimum single delay circuit number of main control end and calibration, the delay circuit of main control end is set.The embodiment of the present invention can effectively reduce because of the nonsynchronous probability of Signal transmissions on the data line caused by the difference of pcb plate wiring.
Description
Technical field
The invention belongs to signal transacting field, particularly relate to ddr series pcb plate timing compensation method, system and terminal.
Background technology
Along with the development of embedded electronic product, present multimedia processor can run very high dominant frequency, to meet the growing application demand of operating system, such as run the various application demands that storer arm-context a9 that dominant frequency reaches 1.2Ghz can realize intelligent operating system, meet the needs of present embedded intelligence operating system.
But, in order to the demand of the large internal memory and low cost that meet operating system simultaneously, existing market generally selects Double Data Rate synchronous DRAM (Double Data Rate SDRAM, ddr), these speed of ddr2 and ddr3 are fast, capacity is large and cost is low storer as the internal memory of system.But these storer factor data transmission speeds are than very fast, to the quality of signal and timing requirements higher, and traditional chip design, consider seldom to the sequential of chip exterior, especially at high speeds, along with the dominant frequency of system constantly improves, the increase of power consumption, various impact can be brought to signal in the integrality etc. of electromagnetic interference (EMI) and signal, if directly use chip, do not process the signal on chip, then the signal on data line easily occurs transmitting nonsynchronous phenomenon, and then causes the data acquisition of terminal to go wrong.Such as, if printed circuit board (PCB) (PrintedCircuit Board, pcb) wiring has problem, can not meet at a high speed, the applied environment of high request and application conditions, will affect the sequential of chip exterior, thus cause the transmission of the signal on data line on pcb plate asynchronous.
Summary of the invention
Embodiments provide a kind of ddr series pcb plate timing compensation method, be intended to solve existing operating system when the internal memory selecting capacity is large and cost is low storer as system, the nonsynchronous problem of the Signal transmissions on the data line caused.
The embodiment of the present invention is achieved in that ddr series pcb plate timing compensation method, and described method comprises the steps:
The fabric swatch design of pcb plate is emulated, to test out the timing skew time of the synchronizing signal of the fabric swatch design of described pcb plate;
The actual pcb plate corresponding to the fabric swatch design of described pcb plate is tested, to test out the timing skew time of synchronizing signal on described actual pcb plate;
The timing skew time of the synchronizing signal of the fabric swatch design of pcb plate according to timing skew time calibration of synchronizing signal on described actual pcb plate;
In conjunction with the timing skew time of synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and described actual pcb plate, determine the minimum single time delay circuit unit number that the main control end that need arrange compensates;
In conjunction with timing skew time of synchronizing signal of the fabric swatch design of the described pcb plate after the delay unit time span of the single delay circuit of main control end and calibration, the compensation delay circuit unit number arranging main control end reaches synchronous with the synchronizing signal making the fabric swatch of the described pcb plate after calibration and design.
Another object of the embodiment of the present invention is to provide a kind of ddr series pcb plate timing compensation system, and described system comprises:
Simulate signal timing skew time measuring unit, for emulating the fabric swatch design of pcb plate, to test out the timing skew time of the synchronizing signal of the fabric swatch design of described pcb plate;
Actual signal timing skew time measuring unit, the actual pcb plate corresponding for the fabric swatch design to described pcb plate is tested, to test out the timing skew time of synchronizing signal on described actual pcb plate;
Simulate signal timing skew unit time calibration, for the timing skew time of the synchronizing signal of the fabric swatch design of pcb plate according to timing skew time calibration of synchronizing signal on described actual pcb plate;
Single delay circuit number determining unit, the timing skew time of synchronizing signal on the delay unit time and described actual pcb plate of the single delay circuit of main control end in conjunction with actual measurement, determine the minimum single time delay circuit unit number that the main control end that need arrange compensates;
Delay circuit setting unit, for timing skew time of synchronizing signal of the fabric swatch design of the described pcb plate after the delay unit time span of the single delay circuit in conjunction with main control end and calibration, the compensation delay circuit unit number arranging main control end reaches synchronous with the synchronizing signal making the fabric swatch of the described pcb plate after calibration and design.
Another object of the embodiment of the present invention is to provide a kind of ddr series pcb plate timing compensation terminal, and described terminal comprises above-mentioned ddr series pcb plate timing compensation system.
The embodiment of the present invention can effectively reduce because of the nonsynchronous probability of Signal transmissions on the data line caused by the difference of pcb plate wiring, and then the probability of data collection problems appears in reduction terminal.
Accompanying drawing explanation
Fig. 1 is the ddr series pcb plate timing compensation method flow that first embodiment of the invention provides;
Fig. 2 is the delay circuit schematic diagram of the main control end that first embodiment of the invention provides;
Fig. 3 is the ddr series pcb plate timing compensation system construction drawing that second embodiment of the invention provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
In the embodiment of the present invention, it is the time identical with the timing skew time of the synchronizing signal of actual pcb plate by timing skew time calibration of the synchronizing signal of emulation pcb plate, again in conjunction with multiple independently delay circuit, the timing skew time of the synchronizing signal of the synchronous emulation pcb plate through calibration, to obtain the synchronizing signal that there is not the timing skew time.
Embodiments provide one: ddr series pcb plate timing compensation method, system and terminal.
Described method comprises: emulate the fabric swatch design of pcb plate, to test out the timing skew time of the synchronizing signal of the fabric swatch design of described pcb plate;
The actual pcb plate corresponding to the fabric swatch design of described pcb plate is tested, to test out the timing skew time of synchronizing signal on described actual pcb plate;
The timing skew time of the synchronizing signal of the fabric swatch design of pcb plate according to timing skew time calibration of synchronizing signal on described actual pcb plate;
In conjunction with the timing skew time of synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and described actual pcb plate, determine the minimum single time delay circuit unit number that the main control end that need arrange compensates;
In conjunction with timing skew time of synchronizing signal of the fabric swatch design of the described pcb plate after the delay unit time span of the single delay circuit of main control end and calibration, the compensation delay circuit unit number arranging main control end reaches synchronous with the synchronizing signal making the fabric swatch of the described pcb plate after calibration and design.
Described system comprises: simulate signal timing skew time measuring unit, for emulating the fabric swatch design of pcb plate, to test out the timing skew time of the synchronizing signal of the fabric swatch design of described pcb plate;
Actual signal timing skew time measuring unit, the actual pcb plate corresponding for the fabric swatch design to described pcb plate is tested, to test out the timing skew time of synchronizing signal on described actual pcb plate;
Simulate signal timing skew unit time calibration, for the timing skew time of the synchronizing signal of the fabric swatch design of pcb plate according to timing skew time calibration of synchronizing signal on described actual pcb plate;
Single delay circuit number determining unit, the timing skew time of synchronizing signal on the delay unit time and described actual pcb plate of the single delay circuit of main control end in conjunction with actual measurement, determine the minimum single time delay circuit unit number that the main control end that need arrange compensates;
Delay circuit setting unit, for timing skew time of synchronizing signal of the fabric swatch design of the described pcb plate after the delay unit time span of the single delay circuit in conjunction with main control end and calibration, the compensation delay circuit unit number arranging main control end reaches synchronous with the synchronizing signal making the fabric swatch of the described pcb plate after calibration and design.
Described terminal comprises: the terminal of above-mentioned ddr series pcb plate timing compensation system.
The embodiment of the present invention can effectively reduce because of the nonsynchronous probability of Signal transmissions on the data line caused by the difference of pcb plate wiring, and then the probability of data collection problems appears in reduction terminal.
In order to technical solutions according to the invention are described, be described below by specific embodiment.
embodiment one:
Fig. 1 shows a kind of ddr series pcb plate timing compensation method flow that first embodiment of the invention provides, in the present embodiment, by the timing skew time of the synchronizing signal of the fabric swatch design of calibration pcb plate, and the delay circuit arranging main control end is to reach the sequential compensating ddr series pcb plate, details are as follows:
Step S11, emulates the fabric swatch design of pcb plate, to test out the timing skew time of the synchronizing signal of the fabric swatch design of this pcb plate.
In the present embodiment, after the fabric swatch of pcb plate has designed, by pcb signal simulation instrument subsidiary or special in pcb drawing tools, according to the conditions and environment parameter that application needs, the fabric swatch design of the pcb plate completed is emulated, to test out the timing skew time of the relevant synchronizing signal on this pcb plate.
Step S12, the actual pcb plate corresponding to the fabric swatch design of this pcb plate is tested, to test out the timing skew time of synchronizing signal on this actual pcb plate.
In the present embodiment, actual pcb plate is produced in the fabric swatch design according to the pcb board completed, and uses relevant instrument, the instruments such as such as oscillograph, tests the actual pcb plate produced, to test out the timing skew time of synchronizing signal on this actual pcb plate.
Step S13, according to the timing skew time of the synchronizing signal that the fabric swatch of timing skew this pcb plate time calibration of synchronizing signal on this actual pcb plate designs.
In the present embodiment, when the timing skew time of synchronizing signal corresponding in the timing skew time of certain synchronizing signal on actual pcb plate and the pcb plate of emulation is different, needing timing skew time calibration of the synchronizing signal in the pcb plate of emulation is the time identical with the timing skew time of synchronizing signal corresponding on actual pcb plate, thus both can basis for estimation pcb emulation the timing skew time, with the deviation time proportionate relationship of the pcb plate of time, reference can be provided to the compensation relationship compensating actual pcb plate synchronous transmission of signal time delay again.
Step S14, in conjunction with the delay unit time of the single delay circuit of main control end of actual measurement and the timing skew time of synchronizing signal on this actual pcb plate, determines the minimum single time delay circuit unit number that the main control end that need arrange compensates.
As one embodiment of the present invention, in conjunction with the delay unit time of the single delay circuit of main control end of actual measurement and the timing skew time of synchronizing signal on this actual pcb plate, determine that the step of the minimum single time delay circuit unit number that the main control end that need arrange compensates specifically comprises:
The delay unit time of A1, the single delay circuit of actual measurement.In the present embodiment, main control end delay circuit design in, there is some time delay impact dampers buffer and carry out buffered signal, the circuit at this impact damper buffer place also referred to as time delay circuit unit, the delay unit time span of the single delay circuit of actual measurement.Because of under certain physical condition, the delay time unit of each time delay impact damper buffer is a set time, only need measure the delay unit time of a delay circuit.
A2, obtain maximum timing skew time of synchronizing signal on this actual pcb plate, and by the delay unit time of the maximum timing skew time of synchronizing signal on this actual pcb plate divided by this single delay circuit, gained business is the minimum single time delay circuit unit number that the main control end that need arrange compensates.In the present embodiment, from measure actual pcb plate synchronizing signal the timing skew time in, filter out the maximum timing skew time of synchronizing signal on this actual pcb plate, and by maximum timing skew time of filtering out delay unit time span divided by the single delay circuit measured, to obtain the minimum single time delay circuit unit number that the main control end that need arrange compensates.Such as, suppose that on actual pcb plate, the maximum timing skew time of synchronizing signal is 20ms, the delay unit time of single delay circuit is all 1ms, then the minimum single time delay circuit unit number needing the main control end arranged to compensate is 20.
Step S15, in conjunction with timing skew time of synchronizing signal of the fabric swatch design of this pcb plate after the delay unit time span of the single delay circuit of this main control end and calibration, the compensation delay circuit unit number arranging main control end reaches synchronous with the synchronizing signal making the fabric swatch of the described pcb plate after calibration and design.
As one embodiment of the present invention, in conjunction with timing skew time of synchronizing signal of the fabric swatch design of this pcb plate after the delay unit time span of the single delay circuit of this main control end and calibration, the compensation delay circuit unit number arranging main control end reaches synchronous step with the synchronizing signal making the fabric swatch of the described pcb plate after calibration and design and specifically comprises:
B1, determine the single time delay circuit unit number required for the timing skew time of each synchronizing signal of the fabric swatch design of pcb plate after synchronous calibration.In the present embodiment, because the timing skew time of each synchronizing signal is not necessarily identical, therefore after synchronous calibration, the single time delay circuit unit number required for the timing skew time of each synchronizing signal also may be different.Such as, suppose that the timing skew time of A, B synchronizing signal is through calibration, be respectively 10ms and 4ms, the delay unit time of single delay circuit is all 1ms, then the single time delay circuit unit number required for the timing skew time of synchronous A synchronizing signal is 10, and the single time delay circuit unit number required for the timing skew time of synchronous B synchronizing signal is 4.
B2, minimum single time delay circuit unit number in conjunction with the compensation of this main control end, single delay circuit number required for the timing skew time of each synchronizing signal designed by the fabric swatch of pcb plate after synchronous calibration carries out tandem compound, to obtain the delay circuit of the main control end of the synchronizing signal of the fabric swatch design of the pcb plate after synchronous calibration.
In the present embodiment, the delay circuit of main control end carries out tandem compound by multiple independently time delay circuit unit and determines, and reaches the object of the clock signal of synchronous pcb plate by the time delay sequential of amendment input and output I/O port end.Wherein, an independently time delay circuit unit formation one-level time delay, the time delay circuit unit of 2 series connection form secondary time delays etc.Such as, the minimum single time delay circuit unit number supposing main control end is 3, single time delay circuit unit number required for the timing skew time of synchronous calibrated C, D, E synchronizing signal is respectively 1,2,3, the minimum single time delay circuit unit number of the main control end that then need arrange carries out tandem compound, again synchronizing signal C synchronous for need, D, E are passed through from the delay circuit of appropriate level, with the time difference needed for satisfied compensation, obtain the delay circuit of main control end, concrete schematic diagram as shown in Figure 2.
As one embodiment of the present invention, the timing skew time of the synchronizing signal of the fabric swatch design of this pcb plate after the delay unit time span and calibration of the single delay circuit compensated in conjunction with this main control end, the time delay circuit unit number arranging the compensation of main control end comprises the steps: after reaching synchronous step with the synchronizing signal making the fabric swatch of the described pcb plate after calibration and design further
Timing sequence test is carried out to installing the terminal of this pcb plate, and according to the timing skew of this pcb plate synchronizing signal of test result correction.
In the present embodiment, timing sequence test is carried out to the terminal of having installed through the pcb plate of timing compensation, if still there is timing skew in the synchronizing signal of this pcb plate transmission, then compensate and correct according to the bias contribution situation of reality, avoid the data acquisition causing terminal to go wrong, such as avoid some bit bit data collection to occur mistake.
In the first embodiment of the invention, it is the time identical with the timing skew time of the synchronizing signal of actual pcb plate by timing skew time calibration of the synchronizing signal of emulation pcb plate, again in conjunction with multiple independently time delay circuit unit, the timing skew time of the synchronizing signal of the synchronous emulation pcb plate through calibration, to obtain the synchronizing signal that there is not the timing skew time.Pass through software design patterns, the storer fast to ddr series (ddr, ddr2, ddr3) these speed, capacity is large and cost is low carries out timing compensation, thus effectively reduce because of the nonsynchronous probability of Signal transmissions on the data line caused by the difference of pcb plate wiring, and then there is the probability of data collection problems in reduction terminal.
embodiment two:
Fig. 3 shows the structure of the ddr series pcb plate timing compensation system that second embodiment of the invention provides, and for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention.
This ddr series pcb plate timing compensation system may be used for the various information processing terminals by wired or wireless network connection server, such as mobile phone, pocket computer (Pocket Personal Computer, PPC), palm PC, computing machine, notebook computer, personal digital assistant (Personal Digital Assistant, PDA) etc., can be run on the software unit in these terminals, the unit that hardware cell or software and hardware combine, also can be integrated in these terminals as independently suspension member or run in the application system of these terminals, wherein:
Simulate signal timing skew time measuring unit 31, for emulating the fabric swatch design of pcb plate, to test out the timing skew time of the synchronizing signal of the fabric swatch design of this pcb plate.
In the present embodiment, the emulation tool subsidiary by pcb drawing tools or the emulation tool of specialty, carry out emulation testing, to obtain the timing skew time of the synchronizing signal of the pcb plate of emulation to the fabric swatch design of the pcb plate completed.
Actual signal timing skew time measuring unit 32, the actual pcb plate corresponding for the fabric swatch design to this pcb plate is tested, to test out the timing skew time of synchronizing signal on this actual pcb plate.
Simulate signal timing skew unit time calibration 33, the timing skew time of the synchronizing signal that the fabric swatch for timing skew this pcb plate time calibration according to synchronizing signal on this actual pcb plate designs.
In the present embodiment, the timing skew time of synchronizing signal on the timing skew time of the synchronizing signal of the emulation pcb plate relatively obtained and actual pcb plate, if both are different, then with the timing skew time of the timing skew time of synchronizing signal on actual pcb plate for the synchronizing signal according to calibration emulation pcb plate.
Single delay circuit number determining unit 34, the timing skew time of synchronizing signal on the delay unit time and this actual pcb plate of the single delay circuit of main control end in conjunction with actual measurement, determine the minimum single time delay circuit unit number that the main control end that need arrange compensates.
In the present embodiment, first obtain the maximum timing skew time of all synchronizing signals on actual pcb plate, then determine the minimum single time delay circuit unit number of the main control end that need arrange in conjunction with delay unit time of the single delay circuit of actual measurement.
Delay circuit setting unit 35, for timing skew time of synchronizing signal of the fabric swatch design of this pcb plate after the delay unit time span of the single delay circuit in conjunction with this main control end and calibration, the compensation delay circuit unit number arranging main control end reaches synchronous with the synchronizing signal making the fabric swatch of this pcb plate after calibration and design.
In the present embodiment, by there is the synchronizing signal of the fabric swatch design of the pcb of timing skew after calibration by least one time delay circuit unit, to revise the synchronizing signal that there is timing skew.In the present embodiment, the circuit that synchronously there is the synchronizing signal of the pcb plate of timing skew is the delay circuit of main control end.
As one embodiment of the present invention, this single delay circuit number determining unit 34 comprises: the delay time measurement module 341 of single delay circuit and single delay circuit number acquisition module 342, wherein:
The delay time measurement module 341 of single delay circuit, for the delay unit time of the single delay circuit of actual measurement.
In the present embodiment, when there is the synchronizing signal of timing skew time in adopting buffer as the synchronous pcb plate of delay circuit, the delay unit time of the single delay circuit of actual measurement.
Single delay circuit number acquisition module 342, for obtaining the maximum timing skew time of synchronizing signal on this actual pcb plate, and by the delay unit time of the maximum timing skew time of synchronizing signal on this actual pcb plate divided by this single delay circuit, gained business is the minimum single time delay circuit unit number that the main control end that need arrange compensates.
In the present embodiment, determine the single time delay circuit unit that number is minimum, so that the single time delay circuit unit number that follow-up use is determined is combined into the delay circuit of main control end, improve resource utilization.Wherein, the single delay circuit that delay unit number is minimum was determined divided by the delay unit time of single delay circuit by the maximum timing skew time of synchronizing signal on actual pcb plate.
As one embodiment of the present invention, this delay circuit setting unit 35 comprises: delay circuit number determination module 351 needed for the timing skew time and single delay circuit serial module structure 352, wherein:
Delay circuit number determination module 351 needed for the timing skew time, for determining the single time delay circuit unit number of the timing skew time of each synchronizing signal of the fabric swatch design of pcb plate after synchronous calibration.
In the present embodiment, the single time delay circuit unit number needed for the timing skew time of this synchronizing signal synchronous is determined according to the timing skew time of synchronizing signal, because the timing skew time of each synchronizing signal is not necessarily identical, therefore after synchronous calibration, the single time delay circuit unit number required for the timing skew time of each synchronizing signal also may be different.
Single delay circuit serial module structure 352, for the minimum single time delay circuit unit number of the compensation in conjunction with this main control end, single time delay circuit unit number required for the timing skew time of each synchronizing signal designed by the fabric swatch of pcb plate after this synchronous calibration carries out tandem compound, to obtain the delay circuit of the main control end of the synchronizing signal of the fabric swatch design of the pcb plate after synchronous calibration.
In the present embodiment, the multiple independently delay circuits determined are carried out tandem compound, and by the synchronizing signal of the pcb plate after calibration synchronous for needs by corresponding time delay rank circuit, to obtain the synchronizing signal not having the timing skew time.
As one embodiment of the present invention, this ddr series pcb plate timing compensation system comprises:
Timing skew compensating unit 36, for carrying out timing sequence test to installing the terminal of this pcb plate, and according to timing skew time of this pcb plate synchronizing signal of test result correction.
In the present embodiment, timing sequence test is carried out to the terminal (such as embedded electronic product) of having installed through the pcb plate of timing compensation, if still there is timing skew in the synchronizing signal of this pcb plate transmission, then compensate and correct according to the bias contribution situation of reality, avoid the data acquisition causing terminal to go wrong, such as avoid some bit bit data collection to occur mistake.
In second embodiment of the invention, timing compensation is carried out by the storer fast to ddr series (ddr, ddr2, ddr3) these speed, capacity is large and cost is low, thus effectively reduce because of the nonsynchronous probability of Signal transmissions on the data line caused by the difference of pcb plate wiring, and then there is the probability of data collection problems in reduction terminal.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a ddr series pcb plate timing compensation method, it is characterized in that, described method comprises the steps:
The fabric swatch design of pcb plate is emulated, to test out the timing skew time of the synchronizing signal of the fabric swatch design of described pcb plate;
The actual pcb plate corresponding to the fabric swatch design of described pcb plate is tested, to test out the timing skew time of synchronizing signal on described actual pcb plate; Described actual pcb plate is the pcb plate produced according to the fabric swatch design of described pcb plate;
The timing skew time of the synchronizing signal of the fabric swatch design of pcb plate according to timing skew time calibration of synchronizing signal on described actual pcb plate;
In conjunction with the timing skew time of synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and described actual pcb plate, determine the minimum single time delay circuit unit number that the main control end that need arrange compensates;
In conjunction with timing skew time of synchronizing signal of the fabric swatch design of the described pcb plate after the delay unit time span of the single delay circuit of main control end and calibration, the compensation delay circuit unit number arranging main control end reaches synchronous with the synchronizing signal making the fabric swatch of the described pcb plate after calibration and design.
2. the method for claim 1, it is characterized in that, the timing skew time of synchronizing signal on the delay unit time of the single delay circuit of the described main control end in conjunction with actual measurement and described actual pcb plate, determine that the step of the minimum single time delay circuit unit number that the main control end that need arrange compensates specifically comprises:
The delay unit time of the single delay circuit of actual measurement;
Obtain the maximum timing skew time of synchronizing signal on described actual pcb plate, and by the delay unit time of the maximum timing skew time of synchronizing signal on described actual pcb plate divided by described single delay circuit, gained business is the minimum single time delay circuit unit number that the main control end that need arrange compensates.
3. the method for claim 1, it is characterized in that, the timing skew time of the synchronizing signal of the fabric swatch design of the described pcb plate after the delay unit time span of the described single delay circuit in conjunction with main control end and calibration, the compensation delay circuit unit number arranging main control end reaches synchronous step with the synchronizing signal making the fabric swatch of the described pcb plate after calibration and design and specifically comprises:
The single time delay circuit unit number required for the timing skew time of each synchronizing signal that the fabric swatch of pcb plate designs after determining synchronous calibration;
In conjunction with the minimum single time delay circuit unit number of the compensation of described main control end, single time delay circuit unit number required for the timing skew time of each synchronizing signal designed by the fabric swatch of pcb plate after described synchronous calibration carries out tandem compound, to obtain the delay circuit of the main control end of the synchronizing signal of the fabric swatch design of the pcb plate after synchronous calibration.
4. the method as described in any one of claims 1 to 3, is characterized in that, after the step of the described compensation delay circuit unit number arranging main control end, comprises the steps: further
Carry out timing sequence test to installing the terminal of described pcb plate, and according to test result correction the timing skew of pcb plate synchronizing signal.
5. a ddr series pcb plate timing compensation system, it is characterized in that, described system comprises:
Simulate signal timing skew time measuring unit, for emulating the fabric swatch design of pcb plate, to test out the timing skew time of the synchronizing signal of the fabric swatch design of described pcb plate;
Actual signal timing skew time measuring unit, the actual pcb plate corresponding for the fabric swatch design to described pcb plate is tested, to test out the timing skew time of synchronizing signal on described actual pcb plate; Described actual pcb plate is the pcb plate produced according to the fabric swatch design of described pcb plate;
Simulate signal timing skew unit time calibration, for the timing skew time of the synchronizing signal of the fabric swatch design of pcb plate according to timing skew time calibration of synchronizing signal on described actual pcb plate;
Single delay circuit number determining unit, the timing skew time of synchronizing signal on the delay unit time and described actual pcb plate of the single delay circuit of main control end in conjunction with actual measurement, determine the minimum single time delay circuit unit number that the main control end that need arrange compensates;
Delay circuit setting unit, for timing skew time of synchronizing signal of the fabric swatch design of the described pcb plate after the delay unit time span of the single delay circuit in conjunction with main control end and calibration, the compensation delay circuit unit number arranging main control end reaches synchronous with the synchronizing signal making the fabric swatch of the described pcb plate after calibration and design.
6. system as claimed in claim 5, it is characterized in that, described single delay circuit number determining unit comprises:
The delay time measurement module of single delay circuit, for the delay unit time of the single delay circuit of actual measurement;
Single delay circuit number acquisition module, for obtaining the maximum timing skew time of synchronizing signal on described actual pcb plate, and by the delay unit time of the maximum timing skew time of synchronizing signal on described actual pcb plate divided by described single delay circuit, gained business is the minimum single time delay circuit unit number that the main control end that need arrange compensates.
7. system as claimed in claim 5, it is characterized in that, described delay circuit setting unit comprises:
Delay circuit number determination module needed for the timing skew time, for determining the single time delay circuit unit number of the timing skew time of each synchronizing signal of the fabric swatch design of pcb plate after synchronous calibration;
Single delay circuit serial module structure, for the minimum single time delay circuit unit number of the compensation in conjunction with described main control end, single time delay circuit unit number required for the timing skew time of each synchronizing signal designed by the fabric swatch of pcb plate after described synchronous calibration carries out tandem compound, to obtain the delay circuit of the main control end of the synchronizing signal of the fabric swatch design of the pcb plate after synchronous calibration.
8. the system as described in any one of claim 5 to 7, is characterized in that, described system comprises:
Timing skew compensating unit, for carrying out timing sequence test to installing the terminal of described pcb plate, and according to test result correction timing skew time of pcb plate synchronizing signal.
9. a ddr series pcb plate timing compensation terminal, is characterized in that, described terminal comprises the ddr series pcb plate timing compensation system described in 5 to 8 any one claims.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210037806.9A CN103257309B (en) | 2012-02-17 | 2012-02-17 | Ddr series pcb plate timing compensation method, system and terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210037806.9A CN103257309B (en) | 2012-02-17 | 2012-02-17 | Ddr series pcb plate timing compensation method, system and terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103257309A CN103257309A (en) | 2013-08-21 |
| CN103257309B true CN103257309B (en) | 2015-10-07 |
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| CN103455691A (en) * | 2013-09-25 | 2013-12-18 | 浪潮电子信息产业股份有限公司 | Simplified CCT (channel check tool) pre-simulation method |
| CN106448744B (en) * | 2016-09-22 | 2020-04-03 | 广东威创视讯科技股份有限公司 | DDR timing sequence analysis method, device and system |
| CN107480390B (en) * | 2017-08-23 | 2020-08-21 | 京东方科技集团股份有限公司 | Signal delay compensation method and device and computer equipment |
| CN109800450B (en) * | 2018-12-10 | 2021-06-22 | 中兴通讯股份有限公司 | Method, device and equipment for realizing simplified memory circuit and memory circuit |
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Denomination of invention: Double data rate SDRAM (ddr) series printed circuit board (pcb) timing sequence compensation method, system and terminal Effective date of registration: 20190130 Granted publication date: 20151007 Pledgee: China Co truction Bank Corp Guangzhou economic and Technological Development Zone sub branch Pledgor: Anyka (Guangzhou) Microelectronics Technology Co., Ltd. Registration number: 2019440000051 |
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