CN103257309B - Ddr series pcb plate timing compensation method, system and terminal - Google Patents
Ddr series pcb plate timing compensation method, system and terminal Download PDFInfo
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- CN103257309B CN103257309B CN201210037806.9A CN201210037806A CN103257309B CN 103257309 B CN103257309 B CN 103257309B CN 201210037806 A CN201210037806 A CN 201210037806A CN 103257309 B CN103257309 B CN 103257309B
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- pcb plate
- delay circuit
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- timing skew
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004744 fabric Substances 0.000 claims abstract description 77
- 238000013461 design Methods 0.000 claims abstract description 74
- 238000012360 testing method Methods 0.000 claims abstract description 32
- 238000005259 measurement Methods 0.000 claims abstract description 21
- 230000001360 synchronised effect Effects 0.000 claims description 37
- 150000001875 compounds Chemical class 0.000 claims description 7
- 238000012937 correction Methods 0.000 claims description 4
- 230000008054 signal transmission Effects 0.000 abstract description 7
- 238000013480 data collection Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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CN201210037806.9A CN103257309B (en) | 2012-02-17 | 2012-02-17 | Ddr series pcb plate timing compensation method, system and terminal |
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CN201210037806.9A CN103257309B (en) | 2012-02-17 | 2012-02-17 | Ddr series pcb plate timing compensation method, system and terminal |
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CN103257309A CN103257309A (en) | 2013-08-21 |
CN103257309B true CN103257309B (en) | 2015-10-07 |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN103455691A (en) * | 2013-09-25 | 2013-12-18 | 浪潮电子信息产业股份有限公司 | Simplified CCT (channel check tool) pre-simulation method |
CN106448744B (en) * | 2016-09-22 | 2020-04-03 | 广东威创视讯科技股份有限公司 | DDR timing sequence analysis method, device and system |
CN107480390B (en) * | 2017-08-23 | 2020-08-21 | 京东方科技集团股份有限公司 | Signal delay compensation method and device and computer equipment |
CN109800450B (en) * | 2018-12-10 | 2021-06-22 | 中兴通讯股份有限公司 | Method, device and equipment for realizing simplified memory circuit and memory circuit |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1169000A (en) * | 1996-04-23 | 1997-12-31 | 东芝株式会社 | Time piece synchronism delay control circuit |
CN1337696A (en) * | 2000-06-30 | 2002-02-27 | 惠普公司 | Method and apparatus for calibration of time sequence of write-dowu processing onto storage medium |
CN1393992A (en) * | 2001-07-02 | 2003-01-29 | 朗迅科技公司 | Delay compensating circuit containing feedback loop |
CN1499523A (en) * | 2002-10-30 | 2004-05-26 | ����ʿ�뵼������˾ | Delay locking loop having acceleration mode and controlled by register |
CN101042925A (en) * | 2006-03-21 | 2007-09-26 | 联发科技股份有限公司 | Memory controller, memory device and strobe signal calibration method |
CN101228690A (en) * | 2005-07-29 | 2008-07-23 | 富士通株式会社 | delay adjustment device |
CN101446841A (en) * | 2008-12-01 | 2009-06-03 | 炬才微电子(深圳)有限公司 | Method for confirming memory controller clock calibration value and system thereof |
WO2010151378A1 (en) * | 2009-06-24 | 2010-12-29 | Advanced Micro Devices, Inc. | Adjustment of write timing in a memory device |
WO2011156041A1 (en) * | 2010-06-08 | 2011-12-15 | Rambus Inc. | Integrated circuit device timing calibration |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100510063B1 (en) * | 2002-12-24 | 2005-08-26 | 주식회사 하이닉스반도체 | Register controlled delay locked loop |
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Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1169000A (en) * | 1996-04-23 | 1997-12-31 | 东芝株式会社 | Time piece synchronism delay control circuit |
CN1337696A (en) * | 2000-06-30 | 2002-02-27 | 惠普公司 | Method and apparatus for calibration of time sequence of write-dowu processing onto storage medium |
CN1393992A (en) * | 2001-07-02 | 2003-01-29 | 朗迅科技公司 | Delay compensating circuit containing feedback loop |
CN1499523A (en) * | 2002-10-30 | 2004-05-26 | ����ʿ�뵼������˾ | Delay locking loop having acceleration mode and controlled by register |
CN101228690A (en) * | 2005-07-29 | 2008-07-23 | 富士通株式会社 | delay adjustment device |
CN101042925A (en) * | 2006-03-21 | 2007-09-26 | 联发科技股份有限公司 | Memory controller, memory device and strobe signal calibration method |
CN101446841A (en) * | 2008-12-01 | 2009-06-03 | 炬才微电子(深圳)有限公司 | Method for confirming memory controller clock calibration value and system thereof |
WO2010151378A1 (en) * | 2009-06-24 | 2010-12-29 | Advanced Micro Devices, Inc. | Adjustment of write timing in a memory device |
WO2011156041A1 (en) * | 2010-06-08 | 2011-12-15 | Rambus Inc. | Integrated circuit device timing calibration |
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Denomination of invention: Double data rate SDRAM (ddr) series printed circuit board (pcb) timing sequence compensation method, system and terminal Effective date of registration: 20171102 Granted publication date: 20151007 Pledgee: China Co truction Bank Corp Guangzhou economic and Technological Development Zone sub branch Pledgor: Anyka (Guangzhou) Microelectronics Technology Co., Ltd. Registration number: 2017990001008 |
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Date of cancellation: 20181227 Granted publication date: 20151007 Pledgee: China Co truction Bank Corp Guangzhou economic and Technological Development Zone sub branch Pledgor: Anyka (Guangzhou) Microelectronics Technology Co., Ltd. Registration number: 2017990001008 |
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Denomination of invention: Double data rate SDRAM (ddr) series printed circuit board (pcb) timing sequence compensation method, system and terminal Effective date of registration: 20190130 Granted publication date: 20151007 Pledgee: China Co truction Bank Corp Guangzhou economic and Technological Development Zone sub branch Pledgor: Anyka (Guangzhou) Microelectronics Technology Co., Ltd. Registration number: 2019440000051 |
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Date of cancellation: 20200320 Granted publication date: 20151007 Pledgee: China Co truction Bank Corp Guangzhou economic and Technological Development Zone sub branch Pledgor: ANYKA (GUANGZHOU) MICROELECTRONICS TECHNOLOGY Co.,Ltd. Registration number: 2019440000051 |
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Address after: 3 / F, C1 area, innovation building, 182 science Avenue, Science City, Guangzhou, Guangdong 510663 Patentee after: Guangzhou Ankai Microelectronics Co.,Ltd. Address before: 3 / F, C1 area, innovation building, 182 science Avenue, Science City, Guangzhou, Guangdong 510663 Patentee before: ANYKA (GUANGZHOU) MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
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Address after: 510555 No. 107 Bowen Road, Huangpu District, Guangzhou, Guangdong Patentee after: Guangzhou Ankai Microelectronics Co.,Ltd. Address before: 3 / F, C1 area, innovation building, 182 science Avenue, Science City, Guangzhou, Guangdong 510663 Patentee before: Guangzhou Ankai Microelectronics Co.,Ltd. |
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