CN103455691A - Simplified CCT (channel check tool) pre-simulation method - Google Patents

Abstract

The invention provides a simplified CCT (channel check tool) pre-simulation method. CCT provides a convenient pre-simulation method for signal loss influence of actual routing environments in PCB (printed circuit board) design, a powerful evaluation basis is provided for project early stage risk evaluation and design planning. The automatic simulation provides an effective and independent research process for developers, complete dependence on Intel design guidance is avoided, and creative products with self features can be developed. The pre-simulation result of a new project is compared with the simulation result of a developed project, the new project scheme is large in topology possibility if the pre-simulation result is better than the simulation value of the developed project, otherwise, risks and project scheme feasibility need to be evaluated, and the project schemes needs to be changed appropriately for simulation and comparison again.

Description

Emulation mode before a kind of CCT of simplification

Technical field

The present invention relates to field of computer technology, emulation mode before the CCT of specifically a kind of simplification.

Background technology

Along with the signal rate of rising, in PCB design, the actual thread environment of walking is increasing on the loss impact of signal, thereby causes the risk of system signal stability also more and more higher.Therefore will design safely, low-risk systems stabilisation, walk thread environment in design early stage to signal actual and do impacts such as simulating and simulate the signal attenuation loss and just seem very important.The checking tool CCT of passage (Channel Check Tool) C/C for short T, provide a kind of simple and efficient effective emulation mode for emulation before signal exactly, its simulation flow as shown in Figure 1, the front simulation result of new projects and the simulation result of existing project are made comparisons, if comparative result is better than the project simulation value of passing through test, the scheme of new projects and topological feasibility are larger; If be worse than the project simulation value of passing through test, need to assess risk and scheme feasibility, and appropriate change project alternative emulation comparison again.CCT for PCB in designing actual walk thread environment impact provide easily on loss of signal before emulation mode, strong judging basis is provided also to project risk assessment in early stage and design planning simultaneously.The simulation flow of its independence (as shown in Figure 1), also, for the research and development deviser provides effectively independently R&D process, rely on the design guidance of Intel no longer fully, thereby develop, has the product that self-characteristic has more innovation.As shown in Figure 1, we only need and research and develop successful project simulation result by the front simulation result of new projects and make comparisons, if comparative result is better than the project simulation value of passing through test, the scheme of new projects and topological feasibility are larger; If be worse than the project simulation value of passing through test, need to assess risk and scheme feasibility, and appropriate change project alternative emulation comparison again.But the complicacy due to system architecture, high-speed bus often runs through a plurality of PCB veneers, when the simulated extraction model, just need to set up pore model and transmission line model for each different stacked veneers, can expend a large amount of time like this, thereby affect project process.This invention is exactly for this class problem, simplifies the CCT emulation mode.

Summary of the invention

The front emulation mode of CCT that the purpose of this invention is to provide a kind of simplification.

The objective of the invention is to realize in the following manner, step is as follows:

1) set up the topology simulation link that is similar to or oneself has completed and passed through the similar item of test with Intel's design guidance, according to off-the-shelf item, choose the successful item of similar system framework as the emulation reference;

2) intercept out the part link that in framework, in bus topology, different PCB design and do model extraction, set up the topology simulation link of new projects;

3) start time-domain-simulation, the simulation result of the part link designed by the more different PCB of CCT emulation, and do risk assessment, calculate and compare the above two channel parameters;

4) risk assessment;

5) if risk can be accepted, finish front emulation; If risk is unacceptable, returns to step 1) and change with reference to topology or return to step 2) the change design parameter.

The invention has the beneficial effects as follows: the application of this emulation mode of CCT is very strong, and independence is also very high.But because the link topology of some bus is very complicated, often run through several pcb boards, like this when the simulated extraction model, just need to set up pore model and transmission line model for each different stacked veneers, and the process spended time of extraction model is relatively long, especially cross pore model, and take over multi-model at the link medium chain and tend to the problem that occurs that link is not restrained, therefore the present invention is exactly for this problem, simplify CCT emulation, when system architecture is just the same or part when the same, we only extract the link of the difference in topology and do emulation relatively.

The accompanying drawing explanation

Fig. 1 is CCT simulation flow figure;

Fig. 2 is A project and B project bus topology figure;

Fig. 3 is project A veneer 1 cabling environment map;

Fig. 4 is project B veneer 1 cabling environment map.

Embodiment

With reference to Figure of description, method of the present invention is described in detail below.

Along with the signal rate of rising, in PCB design, the actual thread environment of walking is increasing on the loss impact of signal, thereby causes the risk of system signal stability also more and more higher.Therefore will design safely, low-risk systems stabilisation, walk thread environment in design early stage to signal actual and do impacts such as simulating and simulate the signal attenuation loss and just seem very important.The checking tool CCT of passage (Channel Check Tool) just provides a kind of simple and efficient effective emulation mode for emulation before signal, its simulation flow as shown in Figure 1, the front simulation result of new projects and the simulation result of existing project are made comparisons, if comparative result is better than the project simulation value of passing through test, the scheme of new projects and topological feasibility are larger; If be worse than the project simulation value of passing through test, need to assess risk and scheme feasibility, and appropriate change project alternative emulation comparison again.

A lot of approximate designs are arranged usually, system architecture is approximate or the same, just on function, adjust to some extent, the topological structure of high speed signal is also approximate or identical, just in veneer walk thread environment or the ply stack structure is different, so we only use with our successful case and compare and get final product when front emulation, need not be confined to the design guidance of Intel.For example the system architecture of A project and B project is in full accord, and just function realizes some difference, and certain bus topology (as shown in Figure 2) is also in full accord, and the A project is by test.So during emulation, we only need make comparisons and get final product with the simulation result of A project before doing the B project.And A project and B project share a part of PCB, only first veneer upward wiring length difference, stacked difference, walk thread environment difference (as Fig. 3, shown in Fig. 4).So in order to save time, simplify emulation, we only do the emulation comparison of first veneer to two projects, like this when realistic model extracts, we only need the via hole and the transmission line model that extract first veneer to get final product, for our simulation time is at least saved more than 60%.

Under current entry design environment, a lot of approximate designs are arranged usually, system architecture is approximate or the same, just on function, adjust to some extent, the topological structure of high speed signal is also approximate or identical, just in veneer walk thread environment or the ply stack structure is different, compare and get final product so we only use with our successful case when front emulation, need not be confined to the design guidance of Intel.Therefore the application of this emulation mode of CCT is very strong, and independence is also very high.But because the link topology of some bus is very complicated, often run through several pcb boards, like this when the simulated extraction model, just need to set up pore model and transmission line model for each different stacked veneers, and the process spended time of extraction model is relatively long, especially cross pore model, and take over multi-model at the link medium chain and tend to the problem that occurs that link is not restrained, therefore the present invention is exactly for this problem, simplify CCT emulation, when system architecture is just the same or part when the same, we only extract the link of the difference in topology and do emulation relatively.

Embodiment

Step is as follows

1) choose the successful item of similar system framework as the emulation reference according to off-the-shelf item;

2) intercept out the part link that in framework, in bus topology, different PCB design and do model extraction;

The simulation result of the part link 3) designed by the more different PCB of CCT emulation, and do risk assessment.

Except the described technical characterictic of instructions, be the known technology of those skilled in the art.

Claims (1)

1. emulation mode before the CCT of a simplification is characterized in that step is as follows:

1) set up the topology simulation link that is similar to or oneself has completed and passed through the similar item of test with Intel's design guidance, according to off-the-shelf item, choose the successful item of similar system framework as the emulation reference;

2) intercept out the part link that in framework, in bus topology, different PCB design and do model extraction, set up the topology simulation link of new projects;

3) start time-domain-simulation, the simulation result of the part link designed by the more different PCB of CCT emulation, and do risk assessment, calculate and compare the above two channel parameters;

4) risk assessment;

5) if risk can be accepted, finish front emulation; If risk is unacceptable, returns to step 1) and change with reference to topology or return to step 2) the change design parameter.

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