CN107478868A - A kind of signal testing plate for realizing different delayed time function and its design method - Google Patents
A kind of signal testing plate for realizing different delayed time function and its design method Download PDFInfo
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- CN107478868A CN107478868A CN201710639361.4A CN201710639361A CN107478868A CN 107478868 A CN107478868 A CN 107478868A CN 201710639361 A CN201710639361 A CN 201710639361A CN 107478868 A CN107478868 A CN 107478868A
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- module
- plate
- time function
- signal testing
- delayed time
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses a kind of signal testing plate for realizing different delayed time function and its design method, described signal testing plate includes switching Slab element and interface unit, and switching Slab element includes mainboard module, extends plate module, small card module；Described extension plate module is plugged on mainboard module with small card module by slot；Described mainboard module, extension plate module and small card module is respectively configured with more than two linkage lengths；Interface unit is configured with described mainboard module, described interface unit is SMA interfaces.A kind of signal testing plate for realizing different delayed time function and its design method of the present invention is compared to the prior art, it is possible to achieve passive channel is known the real situation in advance, to analyze whether passive link meets design requirement.
Description
Technical field
The present invention relates to the signal testing technical field of passive link, specifically one kind realizes different delayed time function
Signal testing plate and its design method.
Background technology
Along with the arrival of cloud computing era, server quickly grows emergence, in the motherboard design of server, letter
Number speed more and more higher, high speed signal are also constantly being lifted to the demand of signal integrity.
In current PCB design, layout, wiring are main work.And in the disparity items of same platform, it is same
The PCB design of partial circuit can use identical PCB lamination, drilling and cabling, as long as newly-increased so in later stage processing
Cabling.When being laid out wires design for same design part in PCB design, it be able to can be expired with use calling module
Foot requires, for example, when same partial circuit has application in multiple projects, can use same module to design.For
The high speed cabling such as PCIe, SAS, SATA, USB, prior art are modeled by modes such as 3D modeling, PCB trace extractions；But
It is as follows the drawbacks of presence：
The actual cablings of PCB are lacked and tested, emulate has gap with actual passive channel, so as to meet design requirement.
The content of the invention
The technical assignment of the present invention is to be directed to above weak point, there is provided a kind of signal for realizing different delayed time function is surveyed
Test plate (panel) and its design method.
The technical solution adopted for the present invention to solve the technical problems is：A kind of signal for realizing different delayed time function is surveyed
Test plate (panel), including switching Slab element and interface unit；Described switching Slab element, for emulation PC IE high speed signals, have a variety of
Linkage length；Described interface unit, for connecting test instrument, and carry out the collection and extraction of data.
Further, preferable structure is that described switching Slab element includes mainboard module, extends plate module, small snap gauge
Block；Described extension plate module is plugged on mainboard module with small card module by slot；Described mainboard module, extension plate
Module and small card module are respectively configured with more than two linkage lengths；
Interface unit is configured with described mainboard module, described interface unit is SMA interfaces.
Further, preferable structure is that described mainboard module is configured with tri- kinds of links of 6inch, 9inch, 12inch
Length.
Further, preferable structure is, described extension plate module be configured with 1.5inch, 2inch, 2.5inch,
Seven kinds of linkage lengths of 3inch, 3.5inch, 4inch, 5inch.
Further, preferable structure is that described small card module is configured with two kinds of link length of 3.5inch and 4inch
Degree.
Further, preferable structure is that described SMA interfaces use screw patterns.
A kind of signal testing plate design method for realizing different delayed time function,
S1, according to PCIE topological structures, design adapter plate structure；
S2, the linkage length for designing pinboard；
S3, determine SMA interface types；
S4, pinboard pass through active and passive test data analysis signal matter by SMA interface connecting test instruments
Amount problem.
Further, preferable method is that described PCIE topological structures are PCIe CPU-Riser-DC topologys, PCIe
CPU-oculink-nvme topologys, PCIe CPU-PCIe AN connectors topology.
Further, preferable method is that described adapter plate structure includes mainboard module, extends plate module, small snap gauge
Block；Described extension plate module is plugged on mainboard module with small card module by slot；Described mainboard module, extension plate
Module and small card module are respectively configured with more than two linkage lengths.
Further, preferable method is that described mainboard module is configured with tri- kinds of links of 6inch, 9inch, 12inch
Length；Described extension plate module is configured with 1.5inch, 2inch, 2.5inch, 3inch, 3.5inch, 4inch, 5inch seven
Kind linkage length；Described small card module is configured with two kinds of linkage lengths of 3.5inch and 4inch.
A kind of signal testing plate design method for realizing different delayed time function of the present invention is compared to the prior art, beneficial
Effect is as follows：
1st, the compatible substantial amounts of signal variable of test board of the invention, it is possible to achieve the selection of 42 kinds of linkage lengths, so as to real
Existing different delay function, realize emulation with actual passive channel without gap；
2nd, by the test system, realize that passive channel is known the real situation in advance, to analyze whether passive link meets that design will
Ask；
3rd, the chip that producer provides can be scrambled by the test system and realize that surplus is known the real situation, error rate test etc. passes through
Test data calibrates simulation model with emulating the contrast of data.
Embodiment
With reference to specific embodiment, the invention will be further described.
The present invention is a kind of signal testing plate for realizing different delayed time function and its design method.
Embodiment 1：
A kind of design method for the signal testing plate for realizing different delayed time function, PCIe test system pinboards are first developed,
The main purpose of described signal testing plate is exactly for emulation PC Ie high speed signals.
S1, for common different topology, respectively PCIe CPU-Riser-DC topologys, PCIe CPU-oculink-
Nvme topologys, PCIe CPU-PCIe AN connectors topology, these three different topologys cover nearly all PCIe cablings
Topological structure, develop PCIe test system pinboards.
Analysis result is as follows：
The first topology：PCIe CPU-Riser-DC topology analysis；Gone to from PCIe cablings from CPU
The nonstandard connectors of PCIe 240pin and then being drawn from Riser, Riser connects GPU, network interface card, SAS cards etc. again, such case, in order to
Realize full link passive channel test, it is necessary to design the pinboard of the subcards such as pinboard and GPU, network interface card, the SAS cards of mainboard.
Second of topology:PCIe CPU-oculink-nvme topology analysis；Walked from PCIe cablings from CPU
Finally gone to mainboard ocu link connectors and then by the ocu link connectors on cable connection backboards and support nvme
The connector of hard disk.
The third topology:PCIe CPU-PCIe conn standard topology analysis；From PCIe cablings
The PCIe standard connector directly gone to from CPU on mainboard.PCIe standard connector connects GPU, network interface card, SAS cards etc. again.It is this
Situation, in order to realize full link passive channel test, it is necessary to design the subcards such as pinboard and GPU, network interface card, the SAS cards of mainboard
Pinboard.
After above-mentioned analysis, test system pinboard is made up of three boards, respectively motherboard circuit plate (MB cards),
Extend signal circuit board (EB cards) and lesser calorie (SC cards).
S2, pinboard sheet material choose the most frequently used sheet material to simulate practical application scene；The most common stacking of mainboard, from public affairs
Take charge of the mainboard of volume production in generic server；GPU, network interface card, SAS cards choose a kind of most common compatible stacking；Mainboard and small
Card stack Rotating fields are identical to be shown in Table 1；Extend signal circuit board, i.e. the laminated construction of extension plate is to be shown in Table 2；
Table 1
Table 2
S3, in specific testing scheme, MB linkage length has tri- kinds of selections of 6inch, 9inch, 12inch, extension plate
(EB) linkage length has 7 kinds of selections of 1.5inch, 2inch, 2.5inch, 3inch, 3.5inch, 4inch, 5inch, and inserts
There are two kinds of selections of 3.5inch and 4inch on lesser calorie (SC) on MB plates, like this total of 3*7*2=42 kinds are different
Selection, and different selections has different linkage lengths, different linkage lengths correspond to different signal delay, therefore
Realize different delay features.
S4, SMA type are chosen and calibration chooses the screw formulas SMA for being applied to high speed test.It will can test
Instrument is connected in described SMA interfaces, and the collection and extraction of data are carried out by this interface.
S5, passive and active test carried out by PCIe test systems pinboard respectively, believed by test data analysis
Number quality problems.
The PCIe test systems pinboard of the present invention can simulate common PCIe link length, select on three boards
Different length, can be according to project demand come the delay to different delayed time PCIe signals；When to develop a new product,
By the test system, realize that passive channel is known the real situation in advance, to analyze whether passive link meets design requirement.
The chip that producer provides by test system scrambling realize surplus know the real situation, error rate test etc.；By testing number
Simulation model is calibrated according to the contrast with emulation data.
A kind of present invention signal testing for realizing different delayed time function also caused by this design method of protection application
Plate, including switching Slab element and interface unit；Described switching Slab element, for emulation PC IE high speed signals, there are a variety of chains
Road length；Described interface unit, for connecting test instrument, and carry out the collection and extraction of data.Described pinboard list
Member includes mainboard module, extends plate module, small card module；Described extension plate module is plugged on small card module by slot
On mainboard module；Described mainboard module is configured with tri- kinds of linkage lengths of 6inch, 9inch, 12inch.Described extension template die
Block is configured with seven kinds of linkage lengths of 1.5inch, 2inch, 2.5inch, 3inch, 3.5inch, 4inch, 5inch.Described is small
Card module is configured with two kinds of linkage lengths of 3.5inch and 4inch.Interface unit is configured with described mainboard module, it is described
Interface unit be SMA interfaces.
By embodiment above, the those skilled in the art can readily realize the present invention.But should
Work as understanding, the present invention is not limited to above-mentioned several embodiments.On the basis of disclosed embodiment, the skill
The technical staff in art field can be combined different technical characteristics, so as to realize different technical schemes.
Claims (10)
1. a kind of signal testing plate for realizing different delayed time function, it is characterised in that including switching Slab element and interface unit；
Described switching Slab element, for emulation PC IE high speed signals, there are a variety of linkage lengths；
Described interface unit, for connecting test instrument, and carry out the collection and extraction of data.
2. a kind of signal testing plate for realizing different delayed time function according to claim 1, it is characterised in that described turns
Fishplate bar unit includes mainboard module, extends plate module, small card module；Described extension plate module is inserted with small card module by slot
It is connected on mainboard module；Described mainboard module, extension plate module and small card module is respectively configured with more than two linkage lengths；
Interface unit is configured with described mainboard module, described interface unit is SMA interfaces.
A kind of 3. signal testing plate for realizing different delayed time function according to claim 2, it is characterised in that described master
Plate module is configured with tri- kinds of linkage lengths of 6inch, 9inch, 12inch.
4. a kind of signal testing plate for realizing different delayed time function according to claim 2, it is characterised in that described prolongs
Long plate module is configured with seven kinds of linkage lengths of 1.5inch, 2inch, 2.5inch, 3inch, 3.5inch, 4inch, 5inch.
5. a kind of signal testing plate for realizing different delayed time function according to claim 2, it is characterised in that described is small
Card module is configured with two kinds of linkage lengths of 3.5inch and 4inch.
6. a kind of signal testing plate for realizing different delayed time function according to any one of claim 3-5, its feature exist
In described SMA interfaces use screw patterns.
A kind of 7. signal testing plate design method for realizing different delayed time function, it is characterised in that
S1, according to PCIE topological structures, design adapter plate structure；
S2, the linkage length for designing pinboard；
S3, determine SMA interface types；
S4, pinboard are asked by SMA interface connecting test instruments by active and passive test data analysis signal quality
Topic.
A kind of 8. signal testing plate design method for realizing different delayed time function according to claim 7, it is characterised in that
Described PCIE topological structures are PCIe CPU-Riser-DC topologys, PCIe CPU-oculink-nvme topologys, PCIe CPU-
PCIe standard connector topology.
9. a kind of signal testing plate design method for realizing different delayed time function according to any one of claim 7, institute
The adapter plate structure stated includes mainboard module, extends plate module, small card module；Described extension plate module passes through with small card module
Slot is plugged on mainboard module；Described mainboard module, extension plate module and small card module is respectively configured with more than two chains
Road length.
10. a kind of signal testing plate design method for realizing different delayed time function according to claim 9, its feature exist
In described mainboard module is configured with tri- kinds of linkage lengths of 6inch, 9inch, 12inch；Described extension plate module is configured with
Seven kinds of linkage lengths of 1.5inch, 2inch, 2.5inch, 3inch, 3.5inch, 4inch, 5inch；Described small card module is matched somebody with somebody
It is equipped with two kinds of linkage lengths of 3.5inch and 4inch.
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| CN201710639361.4A CN107478868A (en) | 2017-07-31 | 2017-07-31 | A kind of signal testing plate for realizing different delayed time function and its design method |
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| CN201710639361.4A CN107478868A (en) | 2017-07-31 | 2017-07-31 | A kind of signal testing plate for realizing different delayed time function and its design method |
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Citations (6)
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|---|---|---|---|---|
| CN101739379A (en) * | 2010-01-21 | 2010-06-16 | 山东高效能服务器和存储研究院 | Server-based method for designing hot-swappable PCIE equipment box |
| CN101808460A (en) * | 2010-03-25 | 2010-08-18 | 中兴通讯股份有限公司 | Routing method for PCB and PCB |
| CN103460200A (en) * | 2011-04-05 | 2013-12-18 | 超威半导体公司 | Slot design for flexible and expandable system architecture |
| CN103455691A (en) * | 2013-09-25 | 2013-12-18 | 浪潮电子信息产业股份有限公司 | Simplified CCT (channel check tool) pre-simulation method |
| CN205880145U (en) * | 2016-06-21 | 2017-01-11 | 深圳市兴森快捷电路科技股份有限公司 | Test panel and testing arrangement are surveyed in TRL calibration of passive link |
| CN106503369A (en) * | 2016-11-04 | 2017-03-15 | 郑州云海信息技术有限公司 | A kind of device for realizing that multiple high-speed bus PCB links are shared and its method for designing |
-
2017
- 2017-07-31 CN CN201710639361.4A patent/CN107478868A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101739379A (en) * | 2010-01-21 | 2010-06-16 | 山东高效能服务器和存储研究院 | Server-based method for designing hot-swappable PCIE equipment box |
| CN101808460A (en) * | 2010-03-25 | 2010-08-18 | 中兴通讯股份有限公司 | Routing method for PCB and PCB |
| CN103460200A (en) * | 2011-04-05 | 2013-12-18 | 超威半导体公司 | Slot design for flexible and expandable system architecture |
| CN103455691A (en) * | 2013-09-25 | 2013-12-18 | 浪潮电子信息产业股份有限公司 | Simplified CCT (channel check tool) pre-simulation method |
| CN205880145U (en) * | 2016-06-21 | 2017-01-11 | 深圳市兴森快捷电路科技股份有限公司 | Test panel and testing arrangement are surveyed in TRL calibration of passive link |
| CN106503369A (en) * | 2016-11-04 | 2017-03-15 | 郑州云海信息技术有限公司 | A kind of device for realizing that multiple high-speed bus PCB links are shared and its method for designing |
Non-Patent Citations (1)
| Title |
|---|
| 陈超 等: "多板链路中PCIe3.0信号完整性分析与仿真", 《第十六届计算机工程与工艺年会暨第二届微处理器技术论坛论文集》 * |
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Application publication date: 20171215 |
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