CN104636307A - Method for manufacturing serial data channels supporting FC protocol 16G communication speed - Google Patents
Method for manufacturing serial data channels supporting FC protocol 16G communication speed Download PDFInfo
- Publication number
- CN104636307A CN104636307A CN201510007635.9A CN201510007635A CN104636307A CN 104636307 A CN104636307 A CN 104636307A CN 201510007635 A CN201510007635 A CN 201510007635A CN 104636307 A CN104636307 A CN 104636307A
- Authority
- CN
- China
- Prior art keywords
- serial data
- transmission lines
- loss
- difference
- pcb board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Abstract
The invention discloses a method for manufacturing serial data channels supporting the FC protocol 16G communication speed. The method comprises the following steps that (1) a serial data transceiver at the 16G speed is structured through an FPGA device; (2) a photovoltaic conversion module is soldered to a PCB; (3) difference transmission lines are distributed on the PCB, and loss estimation is conducted on the longest difference transmission line; (4) the insertion loss of the whole transmission channels on the PCB is estimated; (5) after the PCB design is completed, frequency domain simulation is conducted on all the serial data channels on the PCB; (6) crosstalk simulation is conduced on all the serial data channels on the PCB. By means of the method, it is ensured that the loss, the crosstalk and the like of the 16G FC data transmission channels can meet the transmission requirement, and the success rate of the design of 16G FC transmission is increased to a great extent.
Description
Technical field
The present invention relates to communication technical field, propose a kind of method for designing supporting the high-quality serial data channel of FC agreement 16G communication speed.
Technical background
Since calendar year 2001 2G FC technology is released, the FC interconnection technique of a new generation develops rapidly, at present the FC matured product of existing 4G, 8G, and the 5th generation 16G FC also begins to show, and even the standard of 32G FC also emerges.Along with the raising of FC speed, the performance of high-speed serial data path becomes the key design factor of high speed FC transmission, data channel is in the frequency of linear speed 14.025G, we can run into serious Signal transmissions challenge, if consequently signal of not taking measures arrives receiving end effectively cannot receive data (eye pattern closes).In the face of more and more faster FC transfer rate, it is the overriding challenge that FC Hardware Engineer faces.In traditional method for designing, although consider the selection of FPGA device, the medium dissipation factor of sheet material and the appropriate design etc. of rhythmo structure, but the crosstalk etc. between the loss of serial data transmission passage and serial data transmission passage can not accurately be estimated, be easy to cause the loss of transmission channel can not meet the needs of 16G FC or adjacency channel crosstalk excessive, bit error rate increase even link disconnects and repeatedly revises, and finally causes that the project cycle is incured loss through delay, cost increases even project failure greatly.
Summary of the invention
Goal of the invention of the present invention is for 16G FC transmission feature, a kind of method for making supporting the serial data channel of FC agreement 16G communication speed is proposed, effective emulation estimation has all been carried out from the aspect such as customization, high-frequency signal quality, difference transmission lines design of FPGA type selecting, serial data channel, the loss of guarantee 16G FC data transmission channel and crosstalk etc. can meet transmission requirement, and what improve 16G FC transmission largely is designed to power.
Goal of the invention of the present invention is achieved through the following technical solutions:
Support a method for making for the serial data channel of FC agreement 16G communication speed, comprise following steps:
Step 1), on pcb board, utilize FPGA device to build the serial data transceiver of 16G speed;
Step 2), photoelectric conversion module is welded on pcb board;
Step 3), on pcb board, carry out the wiring of difference transmission lines, and emulate before the longest difference transmission lines is carried out and estimate the loss of electric transmission channel, adjusting the cabling mode of difference transmission lines according to the loss result of the electric transmission channel of estimation;
Step 4), the grafting loss of transmission channel whole on pcb board is estimated, and according to the grafting loss result adjustment cabling mode of difference transmission lines and the sheet material of pcb board of the serial transmission channel of estimation;
Step 5), after pcb board designed, simulation in the frequency-domain is carried out to all serial data channels on pcb board, check the loss of each electric transmission channel, if the loss of certain 1 road or multi-path serial data channel is excessive, need the cabling mode of the difference transmission lines of this serial data channel of adjustment separately;
Step 6), all serial data channels on pcb board are done to crosstalk emulation, according to crosstalk simulation result, find out the serial data channel that interference is maximum, the cabling mode of amendment difference transmission lines, again crosstalk emulation is done again, until the crosstalk of all serial data channels is all in claimed range.
According to above-mentioned feature, described step 1) in the FPGA device serial data channel that builds 16G speed comprise following steps:
Step 1.1), build and support the PCS layer of 10GBASE-R agreement and the PMA layer of 14.025G;
Step 1.2), in PCS layer design send pre-emphasis module, continuous time linear equalization module, self-adaptation decision feedback equalization module.
According to above-mentioned feature, described step 3) method of carrying out the wiring of difference transmission lines on pcb board is:
Step 2.1) emulation estimation the single-ended fan-out of BGA of FPGA and the Insertion Loss of difference fan-out thus select be the single-ended fan-out of BGA or difference fan-out mode, if single-ended fan-out is identical with the Insertion Loss effect of difference fan-out, select single-ended fan-out;
Step 2.2) difference transmission lines use arc routing, calculate the characteristic impedance of difference transmission lines, while optimizing via hole, increase hole, ground, formation GSSG layout;
Step 2.3) use back drill technology to remove the stub of via hole to the difference transmission lines cannot walking to show bottom;
Step 2.4), use suitable coupling capacitance, what calculate the reference planes below coupling capacitance hollows out width, increases suitable characteristic impedance.
Beneficial effect of the present invention is: for the demand of high speed data transfer, the high-speed serial data path meeting 16G FC agreement of design, drastically increase the transfer rate of data, meet the requirement sharply increased message transmission rate of future electronic equipment and digital information.What drastically increase high-speed serial data path is designed to power, greatly reduces 16G FC development cost.
Accompanying drawing explanation
Fig. 1 is 16G FC high-speed serial data path schematic diagram.
Fig. 2 high-speed transmission line design flow diagram.
Fig. 3 serial data transmission Channel depletion estimation process flow diagram.
Embodiment
According to drawings and embodiments the present invention is described in further detail below:
The present embodiment hardware module comprises High Speed PCB Board, FPGA circuit and photoelectric conversion module.The difference transmission lines that first high-speed data exports through High-Speed PCB from FPGA finally arrives photoelectric conversion module.The present invention proposes a kind of effective method for designing newly mainly for the PCS layer of FPGA and PMA layer, High-Speed PCB differential transfer passage, can meet the performance requirement of the high bandwidth of 16G FC data transmission, low delay, low jitter.
Basic ideas of the present invention are: first according to the requirement of 16G FC agreement, select suitable FPGA device to build the serial data transceiver of 16G speed, select Altera 28nm Stratix GX V FPGA in the present embodiment.Utilize FPGA to build and support the PCS layer of 10GBASE-R agreement and the PMA layer of 14.025G, in PCS layer design send pre-emphasis module, continuous time linear equalization module, self-adaptation decision feedback equalization module, realize supporting the serial data channel of 16G FC agreement as shown in Figure 1.
Send pre-emphasis module: the high fdrequency component sending signal can be improved, avoid the high-frequency loss in transmitting procedure excessive, cause the higher frequency signal energy of receiving end very weak.
Continuous time linear equalization module: improve the signal to noise ratio (S/N ratio) of signal, increase gain.
Self-adaptation decision feedback equalization module: reduce intersymbol interference.
Pre-emphasis module, continuous time linear equalization module, self-adaptation decision feedback equalization module is all control in the source of signal, improves the integrality of signal, be equivalent to the quality improving signal itself, reduce the rigors to transmission channel.
Photoelectric conversion module is welded on pcb board.
During difference transmission lines design as shown in Figure 2, first the PCB material that medium dissipation factor is little is selected, rhythmo structure reasonable in design.Use the Ansoft HFSS full-field simulations estimation single-ended fan-out of BGA of FPGA and the Insertion Loss of difference fan-out, select to be the single-ended fan-out of BGA or difference fan-out mode according to the single-ended fan-out of estimation and the Insertion Loss result of difference fan-out, under effect same, preferred cabling is wider, the single-ended fan-out that loss is less.
Difference transmission lines uses arc routing, calculates the characteristic impedance of difference transmission lines, increases hole, ground, form GSSG layout while optimizing via hole.To the difference transmission lines cannot walking to show bottom, back drill technology is used to remove the stub of via hole.Use the coupling capacitance of minimum encapsulation, use is solved, and software Polar Si9000 calculates reference planes below coupling capacitance hollows out width, increases suitable characteristic impedance as far as possible.
After PCB layout completes, the SiWave software of Ansoft is used to carry out front emulation to the longest serial data channel, the loss of estimation electric transmission channel.According to the loss result of the electric transmission channel estimated, if the demand of 16G communication can not be met, need the cabling mode (comprising the spacing of differential lines, live width, number of vias) adjusting differential lines.
Then the Insertion Loss that whole serial data channel comprises electric transmission channel loss and optical-electric module is estimated.By the loss of OIF CEI-25G LR standard control 16GFC transmission channel.If loss is excessive, needs the cabling mode of adjustment differential lines, even need to change the less pcb board material of dissipation factor.
After design on board level completes, owing to PCB there being a lot of roads serial data channel there is crosstalk, simulation in the frequency-domain being carried out to PCB, checks the loss of each electric transmission channel.HyperLynx software is finally used to do crosstalk emulation, the differential pair that amendment crosstalk is larger, crosstalk reduction as far as possible.Again crosstalk emulation is done again, until the crosstalk of all serial data channels is all in claimed range.Through the design cycle of above data transmission channel, greatly can improve the success ratio of high-speed serial data transmission channel, greatly reduce development cost.
In sum, as shown in Figure 3, the present invention repeatedly carries out loss evaluation in serial data channel design process, substantially increases the success ratio of 16G FC high speed data transfer channels designs.
The present invention, according to the understanding of 16G FC agreement, when current 16G FC is in research frontier, proposes a kind of method for designing of effective high-quality serial data channel.Substantially increase the success ratio of 16G FC high speed data transfer channels designs, reduce development cost.Also certain reference value is had to data transmission more at a high speed.The method for designing that the present invention proposes is effectively novel, meets the demand to high speed data transfer in digital information system.
Claims (3)
1. support a method for making for the serial data channel of FC agreement 16G communication speed, comprise following steps:
Step 1), on pcb board, utilize FPGA device to build the serial data transceiver of 16G speed;
Step 2), photoelectric conversion module is welded on pcb board;
Step 3), on pcb board, carry out the wiring of difference transmission lines, and emulate before the longest difference transmission lines is carried out and estimate the loss of electric transmission channel, adjusting the cabling mode of difference transmission lines according to the loss result of the electric transmission channel of estimation;
Step 4), the grafting loss of transmission channel whole on pcb board is estimated, and according to the grafting loss result adjustment cabling mode of difference transmission lines and the sheet material of pcb board of the transmission channel of estimation;
Step 5), after pcb board designed, simulation in the frequency-domain is carried out to all serial data channels on pcb board, check the loss of each electric transmission channel, if the loss of certain 1 road or multi-path serial data channel is excessive, need the cabling mode of the difference transmission lines of this serial data channel of adjustment separately;
Step 6), all serial data channels on pcb board are done to crosstalk emulation, according to crosstalk simulation result, find out the serial data channel that interference is maximum, the cabling mode of amendment difference transmission lines, again crosstalk emulation is done again, until the crosstalk of all serial data channels is all in claimed range.
2. method for making according to claim 1, is characterized in that the serial data channel of described FPGA device structure 16G speed comprises following steps:
Step 1.1), build and support the PCS layer of 10GBASE-R agreement and the PMA layer of 14.025G;
Step 1.2), in PCS layer design send pre-emphasis module, continuous time linear equalization module, self-adaptation decision feedback equalization module.
3. method for making according to claim 1, is characterized in that described step 3) method of carrying out the wiring of difference transmission lines on pcb board is:
Step 2.1) emulation estimation the single-ended fan-out of BGA of FPGA and the Insertion Loss of difference fan-out thus select be the single-ended fan-out of BGA or difference fan-out mode, if single-ended fan-out is identical with the Insertion Loss effect of difference fan-out, select single-ended fan-out;
Step 2.2) difference transmission lines use arc routing, calculate the characteristic impedance of difference transmission lines, while optimizing via hole, increase hole, ground, formation GSSG layout;
Step 2.3) use back drill technology to remove the stub of via hole to the difference transmission lines cannot walking to show bottom;
Step 2.4), use suitable coupling capacitance, what calculate the reference planes below coupling capacitance hollows out width, increases suitable characteristic impedance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510007635.9A CN104636307A (en) | 2015-01-08 | 2015-01-08 | Method for manufacturing serial data channels supporting FC protocol 16G communication speed |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510007635.9A CN104636307A (en) | 2015-01-08 | 2015-01-08 | Method for manufacturing serial data channels supporting FC protocol 16G communication speed |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104636307A true CN104636307A (en) | 2015-05-20 |
Family
ID=53215080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510007635.9A Pending CN104636307A (en) | 2015-01-08 | 2015-01-08 | Method for manufacturing serial data channels supporting FC protocol 16G communication speed |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104636307A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106443416A (en) * | 2016-11-18 | 2017-02-22 | 中国电子科技集团公司第二十九研究所 | Method and apparatus for realizing self-calibration of microwave performance of multi-layer circuit board |
| CN107942291A (en) * | 2017-10-12 | 2018-04-20 | 西安天和防务技术股份有限公司 | Intermediate frequency digital receiver, IF signal processing method |
| CN109600149A (en) * | 2018-12-28 | 2019-04-09 | 无锡市同步电子科技有限公司 | A kind of radio-frequency delay line and its test method |
| CN111781992A (en) * | 2020-06-19 | 2020-10-16 | 苏州浪潮智能科技有限公司 | Layout method of multiple board cards in server and server multiple board card structure |
| CN113609808A (en) * | 2021-03-08 | 2021-11-05 | 安徽师范大学 | PCIExpress signal integrity improvement method for navigation display system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09274623A (en) * | 1996-04-08 | 1997-10-21 | Oki Electric Ind Co Ltd | Transmission line simulation system and transmission line simulation method using the same |
| CN1472680A (en) * | 2003-05-01 | 2004-02-04 | 清华大学 | Method for reducing serial interfere on wire distribution procedure of standard apartment |
| CN101527662A (en) * | 2009-04-09 | 2009-09-09 | 中兴通讯股份有限公司 | Method for optimizing high-speed channel and device thereof |
| CN101673317A (en) * | 2009-10-23 | 2010-03-17 | 中兴通讯股份有限公司 | High-speed serial channel pre-emphasis adjusting method and device |
| CN103455691A (en) * | 2013-09-25 | 2013-12-18 | 浪潮电子信息产业股份有限公司 | Simplified CCT (channel check tool) pre-simulation method |
-
2015
- 2015-01-08 CN CN201510007635.9A patent/CN104636307A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09274623A (en) * | 1996-04-08 | 1997-10-21 | Oki Electric Ind Co Ltd | Transmission line simulation system and transmission line simulation method using the same |
| CN1472680A (en) * | 2003-05-01 | 2004-02-04 | 清华大学 | Method for reducing serial interfere on wire distribution procedure of standard apartment |
| CN101527662A (en) * | 2009-04-09 | 2009-09-09 | 中兴通讯股份有限公司 | Method for optimizing high-speed channel and device thereof |
| CN101673317A (en) * | 2009-10-23 | 2010-03-17 | 中兴通讯股份有限公司 | High-speed serial channel pre-emphasis adjusting method and device |
| CN103455691A (en) * | 2013-09-25 | 2013-12-18 | 浪潮电子信息产业股份有限公司 | Simplified CCT (channel check tool) pre-simulation method |
Non-Patent Citations (3)
| Title |
|---|
| 吴茜等: "10G高速印制电路板的设计与研究", 《机电元件》 * |
| 沈军: "基于仿真与验证的高速PCB性能研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 王红飞等: "高速PCB过孔设计研究进展", 《印制电路信息》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106443416A (en) * | 2016-11-18 | 2017-02-22 | 中国电子科技集团公司第二十九研究所 | Method and apparatus for realizing self-calibration of microwave performance of multi-layer circuit board |
| CN106443416B (en) * | 2016-11-18 | 2018-12-25 | 中国电子科技集团公司第二十九研究所 | One kind being able to achieve multilayer circuit board microwave property method for self-calibrating and device |
| CN107942291A (en) * | 2017-10-12 | 2018-04-20 | 西安天和防务技术股份有限公司 | Intermediate frequency digital receiver, IF signal processing method |
| CN109600149A (en) * | 2018-12-28 | 2019-04-09 | 无锡市同步电子科技有限公司 | A kind of radio-frequency delay line and its test method |
| CN111781992A (en) * | 2020-06-19 | 2020-10-16 | 苏州浪潮智能科技有限公司 | Layout method of multiple board cards in server and server multiple board card structure |
| CN111781992B (en) * | 2020-06-19 | 2022-03-08 | 苏州浪潮智能科技有限公司 | Layout method of multiple board cards in server and server multiple board card device |
| CN113609808A (en) * | 2021-03-08 | 2021-11-05 | 安徽师范大学 | PCIExpress signal integrity improvement method for navigation display system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104636307A (en) | Method for manufacturing serial data channels supporting FC protocol 16G communication speed | |
| Momtaz et al. | An 80 mW 40 Gb/s 7-tap T/2-spaced feed-forward equalizer in 65 nm CMOS | |
| CN103621004B (en) | Full duplex transmission method for High speed rear panel system | |
| US9515843B2 (en) | Method and system for link adaptive Ethernet communications | |
| TWI687046B (en) | A two-step feed-forward equalizer for voltage-mode transmitter architecture | |
| US11165609B2 (en) | Signal generation apparatus and method, and system | |
| US8428111B2 (en) | Crosstalk emission management | |
| Yazaki et al. | 25-Gbps× 4 optical transmitter with adjustable asymmetric pre-emphasis in 65-nm CMOS | |
| Reynolds et al. | A 7-tap transverse analog-FIR filter in 0.12/spl mu/m CMOS for equalization of 10Gb/s fiber-optic data systems | |
| De Keulenaer et al. | 56+ Gb/s serial transmission using duo-binary signaling | |
| Dehlaghi et al. | A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS | |
| Rao et al. | Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect | |
| CN102684945A (en) | Test access port (TAP) equipment | |
| Oh et al. | A 5Gb/s 2× 2 MIMO crosstalk cancellation scheme for high-speed I/Os | |
| Wary et al. | A low impedance receiver for power efficient current mode signalling across on-chip global interconnects | |
| Wang et al. | Design high bandwidth-density, low latency and energy efficient on-chip interconnect | |
| Wang et al. | Equalization techniques for high-speed serial interconnect transceivers | |
| CN111431618B (en) | BiCMOS (Bipolar complementary Metal oxide semiconductor) optical transmitter driving circuit based on PAM4 modulation mode | |
| Momtaz et al. | An 80mW 40Gb/s 7-tap T/2-spaced FFE in 65nm CMOS | |
| Beyene et al. | Controlled intersymbol interference design techniques of conventional interconnect systems for data rates beyond 20 Gbps | |
| Choudhary et al. | An EMI immune PAM4 transmitter in 130 nm BiCMOS technology | |
| Bensalem et al. | Comparison of Wideband Interconnecting Technologies for Multigigahertz Novel Memory Architecture | |
| Sen et al. | A multiband transceiver system in 45-nm CMOS for extended data rate through notchy wireline channels | |
| Ban | Feed-forward equalizer for high speed serial electrical communication up to 100 Gb/s | |
| Mo et al. | A 20Gbps on-chip transceiver with equalization technique for global signal transmission |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150520 |
|
| WD01 | Invention patent application deemed withdrawn after publication |