CN103257309A - Double data rate SDRAM (ddr) series printed circuit board (pcb) timing sequence compensation method, system and terminal - Google Patents
Double data rate SDRAM (ddr) series printed circuit board (pcb) timing sequence compensation method, system and terminal Download PDFInfo
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Abstract
The invention provides a double data rate SDRAM (ddr) series printed circuit board (pcb) timing sequence compensation method, system and terminal which is applied to the field of signal processing. The method comprises the steps of testing timing sequence deviation time of synchronizing signals of board distribution design of a pcb, testing actual timing sequence deviation time of the synchronizing signals on the pcb, correcting the timing sequence deviation time of the synchronizing signals of the board distribution design of the pcb according to the actual timing sequence deviation time of the synchronizing signals on the pcb, determining the minimum single time-delay circuit number required to be set of a master control end by combining actually-measured delay time of single time-delay circuits and the actual timing sequence deviation time of the synchronizing signals on the pcb, and setting time-delay circuits at the master control end by combining the minimum single time-delay circuit number at the master control end and the timing sequence deviation time of the synchronizing signals of the board distribution design of the pcb after correction. The ddr series pcb timing sequence compensation method, system and terminal can effectively reduce probability of unsynchronized transmission of signals on a data line caused by a difference of pcb wiring.
Description
Technical field
The invention belongs to the signal process field, relate in particular to the compensation method of ddr series pcb plate sequential, system and terminal.
Background technology
Development along with the embedded electronic product, present multimedia processor can move very high dominant frequency, to satisfy the growing application demand of operating system, the storer arm-context a9 that reaches 1.2Ghz such as the operation dominant frequency can realize the various application demands of intelligent operating system, satisfies the needs of present embedded intelligence operating system.
Yet, for the big internal memory that satisfies operating system simultaneously and demand cheaply, existing market generally select the Double Data Rate synchronous DRAM (Double Data Rate SDRAM, ddr), ddr2 and these speed of ddr3 are fast, capacity is big and cost is low storer be as the internal memory of system.But these storer factors reportedly defeated velocity ratio are very fast, quality and sequential to signal require than higher, and traditional chip design, sequential to chip exterior is considered seldom, especially under high-speed case, along with the dominant frequency of system constantly improves, the increase of power consumption, various influences can be brought to signal in aspects such as integrality at electromagnetic interference (EMI) and signal, if directly use chip, the signal on the chip is not handled, then the signal on the data line occurs transmitting nonsynchronous phenomenon easily, and then causes that the data acquisition of terminal goes wrong.Such as, if printed circuit board (PCB) (Printed Circuit Board, pcb) wiring has problem, do not satisfy at a high speed, the applied environment of high request and application conditions will influence the sequential of chip exterior, thereby cause the transmission of signal on the pcb plate on the data line asynchronous.
Summary of the invention
The embodiment of the invention provides the compensation method of a kind of ddr series pcb plate sequential, is intended to solve existing operating system when selecting capacity is big and cost is low storer as the internal memory of system for use, and the signal on the data line that causes transmits nonsynchronous problem.
The embodiment of the invention is achieved in that the compensation method of ddr series pcb plate sequential, and described method comprises the steps:
Emulation is carried out in design to the fabric swatch of pcb plate, with the timing skew time of the synchronizing signal of the fabric swatch design that tests out described pcb plate;
The corresponding actual pcb plate of fabric swatch design to described pcb plate is tested, to test out the timing skew time of synchronizing signal on the described actual pcb plate;
According to the timing skew time of the synchronizing signal of the fabric swatch design of timing skew described pcb plate time calibration of synchronizing signal on the described actual pcb plate;
In conjunction with the timing skew time of synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and the described actual pcb plate, need to determine the minimum single time delay circuit unit number of the main control end compensation that arranges;
The timing skew time in conjunction with the synchronizing signal of the fabric swatch design of the delay unit time span of the single delay circuit of main control end and the described pcb plate after the calibration, the compensation delay circuit unit number of main control end is set so that the synchronizing signal of the fabric swatch design of the described pcb plate after the calibration reaches synchronous.
Another purpose of the embodiment of the invention is to provide a kind of ddr series pcb plate sequential bucking-out system, and described system comprises:
Simulate signal timing skew time measuring unit is used for emulation is carried out in the fabric swatch design of pcb plate, with the timing skew time of the synchronizing signal of the fabric swatch design that tests out described pcb plate;
Actual signal timing skew time measuring unit is used for the corresponding actual pcb plate of fabric swatch design of described pcb plate is tested, to test out the timing skew time of synchronizing signal on the described actual pcb plate;
Simulate signal timing skew unit time calibration is used for the timing skew time according to the synchronizing signal of the fabric swatch design of timing skew described pcb plate time calibration of synchronizing signal on the described actual pcb plate;
Single delay circuit number determining unit, be used for the timing skew time in conjunction with synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and the described actual pcb plate, need determine the minimum single time delay circuit unit number of the main control end compensation that arranges;
Delay circuit arranges the unit, be used for the timing skew time in conjunction with the synchronizing signal of the fabric swatch design of the delay unit time span of the single delay circuit of main control end and the described pcb plate after the calibration, the compensation delay circuit unit number of main control end be set so that the synchronizing signal of the fabric swatch design of the described pcb plate after the calibration reaches synchronous.
Another purpose of the embodiment of the invention is to provide a kind of ddr series pcb plate sequential compensation terminal, and described terminal comprises above-mentioned ddr series pcb plate sequential bucking-out system.
The embodiment of the invention can effectively reduce because signal on the caused data line of difference of pcb plate wiring transmits nonsynchronous probability, and then reduces the probability that data collection problems appears in terminal.
Description of drawings
Fig. 1 is the ddr series pcb plate sequential compensation method flow process that first embodiment of the invention provides;
Fig. 2 is the delay circuit synoptic diagram of the main control end that provides of first embodiment of the invention;
Fig. 3 is the ddr series pcb plate sequential bucking-out system structural drawing that second embodiment of the invention provides.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the present invention, and be not used in restriction the present invention.
In the embodiment of the invention, be time calibration with the timing skew of the synchronizing signal of emulation pcb plate time identical with the timing skew time of the synchronizing signal of actual pcb plate, again in conjunction with a plurality of independently delay circuits, the timing skew time of the synchronizing signal of the emulation pcb plate of process calibration synchronously is to obtain the synchronizing signal that does not have the timing skew time.
It is a kind of that the embodiment of the invention provides: the compensation method of ddr series pcb plate sequential, system and terminal.
Described method comprises: emulation is carried out in design to the fabric swatch of pcb plate, with the timing skew time of the synchronizing signal of the fabric swatch design that tests out described pcb plate;
The corresponding actual pcb plate of fabric swatch design to described pcb plate is tested, to test out the timing skew time of synchronizing signal on the described actual pcb plate;
According to the timing skew time of the synchronizing signal of the fabric swatch design of timing skew described pcb plate time calibration of synchronizing signal on the described actual pcb plate;
In conjunction with the timing skew time of synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and the described actual pcb plate, need to determine the minimum single time delay circuit unit number of the main control end compensation that arranges;
The timing skew time in conjunction with the synchronizing signal of the fabric swatch design of the delay unit time span of the single delay circuit of main control end and the described pcb plate after the calibration, the compensation delay circuit unit number of main control end is set so that the synchronizing signal of the fabric swatch design of the described pcb plate after the calibration reaches synchronous.
Described system comprises: simulate signal timing skew time measuring unit was used for emulation is carried out in the fabric swatch design of pcb plate, with the timing skew time of the synchronizing signal of the fabric swatch design that tests out described pcb plate;
Actual signal timing skew time measuring unit is used for the corresponding actual pcb plate of fabric swatch design of described pcb plate is tested, to test out the timing skew time of synchronizing signal on the described actual pcb plate;
Simulate signal timing skew unit time calibration is used for the timing skew time according to the synchronizing signal of the fabric swatch design of timing skew described pcb plate time calibration of synchronizing signal on the described actual pcb plate;
Single delay circuit number determining unit, be used for the timing skew time in conjunction with synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and the described actual pcb plate, need determine the minimum single time delay circuit unit number of the main control end compensation that arranges;
Delay circuit arranges the unit, be used for the timing skew time in conjunction with the synchronizing signal of the fabric swatch design of the delay unit time span of the single delay circuit of main control end and the described pcb plate after the calibration, the compensation delay circuit unit number of main control end be set so that the synchronizing signal of the fabric swatch design of the described pcb plate after the calibration reaches synchronous.
Described terminal comprises: the terminal of above-mentioned ddr series pcb plate sequential bucking-out system.
The embodiment of the invention can effectively reduce because signal on the caused data line of difference of pcb plate wiring transmits nonsynchronous probability, and then reduces the probability that data collection problems appears in terminal.
For technical solutions according to the invention are described, describe below by specific embodiment.
Embodiment one:
Fig. 1 shows a kind of ddr series pcb plate sequential compensation method flow process that first embodiment of the invention provides, in the present embodiment, the timing skew time of the synchronizing signal of the fabric swatch design by calibration pcb plate, and the delay circuit that main control end is set to be to reach the sequential of compensation ddr series pcb plate, and details are as follows:
Step S11, emulation is carried out in design to the fabric swatch of pcb plate, with the timing skew time of the synchronizing signal of the fabric swatch design that tests out this pcb plate.
In the present embodiment, after the fabric swatch design of pcb plate is finished, by subsidiary in the pcb drawing tools or special pcb signal simulation instrument, according to the conditions and environment parameter of using needs, emulation is carried out in fabric swatch design to the pcb plate finished, to test out the timing skew time of the relevant synchronizing signal on this pcb plate.
Step S12 tests the corresponding actual pcb plate of fabric swatch design of this pcb plate, to test out the timing skew time of synchronizing signal on this actual pcb plate.
In the present embodiment, produce actual pcb plate according to the fabric swatch design of the pcb board of finishing, and use relevant instrument, such as instruments such as oscillographs, the actual pcb plate of producing is tested, to test out the timing skew time of synchronizing signal on this actual pcb plate.
Step S13 is according to the timing skew time of the synchronizing signal of the fabric swatch design of timing skew this pcb plate time calibration of synchronizing signal on this actual pcb plate.
In the present embodiment, when the timing skew asynchronism(-nization) of synchronizing signal corresponding in the pcb plate of timing skew time of certain synchronizing signal on the actual pcb plate and emulation, need be time calibration the time identical with timing skew time of corresponding synchronizing signal on the actual pcb plate with the timing skew of the synchronizing signal in the pcb plate of emulation, thereby the timing skew time that both can basis for estimation pcb emulation, with the deviation time scale relation of the pcb plate of time, can provide reference to the compensation relationship that compensates actual pcb plate synchronizing signal transmission delay again.
Step S14 in conjunction with the timing skew time of synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and this actual pcb plate, need to determine the minimum single time delay circuit unit number of the main control end compensation that arranges.
As one embodiment of the present invention, in conjunction with the timing skew time of synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and this actual pcb plate, need to determine the step of the minimum single time delay circuit unit number of the main control end compensation that arranges specifically to comprise:
The delay unit time of A1, the single delay circuit of actual measurement.In the present embodiment, in the delay circuit design of main control end, exist some time-delay impact damper buffer to come buffered signal, the circuit at this impact damper buffer place is also referred to as time delay circuit unit, the delay unit time span of the single delay circuit of actual measurement.Because of under the certain physical condition, the delay time unit of each time-delay impact damper buffer is a set time, only needs to measure the delay unit time of a delay circuit.
A2, the maximum timing skew time of obtaining synchronizing signal on this actual pcb plate, and the gained merchant is the minimum single time delay circuit unit number of the main control end compensation that needs to arrange divided by delay unit time of this single delay circuit maximum timing skew time of synchronizing signal on should actual pcb plate.In the present embodiment, the timing skew of synchronizing signal is the time from the actual pcb plate of measuring, filter out the maximum timing skew time of synchronizing signal on this actual pcb plate, and the maximum timing skew time that will filter out is divided by the delay unit time span of the single delay circuit of measuring, to obtain the minimum single time delay circuit unit number of the main control end compensation that needs setting.For example, suppose that the maximum timing skew time of synchronizing signal is 20ms on the actual pcb plate, the delay unit time of single delay circuit all is 1ms, and the minimum single time delay circuit unit number of the main control end that then need arrange compensation is 20.
Step S15, the timing skew time in conjunction with the synchronizing signal of the fabric swatch design of the delay unit time span of the single delay circuit of this main control end and this pcb plate after the calibration, the compensation delay circuit unit number of main control end is set so that the synchronizing signal of the fabric swatch design of the described pcb plate after the calibration reaches synchronous.
As one embodiment of the present invention, in conjunction with the timing skew time of the synchronizing signal of the fabric swatch design of the delay unit time span of the single delay circuit of this main control end and this pcb plate after the calibration, the compensation delay circuit unit number of main control end is set so that the synchronizing signal of the fabric swatch design of the described pcb plate after the calibration reaches synchronous step specifically comprises:
B1, determine the needed single time delay circuit unit number of timing skew time with each synchronizing signal of the fabric swatch design of pcb plate behind the step calibration.In the present embodiment, because the timing skew time of each synchronizing signal is not necessarily identical, therefore also may be different with needed single time delay circuit unit number of the timing skew time of each synchronizing signal behind the step calibration.For example, the timing skew time of A, B synchronizing signal of supposing is through calibration, be respectively 10ms and 4ms, the delay unit time of single delay circuit all is 1ms, then the needed single time delay circuit unit number of timing skew time of A synchronizing signal is 10 synchronously, and the needed single time delay circuit unit number of timing skew time of B synchronizing signal is 4 synchronously.
B2, in conjunction with the minimum single time delay circuit unit number of the compensation of this main control end, to carry out tandem compound with the needed single delay circuit number of timing skew time of each synchronizing signal of the fabric swatch of pcb plate behind step calibration design, to obtain the delay circuit with the main control end of the synchronizing signal of the fabric swatch design of the pcb plate behind the step calibration.
In the present embodiment, the delay circuit of main control end carries out tandem compound by a plurality of independently time delay circuit unit to be determined, and reaches the purpose of the clock signal of synchronous pcb plate by the time-delay sequential of revising input and output IO mouth end.Wherein, an independently time delay circuit unit formation one-level time-delay, the time delay circuit unit of 2 series connection forms secondary time-delay etc.For example, the minimum single time delay circuit unit number of supposing main control end is 3, the timing skew time of synchronous calibrated C, D, E synchronizing signal, needed single time delay circuit unit number was respectively 1,2,3, then the minimum single time delay circuit unit number of the main control end that will arrange is carried out tandem compound, to need synchronous synchronizing signal C, D, E from the delay circuit of appropriate level, to pass through again, to satisfy the required time difference of compensation, obtained the delay circuit of main control end, concrete synoptic diagram as shown in Figure 2.
As one embodiment of the present invention, in the timing skew time in conjunction with the synchronizing signal of the fabric swatch design of the delay unit time span of the single delay circuit of this main control end compensation and this pcb plate after the calibration, the time delay circuit unit number of compensation of main control end is set so that the synchronizing signal of the fabric swatch design of the described pcb plate after the calibration reaches after the synchronous step, further comprises the steps:
The terminal that this pcb plate is installed is carried out timing sequence test, and according to the timing skew of this pcb plate synchronizing signal of test result correction.
In the present embodiment, the terminal that the pcb plate that compensates through sequential has been installed is carried out timing sequence test, if still there is timing skew in the synchronizing signal of this pcb plate transmission, then according to the deviation of reality as a result situation compensate and correct, the data acquisition of avoiding causing terminal goes wrong, such as avoiding some bit bit data collection mistake to occur.
In first embodiment of the invention, be time calibration with the timing skew of the synchronizing signal of emulation pcb plate time identical with the timing skew time of the synchronizing signal of actual pcb plate, again in conjunction with a plurality of independently time delay circuit unit, the timing skew time of the synchronizing signal of the emulation pcb plate of process calibration synchronously is to obtain the synchronizing signal that does not have the timing skew time.By the software setting, ddr series (ddr, ddr2, the ddr3) storer that these speed are fast, capacity is big and cost is low is carried out the sequential compensation, thereby effectively reduce because signal on the caused data line of difference of pcb plate wiring transmits nonsynchronous probability, and then reduce the probability that data collection problems appears in terminal.
Embodiment two:
Fig. 3 shows the structure of the ddr series pcb plate sequential bucking-out system that second embodiment of the invention provides, and for convenience of explanation, only shows the part relevant with the embodiment of the invention.
This ddr series pcb plate sequential bucking-out system can be used for by the various information processing terminals wired or wireless network Connection Service device, mobile phone for example, pocket computing machine (Pocket Personal Computer, PPC), palm PC, computing machine, notebook computer, personal digital assistant (Personal Digital Assistant, PDA) etc., it can be the software unit that runs in these terminals, the unit that hardware cell or software and hardware combine, also can be used as independently, suspension member is integrated in these terminals or runs in the application system of these terminals, wherein:
Simulate signal timing skew time measuring unit 31 is used for emulation is carried out in the fabric swatch design of pcb plate, with the timing skew time of the synchronizing signal of the fabric swatch design that tests out this pcb plate.
In the present embodiment, by the subsidiary emulation tool of pcb drawing tools or the emulation tool of specialty, emulation testing is carried out in the fabric swatch design of the pcb plate finished, with the timing skew time of the synchronizing signal of the pcb plate that obtains emulation.
Actual signal timing skew time measuring unit 32 is used for the corresponding actual pcb plate of fabric swatch design of this pcb plate is tested, to test out the timing skew time of synchronizing signal on this actual pcb plate.
Simulate signal timing skew unit time calibration 33 is used for the timing skew time according to the synchronizing signal of the fabric swatch design of timing skew this pcb plate time calibration of synchronizing signal on this actual pcb plate.
In the present embodiment, the timing skew time of synchronizing signal on the timing skew time of the synchronizing signal of the emulation pcb plate that relatively obtains and the actual pcb plate, if both differences, then the timing skew time with synchronizing signal on the actual pcb plate is the timing skew time of the synchronizing signal of foundation calibration emulation pcb plate.
Single delay circuit number determining unit 34, be used for the timing skew time in conjunction with synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and this actual pcb plate, need determine the minimum single time delay circuit unit number of the main control end compensation that arranges.
In the present embodiment, at first obtain the maximum timing skew time of all synchronizing signals on the actual pcb plate, need to determine the minimum single time delay circuit unit number of the main control end that arranges again in conjunction with the delay unit time of the single delay circuit of actual measurement.
Delay circuit arranges unit 35, be used for the timing skew time in conjunction with the synchronizing signal of the fabric swatch design of the delay unit time span of the single delay circuit of this main control end and this pcb plate after the calibration, the compensation delay circuit unit number of main control end be set so that the synchronizing signal of the fabric swatch design of this pcb plate after the calibration reaches synchronous.
In the present embodiment, the synchronizing signal that the fabric swatch that has the pcb of timing skew after the calibration designs is passed through at least one time delay circuit unit, have the synchronizing signal of timing skew with correction.In the present embodiment, having the circuit of synchronizing signal of the pcb plate of timing skew synchronously is the delay circuit of main control end.
As one embodiment of the present invention, this single delay circuit number determining unit 34 comprises: the delay time measurement module 341 of single delay circuit and single delay circuit number acquisition module 342, wherein:
The delay time measurement module 341 of single delay circuit is for the delay unit time of the single delay circuit of actual measurement.
In the present embodiment, when adopting buffer to have the synchronizing signal of timing skew time as delay circuit in the synchronous pcb plate, the delay unit time of the single delay circuit of actual measurement.
Single delay circuit number acquisition module 342, for the maximum timing skew time of obtaining synchronizing signal on this actual pcb plate, and the gained merchant is the minimum single time delay circuit unit number of the main control end compensation that needs to arrange divided by delay unit time of this single delay circuit maximum timing skew time of synchronizing signal on should actual pcb plate.
In the present embodiment, determine the single time delay circuit unit that number is minimum, so that the single time delay circuit unit number that follow-up use is determined is combined into the delay circuit of main control end, improve resource utilization.Wherein, the minimum single delay circuit of delay unit number was determined divided by the delay unit time of single delay circuit by the maximum timing skew time of synchronizing signal on the actual pcb plate.
As one embodiment of the present invention, this delay circuit arranges unit 35 and comprises: timing skew time required delay circuit number determination module 351 and single delay circuit serial module structure 352, wherein:
Timing skew time required delay circuit number determination module 351 be used for to be determined the needed single time delay circuit unit number of timing skew time with each synchronizing signal of the fabric swatch design of pcb plate behind the step calibration.
In the present embodiment, determine the required single time delay circuit unit number of timing skew time of synchronous this synchronizing signal according to the timing skew time of synchronizing signal, because the timing skew time of each synchronizing signal is not necessarily identical, therefore also may be different with needed single time delay circuit unit number of the timing skew time of each synchronizing signal behind the step calibration.
Single delay circuit serial module structure 352, be used for the minimum single time delay circuit unit number in conjunction with the compensation of this main control end, with this with step calibration after the needed single time delay circuit unit number of timing skew time of each synchronizing signal of fabric swatch design of pcb plate carry out tandem compound, to obtain the delay circuit with the main control end of the synchronizing signal of the fabric swatch design of the pcb plate behind the step calibration.
In the present embodiment, a plurality of independently delay circuits of determining are carried out tandem compound, and will need the synchronizing signal of the pcb plate after the synchronous calibration to pass through corresponding time-delay rank circuit, to obtain the synchronizing signal that does not have the timing skew time.
As one embodiment of the present invention, this ddr series pcb plate sequential bucking-out system comprises:
Timing skew compensating unit 36 is used for the terminal that this pcb plate is installed is carried out timing sequence test, and according to timing skew time of this pcb plate synchronizing signal of test result correction.
In the present embodiment, the terminal (such as the embedded electronic product) that the pcb plate that compensates through sequential has been installed is carried out timing sequence test, if still there is timing skew in the synchronizing signal of this pcb plate transmission, then according to the deviation of reality as a result situation compensate and correct, the data acquisition of avoiding causing terminal goes wrong, such as avoiding some bit bit data collection mistake to occur.
In second embodiment of the invention, by ddr series (ddr, ddr2, the ddr3) storer that these speed are fast, capacity is big and cost is low being carried out the sequential compensation, thereby effectively reduce because signal on the caused data line of difference of pcb plate wiring transmits nonsynchronous probability, and then reduce the probability that data collection problems appears in terminal.
The above only is preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. ddr series pcb plate sequential compensation method is characterized in that described method comprises the steps:
Emulation is carried out in design to the fabric swatch of pcb plate, with the timing skew time of the synchronizing signal of the fabric swatch design that tests out described pcb plate;
The corresponding actual pcb plate of fabric swatch design to described pcb plate is tested, to test out the timing skew time of synchronizing signal on the described actual pcb plate;
According to the timing skew time of the synchronizing signal of the fabric swatch design of timing skew described pcb plate time calibration of synchronizing signal on the described actual pcb plate;
In conjunction with the timing skew time of synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and the described actual pcb plate, need to determine the minimum single time delay circuit unit number of the main control end compensation that arranges;
The timing skew time in conjunction with the synchronizing signal of the fabric swatch design of the delay unit time span of the single delay circuit of main control end and the described pcb plate after the calibration, the compensation delay circuit unit number of main control end is set so that the synchronizing signal of the fabric swatch design of the described pcb plate after the calibration reaches synchronous.
2. the method for claim 1, it is characterized in that, the timing skew time of synchronizing signal on the delay unit time of the described single delay circuit of main control end in conjunction with actual measurement and the described actual pcb plate, need to determine the step of the minimum single time delay circuit unit number of the main control end compensation that arranges specifically to comprise:
The delay unit time of the single delay circuit of actual measurement;
Obtain the maximum timing skew time of synchronizing signal on the described actual pcb plate, and with the delay unit time divided by described single delay circuit maximum timing skew time of synchronizing signal on the described actual pcb plate, the gained merchant is the minimum single time delay circuit unit number of the main control end compensation that needs to arrange.
3. the method for claim 1, it is characterized in that, the timing skew time of the synchronizing signal of the fabric swatch design of the described pcb plate after the delay unit time span of described single delay circuit in conjunction with main control end and the calibration, the compensation delay circuit unit number of main control end is set so that the synchronizing signal of the fabric swatch design of the described pcb plate after the calibration reaches synchronous step specifically comprises:
Determine the needed single time delay circuit unit number of timing skew time with each synchronizing signal of the fabric swatch design of pcb plate behind the step calibration;
Minimum single time delay circuit unit number in conjunction with the compensation of described main control end, the needed single time delay circuit unit number of timing skew time of each synchronizing signal of described fabric swatch design with pcb plate behind the step calibration is carried out tandem compound, to obtain the delay circuit with the main control end of the synchronizing signal of the fabric swatch design of the pcb plate behind the step calibration.
4. as each described method of claim 1 to 3, it is characterized in that, after the step of the described compensation delay circuit unit number that main control end is set, further comprise the steps:
The terminal that described pcb plate is installed is carried out timing sequence test, and according to the timing skew of the described pcb plate of test result correction synchronizing signal.
5. ddr series pcb plate sequential bucking-out system is characterized in that described system comprises:
Simulate signal timing skew time measuring unit is used for emulation is carried out in the fabric swatch design of pcb plate, with the timing skew time of the synchronizing signal of the fabric swatch design that tests out described pcb plate;
Actual signal timing skew time measuring unit is used for the corresponding actual pcb plate of fabric swatch design of described pcb plate is tested, to test out the timing skew time of synchronizing signal on the described actual pcb plate;
Simulate signal timing skew unit time calibration is used for the timing skew time according to the synchronizing signal of the fabric swatch design of timing skew described pcb plate time calibration of synchronizing signal on the described actual pcb plate;
Single delay circuit number determining unit, be used for the timing skew time in conjunction with synchronizing signal on delay unit time of the single delay circuit of main control end of actual measurement and the described actual pcb plate, need determine the minimum single time delay circuit unit number of the main control end compensation that arranges;
Delay circuit arranges the unit, be used for the timing skew time in conjunction with the synchronizing signal of the fabric swatch design of the delay unit time span of the single delay circuit of main control end and the described pcb plate after the calibration, the compensation delay circuit unit number of main control end be set so that the synchronizing signal of the fabric swatch design of the described pcb plate after the calibration reaches synchronous.
6. system as claimed in claim 5 is characterized in that, described single delay circuit number determining unit comprises:
The delay time measurement module of single delay circuit is for the delay unit time of the single delay circuit of actual measurement;
Single delay circuit number acquisition module, for the maximum timing skew time of obtaining synchronizing signal on the described actual pcb plate, and with the delay unit time divided by described single delay circuit maximum timing skew time of synchronizing signal on the described actual pcb plate, the gained merchant is the minimum single time delay circuit unit number of the main control end compensation that needs to arrange.
7. system as claimed in claim 5 is characterized in that, described delay circuit arranges the unit and comprises:
Timing skew time required delay circuit number determination module be used for to be determined the needed single time delay circuit unit number of timing skew time with each synchronizing signal of the fabric swatch design of pcb plate behind the step calibration;
Single delay circuit serial module structure, be used for the minimum single time delay circuit unit number in conjunction with the compensation of described main control end, the needed single time delay circuit unit number of timing skew time of each synchronizing signal of described fabric swatch design with pcb plate behind the step calibration is carried out tandem compound, to obtain the delay circuit with the main control end of the synchronizing signal of the fabric swatch design of the pcb plate behind the step calibration.
8. as each described system of claim 5 to 7, it is characterized in that described system comprises:
The timing skew compensating unit is used for the terminal that described pcb plate is installed is carried out timing sequence test, and according to timing skew time of the described pcb plate of test result correction synchronizing signal.
9. a ddr series pcb plate sequential compensation terminal is characterized in that, described terminal comprises the described ddr series of 5 to 8 each claims pcb plate sequential bucking-out system.
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| CN103257309B (en) | 2015-10-07 |
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