CN110888040A - Signal link fault simulation test method - Google Patents

Abstract

The invention discloses a signal link fault simulation test method, which comprises the steps of establishing an element model library according to a PCB (printed circuit board) laminate, designing a simulation tool for each laminate in the element model library, wherein the simulation tool is internally provided with a plurality of attribute items, and the attribute items comprise layer thickness, line width and dielectric constant of a material; performing pre-simulation design on theoretical signals through a simulation tool, defining a topological structure of the signals, selecting an element value interval, and selecting a reasonable layout and wiring strategy; carrying out fault simulation test analysis after completing the wiring of the PCB laminate according to the pre-simulation design; carrying out relaxation rule setting through a simulation tool to obtain a post-simulation design, and carrying out analog analysis and adjustment on a finished signal wire which does not conform to a pre-simulation design; and comparing the performance parameters in the signal transmission process with the post-simulation design, and positioning the fault point. According to the invention, the establishment of the element model library is combined with a simulation tool, so that the occupied space is reduced, and the integrity of signal link detection is realized; the cost is low, and the detection is convenient and easy.

Description

Signal link fault simulation test method

Technical Field

The invention relates to a signal link fault simulation test method, and belongs to the technical field of signal link fault detection.

Background

With the rapid development of digital circuits, the transmission rate of signals is continuously improved, the transmission frequency of signals is continuously increased, and the transmission line delay of signals has an increasingly large influence on the overall performance of the digital circuits, and gradually becomes a key factor for determining the quality of signals, particularly mainly including the reflection of the signals, crosstalk between the signals, the delay of signal transmission and the like, so that the analog detection of signal link faults is particularly important.

The crosstalk of the computer module is mainly caused by the mutual inductance between signals or the noise on a line caused by the mutual capacitance characteristic, the mutual inductance between the signals mainly causes coupling voltage, the mutual capacitance between the signals mainly causes coupling current, and if the noise exceeds a design threshold value, the noise may cause the malfunction of a rear-stage circuit, thereby affecting the normal work of the system. If the delay of signal transmission exceeds a design threshold, a control sequence error may be caused, so that a function error of a component is influenced, and the normal work of a system is finally influenced.

At present, most of signal link fault simulation detection is input and output signal comparison, the traditional comparison analysis is long in time consumption and incomplete in signal link analysis, and fault points are efficiently checked.

Disclosure of Invention

The invention aims to solve the defects of the prior art, and provides a signal link fault simulation test method aiming at the problems of low efficiency and high cost of the traditional input and output signal comparison analysis.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a signal link fault simulation test method comprises the following steps:

establishing a component model library according to the PCB layer plate,

designing a simulation tool for each laminate in an element model library, wherein the simulation tool is internally provided with a plurality of attribute items, and the attribute items comprise layer thickness, line width and dielectric constant of a material;

performing pre-simulation design on theoretical signals through a simulation tool, defining a topological structure of the signals, selecting an element value interval, and selecting a reasonable layout and wiring strategy;

carrying out fault simulation test analysis after completing the wiring of the PCB laminate according to the pre-simulation design;

carrying out relaxation rule setting through a simulation tool to obtain a post-simulation design, and carrying out analog analysis and adjustment on a finished signal wire which does not conform to a pre-simulation design;

and comparing the performance parameters in the signal transmission process with the post-simulation design, and positioning the fault point.

The invention has the following beneficial effects: the establishment of the element model library is combined with a simulation tool, so that on one hand, the occupied space is reduced, and the integrity of signal link detection is realized; on the other hand, the cost is low, the detection is convenient and easy, and the reliability is high.

Drawings

FIG. 1 is a schematic diagram of a library of component models in the present invention.

Fig. 2 is a diagram of an original waveform of the SDRAM terminal at the time of troubleshooting in the present invention.

Fig. 3 is an original waveform diagram of the CPU side at the time of troubleshooting in the present invention.

Detailed Description

The invention provides a signal link fault simulation test method. The technical solution of the present invention is described in detail below with reference to the accompanying drawings so that it can be more easily understood and appreciated.

A signal link fault simulation test method is disclosed, as shown in figure 1, a PCB layer board is 10 layers, an element model library in the scheme is shown in figure 1, a simulation tool for each layer board is designed in the element model library, the simulation tool is internally provided with a plurality of attribute items, the attribute items comprise layer thickness, line width, dielectric constant of materials and the like, and impedance control of each layer is restricted to 50 ohms.

The method comprises the steps of performing pre-simulation design on theoretical signals through a simulation tool, defining a topological structure of the signals, selecting element value intervals and selecting a reasonable layout and wiring strategy.

And (4) carrying out fault simulation test analysis after wiring of the PCB laminate is finished according to the pre-simulation design, and meeting the requirements when the PCB laminate is qualified. And obtaining the troubleshooting without faults.

And (3) setting a relaxation rule through a simulation tool to obtain a post-simulation design, performing simulation analysis and adjustment on the finished signal wire which is not in line with the pre-simulation design, comparing the performance parameters with the post-simulation design in the signal transmission process, and positioning a fault point.

When signal link fault simulation detection is carried out, the thickness, the line width, the dielectric constant of materials and simulation parameters of each layer which are arranged in a laminated mode need to be set, a high-speed signal line on a computer module mainly comprises a data line, an address line and a control line from a CPU to an SDRAM, and due to the fact that topological structures of the data line and the address line of the SDRAM are not identical, simulation can be carried out by referring to a single board design and selecting the data line, the address line and the control line representing different topological structures for simulation. The data and address lines were simulated at a frequency of 80M and the control lines at a frequency of 30M.

The main means for signal link fault simulation test analysis is signal simulation, which can be divided into pre-simulation design and post-simulation design according to the simulation purpose and the stage of signal simulation in the process of making edition. The method has the advantages that the effective pre-design simulation of the signals is carried out by utilizing a simulation tool through the element model library, the topological structure of the signals can be favorably defined, the element value interval can be favorably selected, and the reasonable layout and wiring strategy can be favorably selected. The post-simulation design is simulation analysis work performed after the wiring of the PCB is completed, and the purpose is mainly to adjust and relax rule setting through simulation analysis on finished signal wires which do not conform to set rules. And various performance parameters in the signal transmission process are analyzed and compared, and fault points are positioned more quickly.

When parameter analysis is performed, as shown in fig. 2 and 3, when data is sent to the SDRAM by the CPU, an original signal is superimposed with a signal reflected from the FPGA, and oscillation is formed at a rising edge of the signal. Meanwhile, although the time delay is small in the signal transmission process, the waveform distortion degree is high, and the fault point can be quickly positioned.

According to the signal link fault simulation test method disclosed by the invention, the element model library is established and combined with the simulation tool, so that on one hand, the occupied space is reduced, and the integrity of signal link detection is realized; on the other hand, the cost is low, the detection is convenient and easy, and the reliability is high.

The technical solutions of the present invention are fully described above, it should be noted that the specific embodiments of the present invention are not limited by the above description, and all technical solutions formed by equivalent or equivalent changes in structure, method, or function according to the spirit of the present invention by those skilled in the art are within the scope of the present invention.

Claims (1)

1. A signal link fault simulation test method is characterized by comprising the following steps:

establishing a component model library according to the PCB layer plate,

designing a simulation tool for each laminate in an element model library, wherein the simulation tool is internally provided with a plurality of attribute items, and the attribute items comprise layer thickness, line width and dielectric constant of a material;

performing pre-simulation design on theoretical signals through a simulation tool, defining a topological structure of the signals, selecting an element value interval, and selecting a reasonable layout and wiring strategy;

carrying out fault simulation test analysis after completing the wiring of the PCB laminate according to the pre-simulation design;

carrying out relaxation rule setting through a simulation tool to obtain a post-simulation design, and carrying out analog analysis and adjustment on a finished signal wire which does not conform to a pre-simulation design;

and comparing the performance parameters in the signal transmission process with the post-simulation design, and positioning the fault point.

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