CN108763717A - A kind of high speed link signal integrality fast evaluation method and system - Google Patents
A kind of high speed link signal integrality fast evaluation method and system Download PDFInfo
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Abstract
A kind of high speed link signal integrality fast evaluation method of present invention offer and system, the method includes：S1, select the similar type topology by test correction as with reference to topology；S2, modeling and simulating is carried out respectively based on present topology and with reference to topology；S3, analysis comparison present topology and the simulation result with reference to topology.The present invention solves the problems, such as to assess poor in timeliness for high speed link signal completeness simulation in the prior art, realizes and complete, to the Simulation Evaluation of high-speed link, utmostly to race against time for link design and optimization within a short period of time, improve timeliness.This method takes full advantage of the data of historical accumulation, can rapid evaluation similar link design risk, improve high-speed link assessment efficiency, for Project design optimization striven for more times.
Description
Technical field
The present invention relates to high speed signal technical field, especially a kind of high speed link signal integrality fast evaluation method with
System.
Background technology
In the design of conventional digital system, high speed interconnects phenomenon and usually can be ignored, because in conventional digital system
In, the influence to system performance is very faint.However, with the continuous development of computer technology, in numerous decision systems
In the factor of energy, high speed interconnects phenomenon and just plays leading role, frequently results in the appearance of some unpredictable problems, greatly
Increase the complexity of system design.Therefore, in high-speed link design, to optimize modules as possible, by emulation tool
Assessment design feasibility and risk point in advance, and according to simulation result optimization design, system design success rate is improved, shortening is ground
Send out the period.During server system high speed signal link design, generally require to be based on the timely Adjusted Option of simulation result, item
The SI evaluation stages of phase more early discovery at present and avoid high speed signal problem, can be designed for system strive for more times and
Allowance has extremely strong timeliness.
It is directed to high speed link signal integrity assessment now, is largely all based on the worst feelings that current design finds design
Condition is compared, if worst condition energy by indexs such as loss, reflection and the eye parameters of emulation worst condition with industrial specification
Enough meet design requirement, then link evaluation low-risk.
Although this assessment thought can ensure the accuracy of assessment, but it is difficult to realize in practical operation.It is seeking
When looking for design worst condition, factor needed to be considered is more.Such as：Link design length, pcb board factory make tolerance, chip
Energy, environment influence etc..Wherein, some factors are difficult to be indicated with accurate model, can only approximate processing.Moreover, this appraisal procedure
It is time-consuming longer, greatly reduce the timeliness of link evaluation.
Invention content
The object of the present invention is to provide a kind of high speed link signal integrality fast evaluation method and systems, it is intended to solve existing
There are the problem of assessing poor in timeliness for high speed link signal completeness simulation in technology, realization to be completed within a short period of time to height
The Simulation Evaluation of speed chain circuit, utmostly races against time for link design and optimization, improves timeliness.
To reach above-mentioned technical purpose, the present invention provides a kind of high speed link signal integrality fast evaluation method, packets
It includes：
S1, select the similar type topology by test correction as with reference to topology；
S2, modeling and simulating is carried out respectively based on present topology and with reference to topology；
S3, analysis comparison present topology and the simulation result with reference to topology.
Preferably, the similar type topology is specially that composed structure is identical, but linkage length, crosses hole site and PCB materials
Material is different.
Preferably, the modeling and simulating is based under representative condition, the impedance of cabling, loss standards, the drive characteristic of chip,
External environmental parameter is representative value.
Preferably, the modeling and simulating includes passive emulation and active emulation.
Preferably, in the active simulation process, linkage length is traversed by fixed step size in certain section, when traversal is tied
Fruit is satisfied by when requiring, and can just assess and pass through.
The present invention also provides a kind of high speed link signal integrality RES(rapid evaluation system)s, including：
With reference to topological selecting module, for selecting the similar type topology by test correction as with reference to topology；
Modeling and simulating module, for being based on present topology and carrying out modeling and simulating respectively with reference to topology；
Analysis of simulation result module, for analyzing comparison present topology and with reference to the simulation result of topology.
Preferably, the similar type topology is specially that composed structure is identical, but linkage length, crosses hole site and PCB materials
Material is different.
Preferably, the modeling and simulating is based under representative condition, the impedance of cabling, loss standards, the drive characteristic of chip,
External environmental parameter is representative value.
Preferably, the modeling and simulating module includes：
Passive simulation unit, for carrying out passive emulation based on present topology and with reference to topology；
Active simulation unit, for carrying out active emulation based on present topology and with reference to topology.
The effect provided in invention content is only the effect of embodiment, rather than invents all whole effects, above-mentioned
A technical solution in technical solution has the following advantages that or advantageous effect：
Compared with prior art, the present invention is by opening up current design link topology with by the similar reference of test verification
It flutters and compares, the canonical parameter based on respective link carries out contrast simulation, is compared and analyzed by the result of the two, and then fast
Speed assessment link risk.It solves the problems, such as to assess poor in timeliness for high speed link signal completeness simulation in the prior art,
Realization is completed, to the Simulation Evaluation of high-speed link, utmostly to race against time, carry for link design and optimization within a short period of time
High-timeliness.This method takes full advantage of the data of historical accumulation, can rapid evaluation similar link design risk, improve height
Speed chain circuit assesses efficiency, has striven for more times for Project design optimization.
Description of the drawings
Fig. 1 is a kind of high speed link signal integrality fast evaluation method flow chart provided in the embodiment of the present invention；
Fig. 2 is a kind of current design link topology schematic diagram provided in the embodiment of the present invention；
Fig. 3 is a kind of reference link topological structure schematic diagram provided in the embodiment of the present invention；
Fig. 4 is the passive simulation result schematic diagram of link signal provided in the embodiment of the present invention；
Fig. 5 is a kind of high speed link signal integrality RES(rapid evaluation system) structural frames provided in the embodiment of the present invention
Figure.
Specific implementation mode
In order to clearly illustrate the technical characterstic of this programme, below by specific implementation mode, and its attached drawing is combined, to this
Invention is described in detail.Following disclosure provides many different embodiments or example is used for realizing the different knots of the present invention
Structure.In order to simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.In addition, the present invention can be with
Repeat reference numerals and/or letter in different examples.This repetition is that for purposes of simplicity and clarity, itself is not indicated
Relationship between various embodiments and/or setting is discussed.It should be noted that illustrated component is not necessarily to scale in the accompanying drawings
It draws.Present invention omits the descriptions to known assemblies and treatment technology and process to avoid the present invention is unnecessarily limiting.
It is provided for the embodiments of the invention a kind of high speed link signal integrality fast evaluation method below in conjunction with the accompanying drawings
It is described in detail with system.
As shown in Figure 1, the embodiment of the invention discloses a kind of high speed link signal integrality fast evaluation methods, including with
Lower step：
S1, select the similar type topology by test correction as with reference to topology；
According to the topological structure of current high-speed link, more similar opening up of the selection by test verification from preliminary project
In flutterring, select the topological structure of similar type as with reference to topology.
As shown in Fig. 2, certain PCIE simplifies in link, mainboard transmitting chip, to connector, then passes through switching through mainboard cabling
Plate is connected to backboard, eventually arrives at terminal hard disk, and each section of track lengths and via distribution situation have been marked in figure.
By comparing topological structure, from being found in preliminary project in the more similar topology by test verification, select
The topological structure of same type is used as with reference to topology, and the selected composed structure with reference to topology is identical.With reference to topology as shown in figure 3,
Reference topology is also to be made of mainboard, pinboard, backboard and hard disk, and difference is linkage length, crosses hole site and PCB materials
Material etc..
S2, modeling and simulating is carried out respectively based on present topology and with reference to topology；
It will be emulated under respective representative condition with reference to the topology of topology and current high-speed link.By the impedance of cabling with
And loss standards, the drive characteristic of chip, external environmental parameter etc. all select representative value, and modeling and simulating is carried out after setting.
By taking PCB trace as an example, current design selects the typical loss indexs of material for 0.58db/inch@4G Hz, and joins
The typical loss indexs for examining topology design the selection of material are 0.65db/inch@4G Hz, are built respectively according to corresponding index respectively
The PCB trace model of vertical present topology and reference topology.Each section model (via and connector etc.) in link has been established
It can be carried out passive and active emulation after.
S3, analysis comparison present topology and the simulation result with reference to topology；
Passive emulation is as shown in figure 4, it can be seen from the figure that the sourceless characteristic of the topology of current design is opened up better than reference
It flutters.
Active emulation is as shown in table 1, when carrying out active emulation, the influence in order to avoid resonance to simulation result, it is proposed that
Linkage length is traversed in suitable interval, according to the step-length of 0.1inch, is traversed from original length L to L-0.5inch, when time
Going through can just think that assessment result is reliable when result all meets design requirement.In traversal section, current design is superior to refer to and open up
Flutter, and refer to topology and meet design requirement in testing early period, thus can be based on above-mentioned evaluation of simulation result link risk compared with
It is low.
Table 1
The embodiment of the present invention being compared by the similar topology that refers to verified by current design link topology and by test,
Canonical parameter based on respective link carries out contrast simulation, is compared and analyzed by the result of the two, and then rapid evaluation chain
Transportation work style danger.Solve the problems, such as in the prior art for high speed link signal completeness simulation assess poor in timeliness, realize compared with
It completes, to the Simulation Evaluation of high-speed link, utmostly to race against time for link design and optimization, improve timeliness in short time.
This method takes full advantage of the data of historical accumulation, can rapid evaluation similar link design risk, improve high-speed link and comment
Estimate efficiency, strives for more times for Project design optimization.
As shown in figure 5, the embodiment of the invention also discloses a kind of high speed link signal integrality RES(rapid evaluation system), packet
It includes：
With reference to topological selecting module, for selecting the similar type topology by test correction as with reference to topology；
By comparing topological structure, from being found in preliminary project in the more similar topology by test verification, select
The topological structure of same type is used as with reference to topology, and the selected composed structure with reference to topology is identical.
Modeling and simulating module, for being based on present topology and carrying out modeling and simulating respectively with reference to topology；
It will be emulated under respective representative condition with reference to the topology of topology and current high-speed link.By the impedance of cabling with
And loss standards, the drive characteristic of chip, external environmental parameter etc. all select representative value.
Analysis of simulation result module, for analyzing comparison present topology and with reference to the simulation result of topology.
The modeling and simulating module includes：
Passive simulation unit, for carrying out passive emulation based on present topology and with reference to topology；
Active simulation unit, for carrying out active emulation based on present topology and with reference to topology.
When carrying out active emulation, the influence in order to avoid resonance to simulation result, it is proposed that by linkage length in suitable area
Interior traversal is traversed from original length L to L-0.5inch according to the step-length of 0.1inch, is wanted when traversing result all meets design
It can just think that assessment result is reliable when asking.
The similar type topology is specially that composed structure is identical, but linkage length, excessively hole site and PCB material are different.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement etc., should all be included in the protection scope of the present invention made by within refreshing and principle.
Claims (9)
1. a kind of high speed link signal integrality fast evaluation method, which is characterized in that including：
S1, select the similar type topology by test correction as with reference to topology；
S2, modeling and simulating is carried out respectively based on present topology and with reference to topology；
S3, analysis comparison present topology and the simulation result with reference to topology.
2. a kind of high speed link signal integrality fast evaluation method according to claim 1, which is characterized in that the phase
It is specially that composed structure is identical, but linkage length, excessively hole site and PCB material are different like type topology.
3. a kind of high speed link signal integrality fast evaluation method according to claim 1, which is characterized in that described to build
It imitates very based under representative condition, the impedance of cabling, l oss standards, the drive characteristic of chip, external environmental parameter are typical case
Value.
4. a kind of high speed link signal integrality fast evaluation method according to claim 1 or 3, which is characterized in that institute
It includes passive emulation and active emulation to state modeling and simulating.
5. a kind of high speed link signal integrality fast evaluation method according to claim 4, which is characterized in that described to have
In the simulation process of source, linkage length is traversed by fixed step size in certain section, when traversing result, which is satisfied by, to be required, can just be commented
Estimate and passes through.
6. a kind of high speed link signal integrality RES(rapid evaluation system), which is characterized in that including：
With reference to topological selecting module, for selecting the similar type topology by test correction as with reference to topology；
Modeling and simulating module, for being based on present topology and carrying out modeling and simulating respectively with reference to topology；
Analysis of simulation result module, for analyzing comparison present topology and with reference to the simulation result of topology.
7. a kind of high speed link signal integrality RES(rapid evaluation system) according to claim 6, which is characterized in that the phase
It is specially that composed structure is identical, but linkage length, excessively hole site and PCB material are different like type topology.
8. a kind of high speed link signal integrality RES(rapid evaluation system) according to claim 7, which is characterized in that described to build
It imitates very based under representative condition, the impedance of cabling, l oss standards, the drive characteristic of chip, external environmental parameter are typical case
Value.
9. a kind of high speed link signal integrality RES(rapid evaluation system) according to claim 6 or 8, which is characterized in that institute
Stating modeling and simulating module includes：
Passive simulation unit, for carrying out passive emulation based on present topology and with reference to topology；
Active simulation unit, for carrying out active emulation based on present topology and with reference to topology.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109325319A (en) * | 2018-12-04 | 2019-02-12 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of high-speed serial bus passive link automatic optimization method |
| CN110362438A (en) * | 2019-07-18 | 2019-10-22 | 浪潮商用机器有限公司 | A kind of bus performance detection method, device, equipment and readable storage medium storing program for executing |
| CN110532654A (en) * | 2019-08-16 | 2019-12-03 | 苏州浪潮智能科技有限公司 | The method and apparatus that parameter determines on a kind of printing board PCB plate |
| CN110888040A (en) * | 2019-11-28 | 2020-03-17 | 苏州长风航空电子有限公司 | Signal link fault simulation test method |
| CN111475355A (en) * | 2020-03-20 | 2020-07-31 | 苏州浪潮智能科技有限公司 | High-speed link signal integrity evaluation method, system, terminal and storage medium |
| CN112446182A (en) * | 2020-11-27 | 2021-03-05 | 苏州浪潮智能科技有限公司 | Method and equipment for optimizing signal integrity |
| CN115827495A (en) * | 2023-02-03 | 2023-03-21 | 树优(宁波)科技有限公司 | Performance evaluation method of topology optimization algorithm, related equipment and storage medium |
-
2018
- 2018-05-22 CN CN201810496734.1A patent/CN108763717A/en not_active Withdrawn
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109325319A (en) * | 2018-12-04 | 2019-02-12 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of high-speed serial bus passive link automatic optimization method |
| CN109325319B (en) * | 2018-12-04 | 2023-03-07 | 中国航空工业集团公司西安航空计算技术研究所 | Automatic optimization method for high-speed serial bus passive link |
| CN110362438A (en) * | 2019-07-18 | 2019-10-22 | 浪潮商用机器有限公司 | A kind of bus performance detection method, device, equipment and readable storage medium storing program for executing |
| CN110362438B (en) * | 2019-07-18 | 2023-05-05 | 浪潮商用机器有限公司 | Bus performance detection method, device, equipment and readable storage medium |
| CN110532654A (en) * | 2019-08-16 | 2019-12-03 | 苏州浪潮智能科技有限公司 | The method and apparatus that parameter determines on a kind of printing board PCB plate |
| CN110532654B (en) * | 2019-08-16 | 2022-09-20 | 苏州浪潮智能科技有限公司 | Method and device for determining parameters on PCB of printed circuit board |
| CN110888040A (en) * | 2019-11-28 | 2020-03-17 | 苏州长风航空电子有限公司 | Signal link fault simulation test method |
| CN111475355A (en) * | 2020-03-20 | 2020-07-31 | 苏州浪潮智能科技有限公司 | High-speed link signal integrity evaluation method, system, terminal and storage medium |
| CN112446182A (en) * | 2020-11-27 | 2021-03-05 | 苏州浪潮智能科技有限公司 | Method and equipment for optimizing signal integrity |
| CN112446182B (en) * | 2020-11-27 | 2023-04-28 | 苏州浪潮智能科技有限公司 | Method and equipment for optimizing signal integrity |
| CN115827495A (en) * | 2023-02-03 | 2023-03-21 | 树优(宁波)科技有限公司 | Performance evaluation method of topology optimization algorithm, related equipment and storage medium |
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Application publication date: 20181106 |