CN105930601B - A kind of DDR timing and delay deflection Simulation Evaluation method based on look-up table - Google Patents
A kind of DDR timing and delay deflection Simulation Evaluation method based on look-up table Download PDFInfo
- Publication number
- CN105930601B CN105930601B CN201610276784.XA CN201610276784A CN105930601B CN 105930601 B CN105930601 B CN 105930601B CN 201610276784 A CN201610276784 A CN 201610276784A CN 105930601 B CN105930601 B CN 105930601B
- Authority
- CN
- China
- Prior art keywords
- signal
- delay
- signal wire
- look
- subsegment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a kind of DDR timing and delay deflection Simulation Evaluation method based on look-up table, time stimulatiom appraisal procedure includes: 1) to carry out time stimulatiom for the signal wire of various signal transmission component types and the physical characteristic type that is delayed in advance, obtains signal wire unit length delay look-up table；2) signal wire for being analysed to signal is divided into signal wire subsegment, determines the delay physical characteristic type and wire length of each signal wire subsegment；3) it tables look-up to obtain the signal delay of each signal wire subsegment；4) the delay summation of each signal wire subsegment is obtained into total delay of signal to be analyzed；Delay deflection Simulation Evaluation method will obtain the delay deflection of total delay subtraction calculations two-way signal to be analyzed of two-way signal to be analyzed.The present invention quickly and easily can carry out Simulation Evaluation to DDR signal delay and deflection, consider the influence of unlike signal transmission part and the physical characteristic that is delayed, and provide fast and accurately timing assessment and design reference for DDR signal design.
Description
Technical field
The present invention relates to DDR time stimulatiom technologies, and in particular to a kind of DDR timing and delay deflection based on look-up table are imitative
True appraisal procedure.
Background technique
With the development of microelectric technique, the performance of microprocessor is higher and higher.In order to improve memory bandwidth, reduction processing
Performance gap between device and memory, Double Data Rate synchronous DRAM (Double Data Rate
Synchronous Dynamic Random Access Memory, DDR SDRAM) it is widely used in the interior of electronic communication system
It deposits in bus design.As typical parallel bus structure, DDR technology improves memory access speed and bandwidth, meets high speed number
According to the demand of transmission.However, DDR technology is kept updating, so that the sequence problem in system design becomes more prominent,
Stern challenge, or even the bottleneck further increased as limitation DDR transmission rate not only are proposed to system design.
In order to which the timing designed DDR in electronic product is assessed, it is imitative to need to carry out DDR timing after the design is completed
Very, to confirm whether it meets the special timing requirements of general timing requirements as defined in specification and the proposition of DDR controller producer.It presses
According to current general simulation flow, it is necessary first to extract chip package and printed circuit board (Printed Circuit Board,
PCB the DDR signal transmission line model on) then by the driver model of DDR signal, transmission line model, connector model and connects
It receives device model to connect according to corresponding topological structure, inputs certain pumping signal and solution from drive side later, it is complete
At the delay of the rear measuring receiver termination collection of letters number.For this emulation mode closest to actual conditions, precision is very high, however but very
It is cumbersome, when chip package is extracted with transmission line model on PCB, topological structure connects and time stimulatiom solution will expend a large amount of
Between.Especially when the model of emulation is complicated, signal is more, either transmission line model extract, topological structure connection or when
Sequence emulation solve needed for workload and the time it is all in exponential increase, in some instances it may even be possible to be up to a couple of days or several weeks, too long emulation into
Degree reduces the meaning of emulation.
There are biggish errors for the method for carrying out DDR timing assessment by the method for wire length calculating.This is because following
Reason: firstly, the speed that signal is propagated in transmission line, not only related to length, also with the material property phase of medium and conductor
It closes.The dielectric constant and fissipation factor of medium, conductivity and surface roughness of conductor etc. can all influence signal velocity.Its
Secondary, the geometrical characteristic of transmission line and medium also has an impact to the spread speed of signal, and the cloth such as the thickness of medium, transmission line is linear
Formula (single-ended, difference) etc..If neglecting these factors, simply by wire length computation delay, it is unable to get accurate
As a result.Especially to the signal of high transfer rate, biggish error may cause the assessment result of mistake.
In conclusion DDR time stimulatiom need to realize it is claimed below: one, it is simple and quick, can be in the shorter time
Inside obtain simulation result；Two, with certain precision, it is able to reflect out the influence of different condition and factor.Existing method without
Method realizes above-mentioned both sides demand simultaneously.
Summary of the invention
The technical problem to be solved in the present invention: in view of the above problems in the prior art, providing one kind can be quickly and easily
To include chip package and PCB on DDR signal delay and deflection carry out Simulation Evaluation, while it can be considered that unlike signal transmit
The influence to signal sequence of component and delay physical characteristic, so as to DDR signal design provide fast and accurately timing assessment and
The DDR timing and delay deflection Simulation Evaluation method based on look-up table of design reference.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention are as follows:
The present invention provides a kind of DDR time stimulatiom appraisal procedure based on look-up table, and step includes:
1) time stimulatiom is carried out for the signal wire of various signal transmission component types in advance, obtains various signal transport parts
The signal wire unit length delay look-up table of part type, the list item of the signal wire unit length delay look-up table includes specified
The delay of unit length cabling corresponding to signal transmission component type, specified delay physical characteristic type the two；
2) being analysed to the signal wire of signal according to signal transmission component Type division is signal wire subsegment, determines each letter
The delay physical characteristic type and wire length of number line subsegment；
3) it according to the delay physical characteristic type and wire length of each signal wire subsegment, compares the signal wire unit length and prolongs
When look-up table, obtain each signal wire subsegment signal delay；
4) it is summed the delay of each signal wire subsegment to obtain total delay of signal to be analyzed.
Preferably, when carrying out time stimulatiom for the signal wire of various signal transmission component types in the step 1), needle
Pair signal transmission component type include chip package base plate, PCB main board card and DIMM daughter card.
Preferably, the signal transmission component type further includes connector, chip soldered ball, is located on signal transmission path
Intermediate board between PCB main board card and DIMM daughter card.
Preferably, when carrying out time stimulatiom for the signal wire of various signal transmission component types in the step 1), needle
Time stimulatiom, the signal wire unit are carried out respectively to the various delay physical characteristic types of each signal transmission component type
Each signal transmission component type corresponds at least one list item in length delay look-up table, and each list item includes specified
The delay of unit length cabling corresponding to signal transmission component type, specified delay physical characteristic type the two.
Preferably, the delay physical characteristic type include signal wire be surface layer microstrip line, signal wire is internal layer strip line
Two kinds of cabling types.
Preferably, the delay physical characteristic type further includes the dielectric material or conductor material type that signal wire uses.
Preferably, the delay physical characteristic type further includes the geometric dimension type and surface roughness class of signal wire
Type.
Preferably, the geometric dimension type refers to the thickness type of signal wire medium or conductor.
Preferably, the detailed step of the step 3) includes:
3.1) according to the delay physical characteristic type Control signal wire unit length of each signal wire subsegment be delayed look-up table,
Determine the unit length delay of each signal wire subsegment；
3.2) function expression according to formula (1) calculates the signal delay of each signal wire subsegment；
DelayAi=LengthAi·DAi(1)
In formula (1),DelayAiIndicate signal to be analyzediThe signal of a signal wire subsegment is delayed,LengthAiIndicate to
Analyze signal theiThe wire length of a signal wire subsegment,DAiIndicate signal to be analyzediThe unit length of a signal wire subsegment is delayed.
The DDR timing delay deflection Simulation Evaluation method based on look-up table that the present invention also provides a kind of, step include:
I the aforementioned DDR time stimulatiom appraisal procedure based on look-up table) is used, obtains the total of two-way signal to be analyzed respectively
Delay；
II) total delay of two-way signal to be analyzed is subtracted each other, obtains the delay deflection between two-way signal to be analyzed.
The present invention is based on the DDR time stimulatiom appraisal procedures of look-up table to have an advantage that the present invention in formal emulation
Assessment can emulate unlike signal transmission part and delay physical characteristic type before starting, and complete signal wire unit
Relevant information in length delay look-up table；It, only need to be to each signal transmission component of signal to be analyzed when Simulation Evaluation starts
Delay physical characteristic type and wire length counted, control signal line unit length delay look-up table obtains data, carries out letter
Corresponding signal delay and delay skew results can be obtained in single calculating.It needs to carry out model extraction with general emulation, open up
Flutter build, timing solution is compared with the whole process of Time delay measurement, substantially increases simulation efficiency, shorten the progress of emulation and multiple
Miscellaneous degree；Compared with the appraisal procedure only calculated by wire length, influence of the wire length to delay is not only allowed for, while also contemplating Jie
The material and geometrical property of matter and conductor, therefore result is more accurate, for higher signal transmission rate will not cause compared with
Big error ensure that the precision of Simulation Evaluation.Present invention incorporates general Whole Process Simulations and wire length to calculate appraisal procedure
Advantage compromises to simulation velocity and precision.Further, since the result of look-up table only need to be emulated once, so that it may it is used for multiple times,
It is highly convenient for iteration optimization.
It is that the present invention is based on the DDR of look-up table the present invention is based on the DDR timing of look-up table delay deflection Simulation Evaluation method
Time stimulatiom appraisal procedure is calculating the application in signal delay and two paths of signals delay deflection, and it includes the present invention is based on lookups
Whole technological means of the DDR time stimulatiom appraisal procedure of table, therefore equally also with the present invention is based on the DDR timing of look-up table
The aforementioned advantages of Simulation Evaluation method, therefore details are not described herein.
Detailed description of the invention
Fig. 1 is the basic procedure schematic diagram of one method of the embodiment of the present invention.
Fig. 2 is the cabling schematic diagram of signal to be analyzed in the embodiment of the present invention one.
Fig. 3 is the table schematic diagram of signal wire unit length delay look-up table in the embodiment of the present invention one.
Fig. 4 is the wire length table schematic diagram of each signal wire subsegment determined in the embodiment of the present invention one.
Specific embodiment
Embodiment one:
As shown in Figure 1, the present embodiment based on look-up table DDR time stimulatiom appraisal procedure the step of include:
1) time stimulatiom is carried out for the signal wire of various signal transmission component types in advance, obtains various signal transport parts
The signal wire unit length delay look-up table of part type, the list item of the signal wire unit length delay look-up table includes specified
The delay of unit length cabling corresponding to signal transmission component type, specified delay physical characteristic type the two；
2) being analysed to the signal wire of signal according to signal transmission component Type division is signal wire subsegment, determines each letter
The delay physical characteristic type and wire length of number line subsegment；
3) it according to the delay physical characteristic type and wire length of each signal wire subsegment, compares the signal wire unit length and prolongs
When look-up table, obtain each signal wire subsegment signal delay；
4) it is summed the delay of each signal wire subsegment to obtain total delay of signal to be analyzed.
In the present embodiment, when carrying out time stimulatiom for the signal wire of various signal transmission component types in step 1), needle
Pair signal transmission component type include chip package base plate, PCB main board card and DIMM daughter card.Referring to fig. 2, DDR is deposited
1., chip package base the signal wire B of certain signal all the way on chip A is stored up, cabling includes three kinds of signal transmission component types:
Plate；2., PCB main board card；3., DIMM daughter card.It should be noted that due to the various aspects such as design, manufacturing process, core
The signal wire of piece package substrate, the signal wire of PCB main board card, DIMM daughter card signal wire three used by medium and conductor
Material property is usually different, but unquestionably, it can according to need using two kinds very aforementioned three kinds of signal wires
To same medium and conductor material, equally it is readily applicable to the present embodiment and is assessed based on the DDR time stimulatiom of look-up table
Method, only the classification quantity of signal transmission component type may different from, and then cause signal wire unit length be delayed
Signal transmission component type in look-up table is reduced, but its basic principle and the present embodiment are essentially identical, therefore herein not
It repeats again.In addition, carrying out time stimulatiom using 3 D electromagnetic field solver (such as HFSS, 3D-FEM) in the present embodiment.
In the present embodiment, when carrying out time stimulatiom for the signal wire of various signal transmission component types in step 1), needle
Pair signal transmission component type further include connector and chip soldered ball, in addition to chip package base plate, PCB main board card, DIMM
Other than board, connector, chip soldered ball is also comprehensively considered, have been located at PCB main board card and DIMM daughter card on signal transmission path
Between three kinds of different signal transmission components of intermediate board, completely to consider the transmission details of DDR clock signal, thus
Ensure the accuracy of DDR time stimulatiom assessment.It should be noted that being located on connector, chip soldered ball, signal transmission path
These three signal transmission components of intermediate board between PCB main board card and DIMM daughter card are not the option that must be selected, example
Such as during calculating two paths of signals delay deflection, the delay factor of above-mentioned three kinds of signal transmission components can be supported mutually
Disappear, result is not had an impact, so as to not consider that two kinds of signal transmission components of connector and chip soldered ball are delayed to signal
Influence.
In the present embodiment, when carrying out time stimulatiom for the signal wire of various signal transmission component types in step 1), needle
Time stimulatiom, the signal wire unit are carried out respectively to the various delay physical characteristic types of each signal transmission component type
Each signal transmission component type corresponds at least one list item in length delay look-up table, and each list item includes specified
The delay of unit length cabling corresponding to signal transmission component type, specified delay physical characteristic type the two.Unquestionably,
The physical characteristic classification of type that is delayed is more detailed, then will be more accurate for the time stimulatiom of the signal, subsequent in control signal line
When unit length delay look-up table, so that it may obtain more accurate delay product.
In the present embodiment, delay physical characteristic type include signal wire be surface layer microstrip line, signal wire is internal layer strip line
Two kinds of cabling types, referring to Fig. 3, it is that surface layer microstrip line (is simply expressed as in Fig. 3 that each signal transmission component, which corresponds to signal wire,
" microstrip line "), internal layer strip line (" strip line " is simply expressed as in Fig. 3) have a project, the unit of project data is ps/
mm.It should be noted that only listing chip package base plate, PCB main board card and DIMM daughter card to simplify the explanation, in Fig. 3
Three kinds of type of dielectric material are illustrated, and in the case where expressing complete situation, signal wire unit length delay look-up table should be wrapped also
Include connector, chip soldered ball two arranges.It should be noted that only listing signal wire to simplify the explanation, in Fig. 3 is surface layer micro-strip
Line, signal wire are two kinds of delay physical characteristic types of internal layer strip line, and in the case where expressing complete situation, signal wire unit length is prolonged
When look-up table should further include row using the signal wire of other media material, conductor material or geometric dimension.
In the present embodiment, delay physical characteristic type further include signal wire use dielectric material or conductor material type,
Geometric dimension type of signal wire etc. and surface roughness type.In the present embodiment, geometric dimension type refer to signal wire medium or
The thickness type of conductor.Referring to Fig. 3 and Fig. 4, dielectric material or conductor material type are divided into low loss dielectric, middle lossy medium again
With high lossy medium, surface roughness type includes low roughness, middle roughness and high roughness.It should be noted that above-mentioned
It can be between different types independently of each other, be also possible to be combined with each other, can specifically be passed due to the signal of required consideration
The manufacturing process of defeated unit type is different and different.Such as in the present embodiment, chip package base plate include at least microstrip line,
Three kinds of strip line, low loss dielectric strip line delay physical characteristic types, PCB main board card include at least microstrip line, low roughness
Three kinds of microstrip line, strip line delay physical characteristic types.
After step 2 determines the wire length of each signal wire subsegment in the present embodiment, table shown in available Fig. 4, each
Project indicates a certain corresponding wire length of physical characteristic type that is delayed, unit mm under a certain signal transmission component type.It needs
It is noted that the table of Fig. 4 is still in simplified form, it is omitted using other media material, conductor material or geometric dimension
Signal wire row.
In the present embodiment, the detailed step of step 3) includes:
3.1) it according to the type of wiring control signal line unit length of each signal wire subsegment delay look-up table, determines each
The unit length of signal wire subsegment is delayed；
3.2) function expression according to formula (1) calculates the signal delay of each signal wire subsegment；
DelayAi=LengthAi·DAi(1)
In formula (1),DelayAiIndicate signal to be analyzediThe signal of a signal wire subsegment is delayed,LengthAiIndicate to
Analyze signal theiThe wire length of a signal wire subsegment,DAiIndicate signal to be analyzediThe unit length of a signal wire subsegment is delayed.
The present embodiment step 1) is carried out and is completed before assessment starts, and is not counted in assessment progress, is not produced to assessment progress
It is raw to influence, so as to greatly improve the efficiency of DDR timing assessment.And when carrying out the assessment of DDR timing, the present embodiment is adopted
With the method for signal wire unit length delay look-up table, only analysis type of wiring and wire length more accurate imitate can be obtained
Very as a result, need to carry out cumbersome setting instead of previous DDR signal time stimulatiom every time, it is low to solve previous simulation efficiency
Problem can be widely applied to the field EDA as a kind of quick DDR signal time stimulatiom method.
Embodiment two:
Different from embodiment one, the present embodiment is on the basis of example 1, further to be based on searching by embodiment one
The DDR time stimulatiom appraisal procedure of table is calculating the application in two paths of signals delay deflection.
DDR timing delay deflection Simulation Evaluation method of the present embodiment based on look-up table, step includes: I) using the present invention
The aforementioned DDR time stimulatiom appraisal procedure based on look-up table obtains total delay of two-way signal to be analyzed respectively；II) by two-way
Total delay of signal to be analyzed is subtracted each other, and the delay deflection (unit ps) between two-way signal to be analyzed is obtained.
In addition, in the present embodiment method, connector, chip soldered ball are not considered, is located at PCB main board on signal transmission path
The influence that three kinds of signal transmission components of intermediate board between card and DIMM daughter card are delayed to signal, this is because believing calculating
In delay deflection between number, these factors can cancel out each other, and not have an impact to result.
The above is only a preferred embodiment of the present invention, protection scope of the present invention is not limited merely to above-mentioned implementation
Example, all technical solutions belonged under thinking of the present invention all belong to the scope of protection of the present invention.It should be pointed out that for the art
Those of ordinary skill for, several improvements and modifications without departing from the principles of the present invention, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of DDR time stimulatiom appraisal procedure based on look-up table, it is characterised in that step includes:
1) time stimulatiom is carried out for the signal wire of various signal transmission component types in advance, obtains various signal transmission component classes
The signal wire unit length delay look-up table of type, the list item of the signal wire unit length delay look-up table includes specified signal
The delay of unit length cabling corresponding to transmission part type, specified delay physical characteristic type the two；
2) being analysed to the signal wire of signal according to signal transmission component Type division is signal wire subsegment, determines each signal wire
The delay physical characteristic type and wire length of subsegment；
3) it according to the delay physical characteristic type and wire length of each signal wire subsegment, compares the signal wire unit length delay and looks into
Table is looked for, the signal delay of each signal wire subsegment is obtained；
4) it is summed the delay of each signal wire subsegment to obtain total delay of signal to be analyzed.
2. the DDR time stimulatiom appraisal procedure according to claim 1 based on look-up table, which is characterized in that the step
1) in for various signal transmission component types signal wire carry out time stimulatiom when, for signal transmission component type include
Chip package base plate, PCB main board card and DIMM daughter card.
3. the DDR time stimulatiom appraisal procedure according to claim 2 based on look-up table, which is characterized in that the signal
Transmission part type further include connector, chip soldered ball, on signal transmission path between PCB main board card and DIMM daughter card
Intermediate board.
4. the DDR time stimulatiom appraisal procedure according to claim 3 based on look-up table, which is characterized in that the step
1) when carrying out time stimulatiom for the signal wire of various signal transmission component types in, for each signal transmission component type
Various delay physical characteristic types carry out time stimulatiom respectively, each letter in the signal wire unit length delay look-up table
Number transmission part type corresponds at least one list item, and each list item include specified signal transmission component type, it is specified
The delay of unit length cabling corresponding to the physical characteristic type the two that is delayed.
5. the DDR time stimulatiom appraisal procedure according to claim 4 based on look-up table, which is characterized in that the delay
Physical characteristic type include signal wire be surface layer microstrip line, signal wire is two kinds of cabling types of internal layer strip line.
6. the DDR time stimulatiom appraisal procedure according to claim 5 based on look-up table, which is characterized in that the delay
Physical characteristic type further includes the dielectric material or conductor material type that signal wire uses.
7. the DDR time stimulatiom appraisal procedure according to claim 6 based on look-up table, which is characterized in that the delay
Physical characteristic type further includes the geometric dimension type and surface roughness type of signal wire.
8. the DDR time stimulatiom appraisal procedure according to claim 7 based on look-up table, which is characterized in that the geometry
Dimension Types refer to the thickness type of signal wire medium or conductor.
9. the DDR time stimulatiom appraisal procedure described according to claim 1~any one of 8 based on look-up table, feature
It is, the detailed step of the step 3) includes:
3.1) it according to the delay physical characteristic type Control signal wire unit length of each signal wire subsegment delay look-up table, determines
The unit length of each signal wire subsegment is delayed；
3.2) function expression according to formula (1) calculates the signal delay of each signal wire subsegment；
DelayAi=LengthAi·DAi(1)
In formula (1),DelayAiIndicate signal to be analyzediThe signal of a signal wire subsegment is delayed,LengthAiIndicate to be analyzed
SignaliThe wire length of a signal wire subsegment,DAiIndicate signal to be analyzediThe unit length of a signal wire subsegment is delayed.
A kind of deflection Simulation Evaluation method 10. DDR timing based on look-up table is delayed, it is characterised in that step includes:
I it) using the DDR time stimulatiom appraisal procedure based on look-up table described in any one of claim 1~9, obtains respectively
Take total delay of two-way signal to be analyzed；
II) total delay of two-way signal to be analyzed is subtracted each other, obtains the delay deflection between two-way signal to be analyzed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610276784.XA CN105930601B (en) | 2016-04-29 | 2016-04-29 | A kind of DDR timing and delay deflection Simulation Evaluation method based on look-up table |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610276784.XA CN105930601B (en) | 2016-04-29 | 2016-04-29 | A kind of DDR timing and delay deflection Simulation Evaluation method based on look-up table |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105930601A CN105930601A (en) | 2016-09-07 |
| CN105930601B true CN105930601B (en) | 2019-03-29 |
Family
ID=56837550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610276784.XA Active CN105930601B (en) | 2016-04-29 | 2016-04-29 | A kind of DDR timing and delay deflection Simulation Evaluation method based on look-up table |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105930601B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109086546B (en) * | 2018-08-22 | 2021-10-29 | 郑州云海信息技术有限公司 | Signal link signal quality evaluation method, device, equipment and readable storage medium |
| CN112183006A (en) * | 2019-07-02 | 2021-01-05 | 上海复旦微电子集团股份有限公司 | Time delay evaluation method and device and readable storage medium |
| CN112216615B (en) * | 2019-07-09 | 2023-09-22 | 澜起科技股份有限公司 | Substrate packaging method capable of adjusting signal transmission time and structure thereof |
| CN110888040A (en) * | 2019-11-28 | 2020-03-17 | 苏州长风航空电子有限公司 | Signal link fault simulation test method |
| CN112989753B (en) * | 2021-01-28 | 2024-05-03 | 深圳市一博科技股份有限公司 | Packaging model for improving DDR simulation precision and modeling method thereof |
| CN114915568B (en) * | 2021-02-09 | 2024-04-09 | 大唐移动通信设备有限公司 | Method and device for determining performance of signal transmission line and storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104424369A (en) * | 2013-08-28 | 2015-03-18 | 京微雅格（北京）科技有限公司 | Time sequence estimation method for FPGA (field programmable gate array) post-mapping net list |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7181710B2 (en) * | 2004-06-28 | 2007-02-20 | Lsi Logic Corporation | Device for estimating cell delay from a table with added voltage swing |
| US7996804B2 (en) * | 2008-01-17 | 2011-08-09 | Lsi Corporation | Signal delay skew reduction system |
| CN105183986A (en) * | 2015-09-07 | 2015-12-23 | 上海飞斯信息科技有限公司 | PCB signal integrity design method for DDRs |
-
2016
- 2016-04-29 CN CN201610276784.XA patent/CN105930601B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104424369A (en) * | 2013-08-28 | 2015-03-18 | 京微雅格（北京）科技有限公司 | Time sequence estimation method for FPGA (field programmable gate array) post-mapping net list |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105930601A (en) | 2016-09-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105930601B (en) | A kind of DDR timing and delay deflection Simulation Evaluation method based on look-up table | |
| US8214785B2 (en) | Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium | |
| US9275706B2 (en) | Auto-calibration for high speed input/output | |
| CN103366023B (en) | Differential signal cabling wiring system and method | |
| US9515031B2 (en) | Mitigation of far-end crosstalk induced by routing and out-of-plane interconnects | |
| US8504334B2 (en) | Simulating the transmission and simultaneous switching output noise of signals in a computer system | |
| CN105679355A (en) | Optimal sampling of data-bus signals using configurable individual time delays | |
| US9496633B1 (en) | Memory module adaptor card | |
| CN107077176B (en) | Two-part electrical connector | |
| KR20160097314A (en) | Crosstalk analysis methods using superposition | |
| CN110716120B (en) | Calibration method for channel delay deviation of automatic chip test equipment | |
| CN108009372A (en) | A kind of method of DDR memory virtuals writing level adjustments responsive | |
| CN116245071A (en) | Wiring method, wiring device, wiring medium and wiring product for storage device | |
| US10372857B2 (en) | Determining parameters of PCB structures | |
| US8257092B2 (en) | Redundant clock channel for high reliability connectors | |
| CN103530212A (en) | Method for high-speed signal loss testing | |
| CN103257309A (en) | Double data rate SDRAM (ddr) series printed circuit board (pcb) timing sequence compensation method, system and terminal | |
| WO2017112075A1 (en) | Device, system and method for providing zone-based configuration of socket structures | |
| Zhao et al. | Fast contour integral equation method for wideband power integrity analysis | |
| Ravelo et al. | Fast estimation of RL‐loaded microelectronic interconnections delay for the signal integrity prediction | |
| US11995389B2 (en) | Connector structure, and skew calculation method and device | |
| CN101957781A (en) | Remote aid memory testing method | |
| Gurulakshmi et al. | Design and analysis of various non-radiating transmission line structures on a high-speed PCBs | |
| Hashemi et al. | Delay analysis using FDTD for source synchronous interfaces | |
| Liao et al. | Challenges of high-speed channel design on GPU accelerated system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |