CN117119671A - High-speed signal line optimization method, system, electronic equipment and readable storage medium - Google Patents
High-speed signal line optimization method, system, electronic equipment and readable storage medium Download PDFInfo
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
Abstract
The application discloses a high-speed signal wire optimizing method, a system, electronic equipment and a readable storage medium, which relate to the field of printed circuit boards and aim to solve the problem that two differential signal wires are not equal in length, and the high-speed signal wire optimizing method comprises the following steps: when two differential signal lines in the high-speed signal lines meet optimization conditions, determining a signal line to be adjusted and a first target signal line in the two differential signal lines; winding the signal wire to be adjusted to obtain a second target signal wire; and adjusting the distance and the line width of the first target signal line and the second target signal line until the corresponding impedance of the first target signal line and the second target signal line meets the preset impedance requirement. The application can lead the two differential signal wires to have equal length and lead the impedance of the two differential signal wires to meet the preset impedance requirement, thereby improving the design quality of the PCB, ensuring good signal integrity and further improving the performance of the product.
Description
Technical Field
The present application relates to the field of printed circuit boards, and in particular, to a method and system for optimizing high-speed signal lines, an electronic device, and a readable storage medium.
Background
The current high-speed signals in the server and the memory have higher and higher speed, and the design requirements are stricter and stricter. For high-speed signals, the differential pair is generally used for transmission because the differential pair has the advantages of strong anti-interference capability, capability of effectively inhibiting electromagnetic interference, accurate time sequence positioning and the like. The differential pair consists of two signal wires with equal signal sizes and 180 degrees phase difference, so that the two signal wires in the differential pair are kept symmetrical, the conversion from a differential mode to a common mode can be avoided, the good integrity of a link signal is ensured, and the system operates normally. However, in practical application, due to limitations of chip pins, connector pin positions, etc., it is impossible to ensure that the routing lengths of the two signal wires are equal.
Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
The application aims to provide an optimization method, an optimization system, electronic equipment and a readable storage medium for a high-speed signal wire, which can enable two differential signal wires to be equal in length and enable the impedance of the two differential signal wires to meet the preset impedance requirement, improve the design quality of a PCB, ensure good signal integrity and further improve the performance of a product.
In order to solve the above technical problems, the present application provides an optimization method for a high-speed signal line, including:
when two differential signal lines in the high-speed signal lines meet optimization conditions, determining a signal line to be adjusted and a first target signal line in the two differential signal lines; the line length of the signal line to be adjusted is smaller than that of the first target signal line;
winding the signal wire to be adjusted to obtain a second target signal wire; the difference between the line length of the second target signal line and the line length of the first target signal line is smaller than a first preset value;
and adjusting the distance and the line width of the first target signal line and the second target signal line until the corresponding impedance of the first target signal line and the second target signal line meets the preset impedance requirement.
In an exemplary embodiment, before the two differential signal lines of the high-speed signal lines meet the optimization condition, the optimization method of the high-speed signal line further includes:
obtaining the line lengths of two differential signal lines in the high-speed signal line;
judging whether the difference value of the line lengths of the two differential signal lines is smaller than the first preset value or not;
if not, judging that two differential signal lines in the high-speed signal lines meet an optimization condition;
If yes, judging that two differential signal lines in the high-speed signal lines do not meet the optimization condition.
In an exemplary embodiment, the process of adding a winding to the signal line to be adjusted to obtain a second target signal line includes:
obtaining the line lengths of two differential signal lines in the high-speed signal line;
calculating the difference value of the line lengths of the two differential signal lines;
determining the number of windings based on the difference;
and adding the number of windings to the signal line to be adjusted to obtain a second target signal line.
In an exemplary embodiment, the process of adjusting the distance and the line width of the first target signal line and the second target signal line until the corresponding impedance of the first target signal line and the second target signal line meets the preset impedance requirement includes:
determining a winding area and a parallel area in the first target signal line and the second target signal line; the winding length area is an area comprising the winding wire;
and adjusting the distance and the line width of the first target signal line and the second target signal line in the winding area until the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
In an exemplary embodiment, the process of adjusting the pitch and the line width of the first and second target signal lines of the winding area includes:
adjusting the distance between the first target signal line and the second target signal line in the winding area according to a first preset step length to obtain a current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain a current line width;
determining a current impedance based on the current line width and the current spacing;
if the current impedance does not meet the preset impedance requirement, repeating the operation of adjusting the distance between the first target signal line and the second target signal line in the winding area according to a first preset step length to obtain a current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain a current line width;
the initial line widths of the first and second target signal lines in the winding area are line widths of the first and second target signal lines in the parallel area; an initial pitch of the first and second target signal lines in the winding area is a pitch of the first and second target signal lines in the parallel area.
In an exemplary embodiment, the optimization method of the high-speed signal line further includes:
obtaining lamination design parameters of a printed circuit board;
the process of determining the current impedance based on the current line width and the current spacing includes:
a current impedance is determined based on the current line width, the current spacing, and the stack design parameter.
In an exemplary embodiment, the process of adjusting the distance and the line width between the first target signal line and the second target signal line in the winding area until the corresponding impedance of the first target signal line and the second target signal line meets the preset impedance requirement includes:
adjusting the distance and the line width of the first target signal line and the second target signal line of the winding area;
and in the adjustment process, when the difference value between the impedance corresponding to the first target signal line and the second target signal line in the winding area and the impedance corresponding to the first target signal line and the second target signal line in the parallel area is smaller than a second preset value, judging that the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
In an exemplary embodiment, the optimization method of the high-speed signal line further includes:
obtaining the line lengths of two differential signal lines in the high-speed signal line;
calculating the difference value of the line lengths of the two differential signal lines;
determining the number of windings according to the difference value;
and based on the number, the line length of the line segment to be processed, which is parallel to the first target signal line, in the second target signal line is adjusted until the insertion loss value and the return loss value corresponding to the first target signal line and the second target signal line meet the reference requirements corresponding to the first target signal line and the second target signal line respectively.
In an exemplary embodiment, based on the number, the line length of the line segment to be processed, which is parallel to the first target signal line, in the second target signal line is adjusted until the insertion loss value and the return loss value corresponding to the first target signal line and the second target signal line both meet the respective corresponding reference requirements, and then the optimization method of the high-speed signal line further includes:
obtaining optimal line lengths when insertion loss values and return loss values corresponding to the first target signal line and the second target signal line meet respective corresponding reference requirements;
acquiring the optimal distance and the optimal line width when the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement;
Determining the optimal line length, the optimal distance and the optimal line width as optimal signal line design parameters;
and storing the optimal signal line design parameters.
In order to solve the above technical problems, the present application further provides an optimization system for a high-speed signal line, including:
the first determining module is used for determining a signal line to be adjusted and a first target signal line in the two differential signal lines when the two differential signal lines in the high-speed signal line meet the optimization condition; the line length of the signal line to be adjusted is smaller than that of the first target signal line;
the compensation module is used for adding windings to the signal line to be adjusted to obtain a second target signal line; the difference between the line length of the second target signal line and the line length of the first target signal line is smaller than a first preset value;
and the optimization module is used for adjusting the distance and the line width of the first target signal line and the second target signal line until the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
In order to solve the technical problem, the present application further provides an electronic device, including:
a memory for storing a computer program;
A processor for implementing the steps of the method for optimizing a high-speed signal line according to any one of the above when executing the computer program.
To solve the above technical problem, the present application further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the method for optimizing a high-speed signal line according to any one of the above.
The application provides an optimization method of a high-speed signal wire, which is characterized in that when two differential signal wires in the high-speed signal wire meet optimization conditions, windings are added to a shorter differential signal wire, so that the two differential signal wires are equal in length, and the line width and the distance between the two differential signal wires are adjusted, so that the impedance of the two differential signal wires meets the preset impedance requirement, the design quality of a PCB is improved, good signal integrity is ensured, and further the performance of a product is improved. The application also provides an optimization system, electronic equipment and computer readable storage medium of the high-speed signal line, which have the same beneficial effects as the optimization method of the high-speed signal line.
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For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of the steps of a method for optimizing a high-speed signal line according to the present application;
FIG. 2 is a schematic diagram of a 45-degree trace provided by the present application;
FIG. 3 is a schematic diagram of an arc trace according to the present application;
fig. 4 is a schematic structural diagram of an optimizing system for a high-speed signal line according to the present application.
Detailed Description
The core of the application is to provide an optimization method, a system, electronic equipment and a readable storage medium of a high-speed signal wire, which can lead two differential signal wires to be equal in length and lead the impedance of the two differential signal wires to meet the preset impedance requirement, improve the design quality of a PCB, ensure good signal integrity and further improve the performance of products.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for optimizing a high-speed signal line according to the present application, where the method includes:
s101: when two differential signal lines in the high-speed signal lines meet the optimization condition, determining a signal line to be adjusted and a first target signal line in the two differential signal lines; the line length of the signal line to be adjusted is smaller than that of the first target signal line;
in some embodiments, before two differential signal lines of the high-speed signal lines satisfy the optimization condition, the optimization method of the high-speed signal lines further includes:
acquiring the line length of two differential signal lines in the high-speed signal line;
judging whether the difference value of the line lengths of the two differential signal lines is smaller than a first preset value or not;
if not, judging that two differential signal lines in the high-speed signal lines meet the optimization condition;
if yes, judging that two differential signal lines in the high-speed signal lines do not meet the optimization condition.
It will be appreciated that the high-speed signal line in this embodiment includes two differential signal lines for transmitting two high-speed signals of equal magnitude and opposite phases, respectively. The two differential signal lines in the differential pair are kept symmetrical, the conversion from a differential mode to a common mode can be avoided, the good link signal integrity and the normal operation of a system are ensured, the wiring lengths of the two differential signal lines are unequal in consideration of the limitation of the positions between the pins of the chip and the cathode of the connector, when the line length difference of the two differential signal lines is large, such as more than 1mil, the two differential signal lines cannot ensure good signal quality when transmitting signals, and the two differential signal lines in the high-speed signal line are judged to meet the optimization condition. Since the line lengths of the two differential signal lines are not identical, the shorter one of the two differential signal lines is determined as the signal line to be adjusted, and the longer one is determined as the first target signal line in the present embodiment.
S102: winding is added to the signal line to be adjusted to obtain a second target signal line; the difference between the line length of the second target signal line and the line length of the first target signal line is smaller than a first preset value;
in order to ensure that the difference of the line lengths of the two differential signal lines is within a first preset value, winding is added to the signal line to be adjusted to obtain a second target signal line, so that the difference of the line length of the second target signal line and the line length of the first target signal line is smaller than a first preset value, namely, the line lengths of the two differential signal lines after processing are ensured to be basically equal in length, wherein the first preset value can be set to be 1mil.
S103: and adjusting the distance and the line width of the first target signal line and the second target signal line until the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
It can be understood that the impedance of the area where the windings are added in the first target signal line and the second target signal line is changed compared with the impedance of the parallel area, that is, after the windings are added, the impedance of the high-speed signal line does not meet the preset impedance requirement, so after the windings are added, the line width of the first target signal line and the line width of the second target signal line and the distance between the line width of the first target signal line and the distance between the line width of the high-speed signal line are adjusted, and the impedance of the high-speed signal line is adjusted until the impedance of the high-speed signal line meets the preset impedance requirement, thereby ensuring the signal transmission quality.
Therefore, in this embodiment, when two differential signal lines in the high-speed signal line meet the optimization condition, the windings are added to the shorter differential signal line, so that the two differential signal lines are equal in length, and the line widths and the distances of the two differential signal lines are adjusted, so that the impedance of the two differential signal lines meets the preset impedance requirement, the design quality of the PCB is improved, good signal integrity is ensured, and further the performance of the product is improved.
Based on the above embodiments:
in some embodiments, the process of adding a winding to the signal line to be adjusted to obtain the second target signal line includes:
acquiring the line length of two differential signal lines in the high-speed signal line;
calculating the difference value of the line lengths of the two differential signal lines;
determining the number of windings based on the difference;
and winding the signal wire to be adjusted by increasing the number of windings to obtain a second target signal wire.
In some embodiments, after calculating the difference between the line lengths of the two differential signal lines and before determining the number of windings based on the difference, the method for optimizing the high-speed signal line further includes:
determining a winding angle corresponding to the winding;
the process of determining the number of windings based on the difference value includes:
the number of windings is determined based on the difference and the winding angle.
It will be understood that, in order to ensure that the first target signal line and the second target signal line are equal in length, the embodiment describes the increased number of windings, first determines the difference between the line lengths of the two differential signal lines, then determines the winding angle corresponding to the windings, and determines the length of the compensated line segment based on the winding angle, and referring to fig. 2, α is the winding angle, and the difference between the length of the bus segment to be compensated and the line length corresponds to the winding angle, based on this, the increased number of windings can be determined, and the number of windings is increased in the signal line to be adjusted, so that the first target signal line and the second target signal line are equal in length, and the accuracy is high.
In some embodiments, the number of windings may be determined based on a differential line length deviation of 600 mils to over 25 mils.
In some embodiments, adjusting the distance and the line width of the first target signal line and the second target signal line until the corresponding impedance of the first target signal line and the second target signal line meets the preset impedance requirement includes:
determining a winding area and a parallel area in the first target signal line and the second target signal line; the winding length area is an area comprising winding wires;
and adjusting the distance and the line width of the first target signal line and the second target signal line around the long area until the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
Referring to fig. 2 and 3, fig. 2 is a conventional 45 ° routing schematic diagram, fig. 3 is a conventional arc routing schematic diagram, the first target signal line and the second target signal line include a parallel area (1) and a winding area (2), the parallel area (1) is an area where the first target signal line and the second target signal line are arranged in parallel, and the winding area (2) is an area including a winding, and it can be understood that the winding in the second target signal line is not parallel to the first target signal line.
The impedance of the winding long region and the impedance of the parallel region are inconsistent, and in the embodiment, only the distance and the line width of the signal line of the winding long region are adjusted, so that the difference value of the impedance of the winding long region and the impedance of the parallel region is smaller than a second preset value, and the impedance of the high-speed signal line can be ensured to meet the preset impedance requirement.
In some embodiments, the process of adjusting the spacing and linewidth of the first and second target signal lines around the long region includes:
the method comprises the steps of adjusting the distance between a first target signal line and a second target signal line in a winding area according to a first preset step length to obtain a current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain a current line width;
Determining a current impedance based on the current line width and the current spacing;
if the current impedance does not meet the preset impedance requirement, repeatedly adjusting the distance between the first target signal line and the second target signal line in the winding area according to a first preset step length to obtain the current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain the current line width;
the initial line widths of the first target signal line and the second target signal line in the winding length region are the line widths of the first target signal line and the second target signal line in the parallel region; the initial pitch around the first and second target signal lines in the long region is the pitch of the first and second target signal lines in the parallel region.
In some embodiments, the process of adjusting the distance and the line width of the first target signal line and the second target signal line around the long area until the corresponding impedance of the first target signal line and the second target signal line meets the preset impedance requirement includes:
adjusting the distance and the line width of the first target signal line and the second target signal line around the long area;
in the adjustment process, when the difference between the impedance corresponding to the first target signal line and the second target signal line in the winding length area and the impedance corresponding to the first target signal line and the second target signal line in the parallel area is smaller than a second preset value, judging that the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
In this embodiment, the pitch of the two differential signal lines in the winding length region is adjusted, and each time the first preset step length is adjusted, it can be understood that the initial pitch of the two differential signal lines in the winding length region, that is, the pitch of the two differential signal lines in the parallel region, is S, as shown in fig. 2, the initial pitch is S, the pitch is adjusted from S, each time the adjustment action is to increase the first preset step length, the first preset step length may be 0.1mil, and when the pitch of the two differential signal lines increases, the impedance increases. The line widths of the two differential signal lines in the winding area are adjusted, and each time the second preset step length is adjusted, it can be understood that the initial line widths of the two differential signal lines in the winding area, that is, the line widths of the two differential signal lines in the parallel area, are adjusted, as shown in fig. 2, the initial distance is W, the line widths are adjusted from W, each time the second preset step length is increased, the second preset step length can be 0.1mil, and when the line widths of the two differential signal lines are increased, the impedance is reduced. Recording the current spacing and the current line width after each adjustment, calculating the current impedance corresponding to the winding area based on the current spacing and the current line width, if the current impedance and the impedance of the parallel area connected with the current impedance are different by not more than 1ohm (the current spacing and the current line width can be adjusted according to different requirements of the project), determining the current spacing and the current line width as the optimal spacing S1 and the optimal line width W1, and if the current impedance corresponding to the winding area calculated by the current spacing and the current line width after the adjustment is different by not more than 1ohm, continuing to adjust the line width and the impedance until the preset impedance requirement is met.
In some embodiments, the method of optimizing a high-speed signal line further comprises:
obtaining lamination design parameters of a printed circuit board;
the process of determining the current impedance based on the current line width and the current spacing includes:
the current impedance is determined based on the current line width, the current spacing, and the stack design parameters.
In this embodiment, before calculating the impedance, the method further includes a step of obtaining a stack design parameter of the printed circuit board, where the stack includes a signal layer, a dielectric layer, a reference layer, and the like, and the stack design parameter includes, but is not limited to, a dielectric thickness, a dielectric constant, a loss factor, a copper thickness, a copper foil roughness, and the like, and each parameter adopts a variable form, so that different projects can be reused, when calculating the impedance, a preset impedance requirement can be determined according to the relevant stack design parameter, and a current impedance can be calculated according to the stack design parameter, a current line width, and a current pitch.
In some embodiments, the method of optimizing a high-speed signal line further comprises:
acquiring the line length of two differential signal lines in the high-speed signal line;
calculating the difference value of the line lengths of the two differential signal lines;
determining a winding angle corresponding to the winding;
determining the number of windings according to the difference value and the winding angle;
Based on the quantity, the line length of the line segment to be processed, which is parallel to the first target signal line, in the second target signal line is adjusted until the insertion loss value and the return loss value corresponding to the first target signal line and the second target signal line meet the reference requirements corresponding to the first target signal line and the second target signal line.
In this embodiment, after the number of windings is determined, the line length of the line segment to be processed, which is parallel to the first target signal line, in the second target signal line is adjusted until the insertion loss value and the return loss value corresponding to the first target signal line and the second target signal line both meet the respective corresponding reference requirements, and referring to fig. 2, the line segment to be processed includes a line segment B and a line segment D, so as to further ensure good signal integrity.
In some embodiments, based on the number, the line length of the line segment to be processed, which is parallel to the first target signal line, in the second target signal line is adjusted until after the insertion loss value and the return loss value corresponding to the first target signal line and the second target signal line both meet the respective corresponding reference requirements, and the method for optimizing the high-speed signal line further includes:
obtaining optimal line lengths when insertion loss values and return loss values corresponding to the first target signal line and the second target signal line meet respective corresponding reference requirements;
Acquiring the optimal distance and the optimal line width when the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement;
determining the optimal line length, the optimal distance and the optimal line width as optimal signal line design parameters;
storing the optimal signal line design parameters.
In this embodiment, after determining the optimal line length, the optimal line width and the optimal distance for the high-speed signal line design, a simulation may be run, and the simulation result is checked or saved, for example, S parameters (including impedance, isolation, coupling, attenuation of signals, etc. of the transmission line) are put into circuit simulation software to perform TDR (Time Domain Reflectometry, time domain reflection technology) analysis, so as to obtain each parameter of the optimal differential line design corresponding to the specific impedance, and then the S parameters are put into the system to perform time domain frequency domain analysis, so as to determine the time domain frequency domain margin of the system. In some embodiments, different stacks of items, different PCB (Printed Circuit Board ) materials, differential wire-wound equal length parameters corresponding to different impedances may be aggregated into a PCB interconnect element design system as an interconnection information store for rapid reference to subsequent item designs.
In summary, the application can be applied to the high-speed line equal-length design of products such as servers, memories and the like, and the link routing design is carried out according to the equal-length winding scheme obtained through simulation, so that good signal integrity is ensured. By using the simulation analysis, a large number of working hours can be reduced, and the development period can be shortened. In addition, the analysis method has wide application range and high popularization degree.
In a second aspect, referring to fig. 4, fig. 4 is a schematic structural diagram of an optimization system for a high-speed signal line according to the present application, where the optimization system for a high-speed signal line includes:
a first determining module 41, configured to determine a signal line to be adjusted and a first target signal line of two differential signal lines when the two differential signal lines of the high-speed signal line satisfy an optimization condition; the line length of the signal line to be adjusted is smaller than that of the first target signal line;
the compensation module 42 is configured to add a winding to the signal line to be adjusted to obtain a second target signal line; the difference between the line length of the second target signal line and the line length of the first target signal line is smaller than a first preset value;
and the optimizing module 43 is configured to adjust the distance and the line width of the first target signal line and the second target signal line until the impedances corresponding to the first target signal line and the second target signal line meet the preset impedance requirement.
In some embodiments, the optimization system of the high-speed signal line further comprises:
the first acquisition module is used for acquiring the line lengths of two differential signal lines in the high-speed signal line;
the judging module is used for judging whether the difference value of the line lengths of the two differential signal lines is smaller than a first preset value or not, and if not, judging that the two differential signal lines in the high-speed signal line meet the optimization condition; if yes, judging that two differential signal lines in the high-speed signal lines do not meet the optimization condition.
In some embodiments, the process of adding a winding to the signal line to be adjusted to obtain the second target signal line includes:
acquiring the line length of two differential signal lines in the high-speed signal line;
calculating the difference value of the line lengths of the two differential signal lines;
determining a winding angle corresponding to the winding;
determining the number of windings based on the difference and the winding angle;
and winding the signal wire to be adjusted by increasing the number of windings to obtain a second target signal wire.
In some embodiments, adjusting the distance and the line width of the first target signal line and the second target signal line until the corresponding impedance of the first target signal line and the second target signal line meets the preset impedance requirement includes:
determining a winding area and a parallel area in the first target signal line and the second target signal line; the winding length area is an area comprising winding wires;
and adjusting the distance and the line width of the first target signal line and the second target signal line around the long area until the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
In some embodiments, the process of adjusting the spacing and linewidth of the first and second target signal lines around the long region includes:
The method comprises the steps of adjusting the distance between a first target signal line and a second target signal line in a winding area according to a first preset step length to obtain a current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain a current line width;
determining a current impedance based on the current line width and the current spacing;
if the current impedance does not meet the preset impedance requirement, repeatedly adjusting the distance between the first target signal line and the second target signal line in the winding area according to a first preset step length to obtain the current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain the current line width;
the initial line widths of the first target signal line and the second target signal line in the winding length region are the line widths of the first target signal line and the second target signal line in the parallel region; the initial pitch around the first and second target signal lines in the long region is the pitch of the first and second target signal lines in the parallel region.
In some embodiments, the optimization system of the high-speed signal line further comprises:
the second acquisition module is used for acquiring the lamination design parameters of the printed circuit board;
The process of determining the current impedance based on the current line width and the current spacing includes:
the current impedance is determined based on the current line width, the current spacing, and the stack design parameters.
In some embodiments, the process of adjusting the distance and the line width of the first target signal line and the second target signal line around the long area until the corresponding impedance of the first target signal line and the second target signal line meets the preset impedance requirement includes:
adjusting the distance and the line width of the first target signal line and the second target signal line around the long area;
in the adjustment process, when the difference between the impedance corresponding to the first target signal line and the second target signal line in the winding length area and the impedance corresponding to the first target signal line and the second target signal line in the parallel area is smaller than a second preset value, judging that the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
In some embodiments, the optimization system of the high-speed signal line further comprises:
the third acquisition module is used for acquiring the line lengths of two differential signal lines in the high-speed signal line;
the first calculation module is used for calculating the difference value of the line lengths of the two differential signal lines;
the second calculation module is used for determining a winding angle corresponding to the winding;
The third calculation module is used for determining the number of windings according to the difference value and the winding angle;
the optimizing module 43 is further configured to adjust, based on the number, a line length of a line segment to be processed in the second target signal line, which is parallel to the first target signal line, until insertion loss values and return loss values corresponding to the first target signal line and the second target signal line both meet respective corresponding reference requirements.
In some embodiments, the optimization system of the high-speed signal line further comprises:
the fourth acquisition module is used for acquiring the optimal line length when the insertion loss value and the return loss value corresponding to the first target signal line and the second target signal line meet the corresponding reference requirements;
a fifth obtaining module, configured to obtain an optimal distance and an optimal line width when impedances corresponding to the first target signal line and the second target signal line meet a preset impedance requirement;
the second determining module is used for determining the optimal line length, the optimal distance and the optimal line width as optimal signal line design parameters;
and the storage module is used for storing the optimal signal line design parameters.
In a third aspect, the present application also provides an electronic device, including:
a memory for storing a computer program;
a processor for implementing the steps of the method of optimizing a high-speed signal line as described in any one of the embodiments above when executing a computer program.
Specifically, the memory includes a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer readable instructions, and the internal memory provides an environment for the operating system and the execution of the computer readable instructions in the non-volatile storage medium. When the processor executes the computer program stored in the memory, the following steps may be implemented: when two differential signal lines in the high-speed signal lines meet the optimization condition, determining a signal line to be adjusted and a first target signal line in the two differential signal lines; the line length of the signal line to be adjusted is smaller than that of the first target signal line; winding is added to the signal line to be adjusted to obtain a second target signal line; the difference between the line length of the second target signal line and the line length of the first target signal line is smaller than a first preset value; and adjusting the distance and the line width of the first target signal line and the second target signal line until the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
Therefore, in this embodiment, when two differential signal lines in the high-speed signal line meet the optimization condition, the windings are added to the shorter differential signal line, so that the two differential signal lines are equal in length, and the line widths and the distances of the two differential signal lines are adjusted, so that the impedance of the two differential signal lines meets the preset impedance requirement, the design quality of the PCB is improved, good signal integrity is ensured, and further the performance of the product is improved.
In some embodiments, the processor, when executing the computer subroutine stored in memory, may implement the following steps: acquiring the line length of two differential signal lines in the high-speed signal line; judging whether the difference value of the line lengths of the two differential signal lines is smaller than a first preset value or not; if not, judging that two differential signal lines in the high-speed signal lines meet the optimization condition; if yes, judging that two differential signal lines in the high-speed signal lines do not meet the optimization condition.
In some embodiments, the processor, when executing the computer subroutine stored in memory, may implement the following steps: acquiring the line length of two differential signal lines in the high-speed signal line; calculating the difference value of the line lengths of the two differential signal lines; determining a winding angle corresponding to the winding; determining the number of windings based on the difference and the winding angle; and winding the signal wire to be adjusted by increasing the number of windings to obtain a second target signal wire.
In some embodiments, the processor, when executing the computer subroutine stored in memory, may implement the following steps: determining a winding area and a parallel area in the first target signal line and the second target signal line; the winding length area is an area comprising winding wires; and adjusting the distance and the line width of the first target signal line and the second target signal line around the long area until the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
In some embodiments, the processor, when executing the computer subroutine stored in memory, may implement the following steps: the method comprises the steps of adjusting the distance between a first target signal line and a second target signal line in a winding area according to a first preset step length to obtain a current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain a current line width; determining a current impedance based on the current line width and the current spacing; if the current impedance does not meet the preset impedance requirement, repeatedly adjusting the distance between the first target signal line and the second target signal line in the winding area according to a first preset step length to obtain the current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain the current line width; the initial line widths of the first target signal line and the second target signal line in the winding length region are the line widths of the first target signal line and the second target signal line in the parallel region; the initial pitch around the first and second target signal lines in the long region is the pitch of the first and second target signal lines in the parallel region.
In some embodiments, the processor, when executing the computer subroutine stored in memory, may implement the following steps: obtaining lamination design parameters of a printed circuit board; the process of determining the current impedance based on the current line width and the current spacing includes: the current impedance is determined based on the current line width, the current spacing, and the stack design parameters.
In some embodiments, the processor, when executing the computer subroutine stored in memory, may implement the following steps: adjusting the distance and the line width of the first target signal line and the second target signal line around the long area; in the adjustment process, when the difference between the impedance corresponding to the first target signal line and the second target signal line in the winding length area and the impedance corresponding to the first target signal line and the second target signal line in the parallel area is smaller than a second preset value, judging that the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
In some embodiments, the processor, when executing the computer subroutine stored in memory, may implement the following steps: acquiring the line length of two differential signal lines in the high-speed signal line; calculating the difference value of the line lengths of the two differential signal lines; determining a winding angle corresponding to the winding; determining the number of windings according to the difference value and the winding angle; based on the quantity, the line length of the line segment to be processed, which is parallel to the first target signal line, in the second target signal line is adjusted until the insertion loss value and the return loss value corresponding to the first target signal line and the second target signal line meet the reference requirements corresponding to the first target signal line and the second target signal line.
In some embodiments, the processor, when executing the computer subroutine stored in memory, may implement the following steps: obtaining optimal line lengths when insertion loss values and return loss values corresponding to the first target signal line and the second target signal line meet respective corresponding reference requirements; acquiring the optimal distance and the optimal line width when the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement; determining the optimal line length, the optimal distance and the optimal line width as optimal signal line design parameters; storing the optimal signal line design parameters.
On the basis of the above embodiment, the electronic device further includes:
the input interface is connected with the processor and used for acquiring the externally imported computer programs, parameters and instructions, and the externally imported computer programs, parameters and instructions are controlled by the processor and stored in the memory. The input interface may be coupled to an input device for receiving parameters or instructions manually entered by a user. The input device can be a touch layer covered on a display screen, or can be a key, a track ball or a touch pad arranged on a terminal shell.
And the display unit is connected with the processor and used for displaying the data sent by the processor. The display unit may be a liquid crystal display or an electronic ink display, etc.
And the network port is connected with the processor and used for carrying out communication connection with external terminal equipment. The communication technology adopted by the communication connection can be a wired communication technology or a wireless communication technology, such as a mobile high definition link technology (MHL), a Universal Serial Bus (USB), a High Definition Multimedia Interface (HDMI), a wireless fidelity technology (WiFi), a Bluetooth communication technology with low power consumption, a communication technology based on IEEE802.11s, and the like.
In a fourth aspect, the present application also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of optimizing a high speed signal line as described in any one of the embodiments above.
The storage medium may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes. The storage medium has stored thereon a computer program which, when executed by a processor, performs the steps of: when two differential signal lines in the high-speed signal lines meet the optimization condition, determining a signal line to be adjusted and a first target signal line in the two differential signal lines; the line length of the signal line to be adjusted is smaller than that of the first target signal line; winding is added to the signal line to be adjusted to obtain a second target signal line; the difference between the line length of the second target signal line and the line length of the first target signal line is smaller than a first preset value; and adjusting the distance and the line width of the first target signal line and the second target signal line until the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
Therefore, in this embodiment, when two differential signal lines in the high-speed signal line meet the optimization condition, the windings are added to the shorter differential signal line, so that the two differential signal lines are equal in length, and the line widths and the distances of the two differential signal lines are adjusted, so that the impedance of the two differential signal lines meets the preset impedance requirement, the design quality of the PCB is improved, good signal integrity is ensured, and further the performance of the product is improved.
In some embodiments, the following steps may be implemented in particular when a computer subroutine stored in a computer readable storage medium is executed by a processor: acquiring the line length of two differential signal lines in the high-speed signal line; judging whether the difference value of the line lengths of the two differential signal lines is smaller than a first preset value or not; if not, judging that two differential signal lines in the high-speed signal lines meet the optimization condition; if yes, judging that two differential signal lines in the high-speed signal lines do not meet the optimization condition.
In some embodiments, the following steps may be implemented in particular when a computer subroutine stored in a computer readable storage medium is executed by a processor: acquiring the line length of two differential signal lines in the high-speed signal line; calculating the difference value of the line lengths of the two differential signal lines; determining a winding angle corresponding to the winding; determining the number of windings based on the difference and the winding angle; and winding the signal wire to be adjusted by increasing the number of windings to obtain a second target signal wire.
In some embodiments, the following steps may be implemented in particular when a computer subroutine stored in a computer readable storage medium is executed by a processor: determining a winding area and a parallel area in the first target signal line and the second target signal line; the winding length area is an area comprising winding wires; and adjusting the distance and the line width of the first target signal line and the second target signal line around the long area until the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
In some embodiments, the following steps may be implemented in particular when a computer subroutine stored in a computer readable storage medium is executed by a processor: the method comprises the steps of adjusting the distance between a first target signal line and a second target signal line in a winding area according to a first preset step length to obtain a current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain a current line width; determining a current impedance based on the current line width and the current spacing; if the current impedance does not meet the preset impedance requirement, repeatedly adjusting the distance between the first target signal line and the second target signal line in the winding area according to a first preset step length to obtain the current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain the current line width; the initial line widths of the first target signal line and the second target signal line in the winding length region are the line widths of the first target signal line and the second target signal line in the parallel region; the initial pitch around the first and second target signal lines in the long region is the pitch of the first and second target signal lines in the parallel region.
In some embodiments, the following steps may be implemented in particular when a computer subroutine stored in a computer readable storage medium is executed by a processor: obtaining lamination design parameters of a printed circuit board; the process of determining the current impedance based on the current line width and the current spacing includes: the current impedance is determined based on the current line width, the current spacing, and the stack design parameters.
In some embodiments, the following steps may be implemented in particular when a computer subroutine stored in a computer readable storage medium is executed by a processor: adjusting the distance and the line width of the first target signal line and the second target signal line around the long area; in the adjustment process, when the difference between the impedance corresponding to the first target signal line and the second target signal line in the winding length area and the impedance corresponding to the first target signal line and the second target signal line in the parallel area is smaller than a second preset value, judging that the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
In some embodiments, the following steps may be implemented in particular when a computer subroutine stored in a computer readable storage medium is executed by a processor: acquiring the line length of two differential signal lines in the high-speed signal line; calculating the difference value of the line lengths of the two differential signal lines; determining a winding angle corresponding to the winding; determining the number of windings according to the difference value and the winding angle; based on the quantity, the line length of the line segment to be processed, which is parallel to the first target signal line, in the second target signal line is adjusted until the insertion loss value and the return loss value corresponding to the first target signal line and the second target signal line meet the reference requirements corresponding to the first target signal line and the second target signal line.
In some embodiments, the following steps may be implemented in particular when a computer subroutine stored in a computer readable storage medium is executed by a processor: obtaining optimal line lengths when insertion loss values and return loss values corresponding to the first target signal line and the second target signal line meet respective corresponding reference requirements; acquiring the optimal distance and the optimal line width when the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement; determining the optimal line length, the optimal distance and the optimal line width as optimal signal line design parameters; storing the optimal signal line design parameters.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. A method of optimizing a high-speed signal line, comprising:
when two differential signal lines in the high-speed signal lines meet optimization conditions, determining a signal line to be adjusted and a first target signal line in the two differential signal lines; the line length of the signal line to be adjusted is smaller than that of the first target signal line;
winding the signal wire to be adjusted to obtain a second target signal wire; the difference between the line length of the second target signal line and the line length of the first target signal line is smaller than a first preset value;
and adjusting the distance and the line width of the first target signal line and the second target signal line until the corresponding impedance of the first target signal line and the second target signal line meets the preset impedance requirement.
2. The method for optimizing high-speed signal lines according to claim 1, wherein said method for optimizing high-speed signal lines further comprises, before two differential signal lines in the high-speed signal lines satisfy an optimization condition:
obtaining the line lengths of two differential signal lines in the high-speed signal line;
judging whether the difference value of the line lengths of the two differential signal lines is smaller than the first preset value or not;
if not, judging that two differential signal lines in the high-speed signal lines meet an optimization condition;
if yes, judging that two differential signal lines in the high-speed signal lines do not meet the optimization condition.
3. The method for optimizing a high-speed signal line according to claim 1, wherein the step of adding a winding to the signal line to be adjusted to obtain a second target signal line comprises:
obtaining the line lengths of two differential signal lines in the high-speed signal line;
calculating the difference value of the line lengths of the two differential signal lines;
determining the number of windings based on the difference;
and adding the number of windings to the signal line to be adjusted to obtain a second target signal line.
4. The method of optimizing high-speed signal lines according to claim 1, wherein adjusting the pitch and the line width of the first target signal line and the second target signal line until the impedances corresponding to the first target signal line and the second target signal line satisfy a preset impedance requirement comprises:
Determining a winding area and a parallel area in the first target signal line and the second target signal line; the winding length area is an area comprising the winding wire;
and adjusting the distance and the line width of the first target signal line and the second target signal line in the winding area until the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
5. The method of optimizing high-speed signal lines according to claim 4, wherein the process of adjusting the pitch and the line width of the first target signal line and the second target signal line of the winding area includes:
adjusting the distance between the first target signal line and the second target signal line in the winding area according to a first preset step length to obtain a current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain a current line width;
determining a current impedance based on the current line width and the current spacing;
if the current impedance does not meet the preset impedance requirement, repeating the operation of adjusting the distance between the first target signal line and the second target signal line in the winding area according to a first preset step length to obtain a current distance, and adjusting the line widths of the first target signal line and the second target signal line in the winding area according to a second preset step length to obtain a current line width;
The initial line widths of the first and second target signal lines in the winding region are line widths of the first and second target signal lines in the parallel region, and the initial pitches of the first and second target signal lines in the winding region are pitches of the first and second target signal lines in the parallel region.
6. The method for optimizing a high-speed signal line according to claim 5, further comprising:
obtaining lamination design parameters of a printed circuit board;
the process of determining the current impedance based on the current line width and the current spacing includes:
a current impedance is determined based on the current line width, the current spacing, and the stack design parameter.
7. The method of optimizing high-speed signal lines according to claim 4, wherein the process of adjusting the pitch and the line width of the first target signal line and the second target signal line in the winding area until the impedances corresponding to the first target signal line and the second target signal line meet the preset impedance requirement comprises:
Adjusting the distance and the line width of the first target signal line and the second target signal line of the winding area;
and in the adjustment process, when the difference value between the impedance corresponding to the first target signal line and the second target signal line in the winding area and the impedance corresponding to the first target signal line and the second target signal line in the parallel area is smaller than a second preset value, judging that the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
8. The method for optimizing a high-speed signal line according to any one of claims 1 to 7, characterized in that the method for optimizing a high-speed signal line further comprises:
obtaining the line lengths of two differential signal lines in the high-speed signal line;
calculating the difference value of the line lengths of the two differential signal lines;
determining the number of windings according to the difference value;
and based on the number, the line length of the line segment to be processed, which is parallel to the first target signal line, in the second target signal line is adjusted until the insertion loss value and the return loss value corresponding to the first target signal line and the second target signal line meet the reference requirements corresponding to the first target signal line and the second target signal line respectively.
9. The method according to claim 8, wherein the method for optimizing the high-speed signal line further comprises, based on the number, adjusting the line length of the line segment to be processed in the second target signal line, which is parallel to the first target signal line, until the insertion loss value and the return loss value corresponding to the first target signal line and the second target signal line each meet the respective corresponding reference requirements:
obtaining optimal line lengths when insertion loss values and return loss values corresponding to the first target signal line and the second target signal line meet respective corresponding reference requirements;
acquiring the optimal distance and the optimal line width when the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement;
determining the optimal line length, the optimal distance and the optimal line width as optimal signal line design parameters;
and storing the optimal signal line design parameters.
10. An optimization system for a high-speed signal line, comprising:
the first determining module is used for determining a signal line to be adjusted and a first target signal line in the two differential signal lines when the two differential signal lines in the high-speed signal line meet the optimization condition; the line length of the signal line to be adjusted is smaller than that of the first target signal line;
The compensation module is used for adding windings to the signal line to be adjusted to obtain a second target signal line; the difference between the line length of the second target signal line and the line length of the first target signal line is smaller than a first preset value;
and the optimization module is used for adjusting the distance and the line width of the first target signal line and the second target signal line until the impedance corresponding to the first target signal line and the second target signal line meets the preset impedance requirement.
11. An electronic device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the method for optimizing a high-speed signal line according to any one of claims 1-9 when executing said computer program.
12. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the method for optimizing a high-speed signal line according to any of claims 1-9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117634403A (en) * | 2024-01-24 | 2024-03-01 | 山东云海国创云计算装备产业创新中心有限公司 | Transmission line structure determining method, system, equipment and readable storage medium |
| CN117634403B (en) * | 2024-01-24 | 2024-05-10 | 山东云海国创云计算装备产业创新中心有限公司 | Transmission line structure determining method, system, equipment and readable storage medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117634403A (en) * | 2024-01-24 | 2024-03-01 | 山东云海国创云计算装备产业创新中心有限公司 | Transmission line structure determining method, system, equipment and readable storage medium |
| CN117634403B (en) * | 2024-01-24 | 2024-05-10 | 山东云海国创云计算装备产业创新中心有限公司 | Transmission line structure determining method, system, equipment and readable storage medium |
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