CN107845393B - DDR signal wiring board, printed circuit board, and electronic device - Google Patents
DDR signal wiring board, printed circuit board, and electronic device Download PDFInfo
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- CN107845393B CN107845393B CN201710970531.7A CN201710970531A CN107845393B CN 107845393 B CN107845393 B CN 107845393B CN 201710970531 A CN201710970531 A CN 201710970531A CN 107845393 B CN107845393 B CN 107845393B
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- ddr signal
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 239000011889 copper foil Substances 0.000 claims description 10
- 230000008054 signal transmission Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- 101100387458 Medicago truncatula DMI1 gene Proteins 0.000 description 3
- 101100097982 Pisum sativum SYM8 gene Proteins 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 2
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
Abstract
The DDR signal wiring board comprises a first wiring layer, a second wiring layer, a third wiring layer and a fourth wiring layer, wherein the first wiring layer is used for setting a first data line and a first power line in a DDR signal line, the second wiring layer is used for setting a first ground plane, the third wiring layer is used for setting an address line, a control line, a clock line, a second data line and a second power line in the DDR signal line, and the fourth wiring layer is used for setting a second ground plane and a third power line. The first wiring layer, the second wiring layer, the third wiring layer and the fourth wiring layer are sequentially stacked from top to bottom. The application also provides a printed circuit board and an electronic device having the wiring board. The DDR signal wiring board can save the number of wiring layers, reduce design cost, enable the signal integrity of the DDR signal wire to be more reliable, and improve the DDR signal transmission quality.
Description
Technical Field
The present disclosure relates to a laminated wiring board, and more particularly to a DDR signal wiring board, and a printed circuit board and an electronic device having the same.
Background
With the continuous development of electronic information technology, Double data rate synchronous dynamic random access memory (DDR) has become the current mainstream memory specification and is generally supported by the mainstream products of various large chipset manufacturers, at present, there are three DDR operating frequencies of 100MHZ, 133MHZ, and 166MHZ, and because DDR memory has the characteristic of Double data rate transmission, a method of operating frequency × 2, namely DDR2, DDR3, and DDR4, is adopted for the identification of DDR memory.
Conventional PCBs (Printed Circuit boards) generally use a laminated wiring Board to route DDR signals. At present, laminated wiring boards usually have more wiring layers, that is, the order or the number of layers of a PCB is higher, and a power supply is designed with a single power supply plane, which increases the design cost of the PCB. And the signal lines are arranged on the plurality of wiring layers, so that the signal integrity of the DDR signal lines cannot be guaranteed, and the impedance of the signal lines cannot be easily controlled.
Disclosure of Invention
The DDR signal wiring board has fewer wiring layers, can reduce design cost, and enables signal integrity of DDR signal lines to be more reliable so as to improve DDR signal transmission quality.
An aspect of the present application provides a DDR signal wiring board including:
a first wiring layer for setting a first data line and a first power supply line in the DDR signal line;
a second wiring layer for providing a first ground plane;
the third wiring layer is used for setting an address line, a control line, a clock line, a second data line and a second power line in the DDR signal line;
a fourth wiring layer for providing a second ground plane and a third power supply line;
the first wiring layer, the second wiring layer, the third wiring layer and the fourth wiring layer are sequentially stacked from top to bottom.
The printed circuit board at least comprises the DDR signal wiring board.
The present application further provides an electronic device including a memory device, a controller device, and a printed circuit board for mounting the memory device and the controller device, wherein the printed circuit board at least includes the DDR signal wiring board.
According to the DDR signal wiring board, the DDR signal wires are arranged on the first wiring layer and the third wiring layer, the second wiring layer and the fourth wiring layer are arranged to form a complete ground plane, and therefore signal integrity of the DDR signal wires is more reliable. In addition, DDR power supply plane layers are not designed independently, DDR power supplies are arranged in the first wiring layer, the third wiring layer and the fourth wiring layer, PND impedance of a power supply path is guaranteed to meet design requirements, the number of wiring layers of DDR signal wiring boards can be saved, and design cost is reduced.
Furthermore, most of the data lines are arranged on the first wiring layer, so that wiring through holes between chips can be reduced, and the DDR signal transmission quality can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural view of a first wiring layer of a DDR signal wiring board according to an embodiment of the present application.
Fig. 2 is a schematic structural view of a second wiring layer of the DDR signal wiring board according to the embodiment of the present application.
Fig. 3 is a schematic structural view of a third wiring layer of the DDR signal wiring board according to the embodiment of the present application.
Fig. 4 is a schematic structural diagram of a fourth wiring layer of the DDR signal wiring board according to the embodiment of the present application.
Description of the main elements
DDR Signal Wiring Board 20
First power supply line 411
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
In order that the above objects, features and advantages of the present application can be more clearly understood, a detailed description of the present application will be given below with reference to the accompanying drawings and detailed description. In addition, the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth to provide a thorough understanding of the present application, and the described embodiments are merely a subset of the embodiments of the present application, rather than all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Referring to fig. 1-4, a DDR signal wiring board 20 is provided. It is understood that the DDR signal wiring Board 20 is a part of a Printed Circuit Board (PCB) (not shown).
In the application, the printed circuit board adopts a stack up structure of m + n + m or an x-layer Anylayer laminated structure, wherein m is more than or equal to 2, n is more than or equal to 2 and is an even number, and x is more than or equal to 6 and is an even number.
In the present embodiment, the DDR signal wiring board 20 includes a first wiring layer 21, a second wiring layer 22, a third wiring layer 23, and a fourth wiring layer 24. The first wiring layer 21, the second wiring layer 22, the third wiring layer 23 and the fourth wiring layer 24 are sequentially stacked from top to bottom.
In this embodiment, the DDR signal is a DDR signal of L PDDR4 (L ow Power Double Data Rate 4SDRAM) chip, and the DDR signal lines include four sets of Data lines, two sets of address lines, two sets of control lines, and a pair of clock lines.
Each group of Data lines includes a Data signal line (Data), a Data Strobe signal line (DQS), and a Data Mask Inversion line (DMI). Specifically, the first group of data lines includes: EBI0_ Data0-Data7, DQS0, DMI0, the second set of Data lines comprising: EBI0_ Data8-Data15, DQS1, DMI1, the third set of Data lines comprising: EBI1_ Data0-Data7, DQS0, DMI0, the fourth set of Data lines comprising: EBI1_ Data8-Data15, DQS1, DMI 1.
The two sets of address lines include: EBI0_ CA0-CA5 and EBI1_ CA0-CA 5.
The two sets of control lines and the pair of clock lines include EBI0_ CS, CKE, C L K, RESET and EBI1_ CS, CKE, C L K, RESET.
Where, CA is an abbreviation of Command Address, CS is an abbreviation of Command Select, CKE is an abbreviation of Clock Enable, and CK is an abbreviation of Clock.
Specifically, referring to fig. 1, fig. 1 is a schematic structural diagram of a first wiring layer 21 of a DDR signal wiring board 20 according to an embodiment of the present application. In this embodiment, the first wiring layer 21 is provided for the first data line 311 and the first power supply line 411 of the DDR signal lines.
In this embodiment, the first data lines 311 include data lines other than the data strobe signal lines DQS in each group of data lines, that is, the following four groups of data lines are laid on the first wiring layer 21: EBI0_ Data0-Data7, DMI0 in the first group of Data lines, EBI0_ Data8-Data15, DMI1 in the second group of Data lines, EBI1_ Data0-Data7, DMI0 in the third group of Data lines, and EBI1_ Data8-Data15, DMI1 in the fourth group of Data lines.
In this embodiment, the first power line 411 is wired as a power copper foil.
In the present embodiment, the layout position of the power copper foil of the first power line 411 on the first wiring layer 21 corresponds to the pad region of the power terminal of the memory device 11 of the electronic apparatus 100, for example, an eMCP chip.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a second wiring layer 22 of a DDR signal wiring board 20 according to an embodiment of the present application. In this embodiment, the second wiring layer 22 is used to provide the first ground plane 331.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a third wiring layer 23 of a DDR signal wiring board 20 according to an embodiment of the present application. In this embodiment, the third wiring layer 23 is provided for the address line 32, the control line 33, the clock line 34, the second data line 312, and the second power supply line 412 in the DDR signal lines.
In this embodiment, the second data lines 312 include data strobe signal lines DQS in each group of data lines, that is, the third wiring layer 23 is provided with two groups of address lines 32 EBI0_ CA0-CA5 and EBI1_ CA0-CA5, two groups of control lines 33 and a pair of clock lines 34 EBI0_ CS, CKE, C L K, RESET and EBI1_ CS, CKE, C L K, RESET, DQS0 in the first group of data lines, DQS1 in the second group of data lines, DQS0 in the third group of data lines, and DQS1 in the fourth group of data lines.
In this embodiment, the second power line 412 is wired as a power copper foil.
In the present embodiment, the position of the power copper foil of the second power supply line 412 disposed on the third wiring layer 23 is located between the gaps of the DDR signal lines on the third wiring layer 23.
Referring to fig. 4, fig. 4 is a schematic structural diagram of the fourth wiring layer 24 of the DDR signal wiring board 20 according to an embodiment of the present application. In this embodiment, the fourth wiring layer 24 is provided for providing the second ground plane 332 and the third power supply line 413.
In the present embodiment, the third power line 413 is wired as a power copper foil.
In the present embodiment, the layout position of the power copper foil of the third power line 413 on the fourth wiring layer 24 is located in the non-projection region of the DDR signal line on the third wiring layer 23 on the fourth wiring layer 24.
According to the DDR signal wiring board 20, the DDR signal wires are arranged on the first wiring layer and the third wiring layer, and the second wiring layer and the fourth wiring layer are arranged to form a complete ground plane, so that the signal integrity of the DDR signal wires is more reliable. In addition, the DDR power supply is arranged in the first, third, and fourth wiring layers without separately designing a DDR power supply plane layer, and the PND (power delivery Network) impedance of the power supply path is ensured to meet the design requirement, so that the number of wiring layers of the DDR signal wiring board 20 can be reduced, and the design cost can be reduced.
Further, in the DDR signal wiring board 20 of the present application, most of the data lines are routed in the first wiring layer 21, so that the number of wiring vias between chips can be reduced, and the quality of DDR signal transmission can be improved.
Furthermore, in the DDR signal wiring board 20 of the present application, the high-speed DQS signal line and the clock line 34 are disposed on the third wiring layer 23 and are microstrip lines, so that the DDR signal wiring board has a good EMI (electromagnetic interference) shielding effect.
Furthermore, in the DDR signal wiring board 20 of the present application, the sensitive control line 33 and the address line 32 are disposed in the third wiring layer 23, so that the adjacent wiring layers are all ground planes, which can effectively prevent external radiation interference.
In the present embodiment, the first data line 311, the two sets of address lines 32, and the two sets of control lines 33 are all designed as single-ended signal lines, and their control impedances are all designed as differential mode 45 ohms. The second data line 312 and the clock line 34 are both designed as differential signal lines, and their control impedances are both designed as differential 90 ohms. For example, each of the data lines DQS is two differential signal lines, one positive and one negative.
The current design requirement of L PDDR4 is to control the impedance of the signal line to 40 ohms, which requires the signal line to be made wide because the impedance of the signal line is inversely proportional to its width, and the line distance needs to be widened to reduce the signal crosstalk problem, which results in an excessively large wiring area on the wiring board, which is not favorable for adapting to the design requirement of the small electronic device.
The DDR signal wiring board 20 of the application makes the DDR single-ended signal line 45 ohm impedance control, and the differential mode 90 ohm impedance control is made to the differential signal line, so that the impedance control of the signal line is realized more easily, and the PCB is processed better.
In the present embodiment, the line width of the single-ended signal line on the first wiring layer 21 is designed to be equal to or greater than 60um, and the line pitch is designed to be twice the line width.
The line width of the single-ended signal line on the third wiring layer 23 is designed to be greater than or equal to 43um, and the line distance is designed to be 2.5 times of the line width.
The line width of the differential signal line on the third wiring layer 23 is designed to be greater than or equal to 43um, and the line distance is designed to be twice of the line width.
The DDR signal wiring board 20 of the application designs the line distance of the signal lines to be more than 2 times of the line width, can effectively reduce the signal crosstalk risk between the signal lines, and therefore can effectively improve the reliability of signals.
The embodiment of the present application also provides a printed circuit board (not shown) including any of the DDR signal wiring boards 20 described above. The printed circuit board adopts a stack up structure of m + n + m or an x-layer Anylayer laminated structure, wherein m is more than or equal to 2, n is more than or equal to 2 and is an even number, and x is more than or equal to 6 and is an even number. The DDR signal wiring board 20 is a part of the printed circuit board.
In the present embodiment, the stacked layer of the DDR signal wiring board 20 adopts a 2-stage HDI (High density interconnect) motherboard design, and a separate DDR power plane is not designed, so that the design order of the printed circuit board can be saved, and the design cost of the printed circuit board can be reduced.
As shown in fig. 1, an electronic apparatus 100 is further provided in the embodiment of the present application, and includes a storage device 11, a control device 12, and the printed circuit board. Wherein the storage device 11 comprises a plurality of data terminals, and the storage device 11 is used for storing data input from the data terminals. The control device 12 is configured to control the storage device 11 to access the data.
The printed circuit board is used for carrying the storage device 11 and the control device 12.
In this embodiment, the memory device 11 is L PDDR4 memory chip, and the L PDDR4 is a fourth generation low power double rate synchronous dynamic random access memory.
The control device 12 may be, for example, a device such as a CPU or a device integrating more functions than the CPU.
The electronic device 100 may be a mobile electronic product such as a smart phone, a tablet computer, or a notebook computer.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present application and not for limiting, and although the present application is described in detail with reference to the above preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present application without departing from the spirit and scope of the technical solutions of the present application.
Claims (10)
1. A DDR signal wiring board, characterized by comprising:
a first wiring layer for setting a first data line and a first power supply line in the DDR signal line;
a second wiring layer for providing a first ground plane;
the third wiring layer is used for setting an address line, a control line, a clock line, a second data line and a second power line in the DDR signal line;
a fourth wiring layer for providing a second ground plane and a third power supply line;
the first wiring layer, the second wiring layer, the third wiring layer and the fourth wiring layer are sequentially stacked from top to bottom;
the DDR signal line comprises four groups of data lines, and each group of data lines comprises a data signal line, a data strobe signal line and a data shielding reverse line; the first data lines include data lines except data strobe signal lines in each group of data lines, and the second data lines include data strobe signal lines in each group of data lines.
2. The DDR signal wiring board of claim 1, wherein the DDR signal is a DDR signal of L PDDR4 chips.
3. The DDR signal wiring board according to claim 1, wherein the first power supply line, the second power supply line, and the third power supply line are arranged as power supply copper foils.
4. The DDR signal wiring board of claim 3, wherein a layout position of the power supply copper foil of the first power supply line on the first wiring layer corresponds to a pad area of a power supply terminal of a memory device of an electronic apparatus; and/or
The arrangement position of the power copper foil of the second power line on the third wiring layer is positioned between gaps of the DDR signal lines on the third wiring layer; and/or
The layout position of the power copper foil of the third power line on the fourth wiring layer is located in a non-projection area of the DDR signal line on the third wiring layer on the fourth wiring layer.
5. The DDR signal wiring board of claim 1, wherein the first data line, the address line and the control line are all designed as single-ended signal lines, and the control impedances thereof are all designed as differential mode 45 ohms;
the second data line and the clock line are both designed as differential signal lines, and the control impedance of the second data line and the clock line is both designed as differential 90 ohms.
6. The DDR signal wiring board of claim 5, wherein a line width of the single-ended signal line on the first wiring layer is designed to be equal to or greater than 60um, and a line pitch is designed to be twice the line width.
7. The DDR signal wiring board of claim 5, wherein a line width of the single-ended signal line on the third wiring layer is designed to be 43um or more, and a line pitch is designed to be 2.5 times the line width.
8. The DDR signal wiring board of claim 5, wherein a line width of the differential signal lines on the third wiring layer is designed to be equal to or greater than 43um, and a line pitch is designed to be twice the line width.
9. A printed circuit board characterized by comprising at least the DDR signal wiring board according to any one of claims 1 to 8.
10. An electronic apparatus comprising a memory device, a controller device, and a printed circuit board for mounting the memory device and the controller device, characterized in that the printed circuit board comprises at least the DDR signal wiring board according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710970531.7A CN107845393B (en) | 2017-10-17 | 2017-10-17 | DDR signal wiring board, printed circuit board, and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710970531.7A CN107845393B (en) | 2017-10-17 | 2017-10-17 | DDR signal wiring board, printed circuit board, and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107845393A CN107845393A (en) | 2018-03-27 |
| CN107845393B true CN107845393B (en) | 2020-07-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710970531.7A Expired - Fee Related CN107845393B (en) | 2017-10-17 | 2017-10-17 | DDR signal wiring board, printed circuit board, and electronic device |
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| Country | Link |
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| CN (1) | CN107845393B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108566724B (en) * | 2018-06-13 | 2020-12-04 | 晶晨半导体（深圳）有限公司 | Wiring board for DDR memory, printed circuit board, and electronic device |
| CN111209654B (en) * | 2019-12-29 | 2023-05-09 | 苏州浪潮智能科技有限公司 | Power transmission network PDN frequency impedance test system and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102630118A (en) * | 2011-02-07 | 2012-08-08 | 索尼公司 | Laminated wiring board |
| CN203399401U (en) * | 2013-08-29 | 2014-01-15 | 上海市共进通信技术有限公司 | Printed circuit board structure realizing electromagnetic interference reduction during signal penetration |
| CN105578740A (en) * | 2016-02-25 | 2016-05-11 | 广东欧珀移动通信有限公司 | Single-sided rigid-flex board and mobile terminal |
-
2017
- 2017-10-17 CN CN201710970531.7A patent/CN107845393B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102630118A (en) * | 2011-02-07 | 2012-08-08 | 索尼公司 | Laminated wiring board |
| CN203399401U (en) * | 2013-08-29 | 2014-01-15 | 上海市共进通信技术有限公司 | Printed circuit board structure realizing electromagnetic interference reduction during signal penetration |
| CN105578740A (en) * | 2016-02-25 | 2016-05-11 | 广东欧珀移动通信有限公司 | Single-sided rigid-flex board and mobile terminal |
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| CN107845393A (en) | 2018-03-27 |
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Address after: Changan town in Guangdong province Dongguan 523860 usha Beach Road No. 18 Applicant after: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS Corp.,Ltd. Address before: Changan town in Guangdong province Dongguan 523860 usha Beach Road No. 18 Applicant before: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS Corp.,Ltd. |
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